LMK00306SQE/NOPB

LMK00306_16 TI1 | Alldatasheet

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Technical content

3:1 MUX SYNC CLKoutA0 CLKoutA0* CLKoutA2 CLKoutA2* CLKin0 CLKin0* CLKin1 CLKin1* OSCin OSCout REFout_EN CLKoutA_TYPE[1:0] CLKin_SEL[1:0] REFout (LVCMOS) GND VCCOA VCCOC VCC VCCOA VCCOB VCCOC Bank A (LVPECL, LVDS, HCSL, or Hi-Z) Universal Inputs (Differential/ Single-Ended) Crystal CLKoutB0 CLKoutB0* CLKoutB2 CLKoutB2* VCCOB CLKoutB_TYPE[1:0] 2 Bank B (LVPECL, LVDS, HCSL, or Hi-Z) CLKoutA1 CLKoutA1* CLKoutB1 CLKoutB1* 100 1000 10000 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT SWING (V) FREQUENCY (MHz) Vcco=2.5 V, Rterm=91 Vcco=3.3 V, Rterm=160 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK00306 SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 LMK003063-GHz6-OutputUltra-LowAdditiveJitter DifferentialClockBuffer/LevelTranslator

1 Features

1• 3:1 Input Multiplexer – Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks – One Crystal Input Accepts a 10 to 40 MHz Crystal or Single-Ended Clock

• Two Banks with 3 Differential Outputs Each – LVPECL, LVDS, HCSL, or Hi-Z (Selectable Per Bank) – LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz: – 20 fs RMS (10 kHz to 1 MHz) – 51 fs RMS (12 kHz to 20 MHz)
• High PSRR: -65 / -76 dBc (LVPECL/LVDS) at

156.25 MHz

• LVCMOS Output with Synchronous Enable Input
• Pin-Controlled Configuration
• VCC Core Supply: 3.3 V ± 5%
• 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
• Industrial Temperature Range: -40°C to +85°C
• 36-lead WQFN (6 mm × 6 mm)

2 Applications

• Clock Distribution and Level Translation for ADCs, DACs, Multi-Gigabit Ethernet, XAUI, Fibre Channel, SATA/SAS, SONET/SDH, CPRI, High- Frequency Backplanes
• Switches, Routers, Line Cards, Timing Cards
• Servers, Computing, PCI Express (PCIe 3.0)
• Remote Radio Units and Baseband Units

3 Description

The LMK00306 is a 3-GHz, 6-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 3 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00306 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies. The LMK00306 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMK00306 WQFN (36) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram LVPECL Output Swing (VOD) vs. Frequency

SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 www.ti.com Product Folder Links: LMK00306 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Table of Contents

10.2 Current Consumption and Power Dissipation

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (May 2013) to Revision D Page

• Added, updated, or renamed the following sections: Specifications; Detailed Description; Application and Implementation; Power Supply Recommendations; Device and Documentation Support; Mechanical, Packaging,
• Added “Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz”parameter with 100 MHz and 156.25 MHz
• Added “Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz”parameter with 100 MHz and 156.25 MHz Changes from Revision B (February 2013) to Revision C Page
• Changed Target Applications by adding additional applications to the second and third bullets, and removing High-
• Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better

www.ti.com SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 Product Folder Links: LMK00306 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated

• Added text to second paragraph of Termination for AC Coupled Differential Operation to explain graphic update to

CLKin_SEL0 CLKin_SEL1 CLKoutB2 CLKoutB0* CLKoutB0 GND CLKin1* REFout_EN GND VCCOA CLKoutA0 CLKoutA0* CLKoutA1 CLKoutA1* CLKoutA2 CLKoutA2* CLKoutA_TYPE0 VCC OSCout CLKin0 CLKin0* CLKoutB_TYPE0 CLKoutB2* CLKoutB1* CLKoutB1 VCCOB VCCOB CLKoutB_TYPE1 CLKin1 VCC REFout VCCOC CLKoutA_TYPE1 3536 34 33 32 31 30 29 28 1110 12 13 14 15 16 17 18 DAP Top Down View GND LMK00306 SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 www.ti.com Product Folder Links: LMK00306 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

www.ti.com SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 Product Folder Links: LMK00306 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated (1) Any unused output pins should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration or Termination and Use of Clock Drivers for output interface and termination techniques. (2) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type. (3) CMOS control input with internal pull-down resistor. Pin Functions(1) PIN TYPE DESCRIPTION NO. NAME DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation. 1, 19, 28 GND GND Ground 2, 5 VCCOA PWR Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (2) 3, 4 CLKoutA0, CLKoutA0* O Differential clock output A0. Output type set by CLKoutA_TYPE pins. 6, 7 CLKoutA1, CLKoutA1* O Differential clock output A1. Output type set by CLKoutA_TYPE pins. 8, 9 CLKoutA2, CLKoutA2* O Differential clock output A2. Output type set by CLKoutA_TYPE pins. 10, 36 CLKoutA_TYPE0, CLKoutA_TYPE1 I Bank A output buffer type selection pins (3) 11, 32 Vcc PWR Power supply for Core and Input buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin. 12 OSCin I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock. 13 OSCout O Output for crystal. Leave OSCout floating if OSCin is driven by a single- ended clock. 14, 17 CLKin_SEL0, CLKin_SEL1 I Clock input selection pins (3) 15, 16 CLKin0, CLKin0* I Universal clock input 0 (differential/single-ended) 18, 29 CLKoutB_TYPE0, CLKoutB_TYPE1 I Bank B output buffer type selection pins (3) 20, 21 CLKoutB2*, CLKoutB2 O Differential clock output B2. Output type set by CLKoutB_TYPE pins. 22, 23 CLKoutB1*, CLKoutB1 O Differential clock output B1. Output type set by CLKoutB_TYPE pins. 24, 27 VCCOB PWR Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (2) 25, 26 CLKoutB0*, CLKoutB0 O Differential clock output B0. Output type set by CLKoutB_TYPE pins. 30, 31 CLKin1*, CLKin1 I Universal clock input 1 (differential/single-ended) 33 REFout O LVCMOS reference output. Enable output by pulling REFout_EN pin high.

34 VCCOC PWR

Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (2) 35 REFout_EN I REFout enable input. Enable signal is internally synchronized to selected clock input. (3)

SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 www.ti.com Product Folder Links: LMK00306 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2) MIN MAX UNIT VCC, VCCO Supply Voltages -0.3 3.6 V VIN Input Voltage -0.3 (VCC + 0.3) V TSTG Storage Temperature -65 +150 °C TL Lead Temperature (solder 4 s) +260 °C TJ Junction Temperature +150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VMachine model (MM) ±150 Charged-device model (CDM), per JEDEC specification JESD22- C101(2) ±750 (1) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type. (2) Vcco should be less than or equal to Vcc (Vcco ≤ Vcc).

6.3 Recommended Operating Conditions

PARAMETER MIN TYP MAX UNIT TA Ambient Temperature Range -40 25 85 °C TJ Junction Temperature 125 °C VCC Core Supply Voltage Range 3.15 3.3 3.45 V VCCO Output Supply Voltage Range (1)(2) 3.3 – 5% 2.5 – 5% 3.3 2.5 3.3 + 5% 2.5 + 5% V (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) Specification assumes 9 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the package. It is recommended that the maximum number of vias be used in the board layout.

6.4 Thermal Information

THERMAL METRIC(1)(2) NJK0036A (WQFN) UNIT

36 PINS

RθJA Junction-to-ambient thermal resistance 31.8 °C/W RθJC(top) (DAP) Junction-to-case (top) thermal resistance 7.2

www.ti.com SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 Product Folder Links: LMK00306 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated (1) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type. (2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. (3) See Power Supply Recommendations for more information on current consumption and power dissipation calculations. (4) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 * 10(PSRR / 20)) / (π * fCLK) ] * 1E12

6.5 Electrical Characteristics

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION(3) ICC_CORE Core Supply Current, All Outputs Disabled CLKinX selected 8.5 10.5 mA OSCin selected 10 13.5 mA ICC_PECL Additive Core Supply Current, Per LVPECL Bank Enabled 20 26.5 mA ICC_LVDS Additive Core Supply Current, Per LVDS Bank Enabled 24 29.5 mA ICC_HCSL Additive Core Supply Current, Per HCSL Bank Enabled 29 35 mA ICC_CMOS Additive Core Supply Current, LVCMOS Output Enabled 3.5 5.5 mA ICCO_PECL Additive Output Supply Current, Per LVPECL Bank Enabled Includes Output Bank Bias and Load Currents, RT = 50 Ω to Vcco - 2V on all outputs in bank 100 123 mA ICCO_LVDS Additive Output Supply Current, Per LVDS Bank Enabled 20 27.5 mA ICCO_HCSL Additive Output Supply Current, Per HCSL Bank Enabled Includes Output Bank Bias and Load Currents, RT = 50 Ω on all outputs in bank 50 65 mA ICCO_CMOS Additive Output Supply Current, LVCMOS Output Enabled

200 MHz, CL = 5 pF

Vcco = 3.3 V ± 5% 9 10 mA Vcco = 2.5 V ± 5% 7 8 mA POWER SUPPLY RIPPLE REJECTION (PSRR) PSRRPECL Ripple-Induced Phase Spur Level Differential LVPECL Output(4) 100 kHz, 100 mVpp Ripple Injected on Vcco, Vcco = 2.5 V

156.25 MHz -65

312.5 MHz -63

LVDS Output(4)

156.25 MHz -76

312.5 MHz -74

HCSL Output(4)

156.25 MHz -72

CMOS CONTROL INPUTS (CLKin_SELn, CLKoutX_TYPEn, REFout_EN) VIH High-Level Input Voltage 1.6 Vcc V VIL Low-Level Input Voltage GND 0.4 V IIH High-Level Input Current VIH = Vcc, Internal pull-down resistor 50 µA IIL Low-Level Input Current VIL = 0 V, Internal pull-down resistor -5 0.1 µA

SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 www.ti.com Product Folder Links: LMK00306 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (5) Specification is ensured by characterization and is not tested in production. (6) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages. (7) Parameter is specified by design, not tested in production. (8) For clock input frequency ≥ 100 MHz, CLKinX can be driven with single-ended (LVCMOS) input swing up to 3.3 Vpp. For clock input frequency < 100 MHz, the single-ended input swing should be limited to 2 Vpp max to prevent input saturation (refer to Driving the Clock Inputs for interfacing 2.5 V/3.3 V LVCMOS clock input < 100 MHz to CLKinX). (9) The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal Interface for crystal drive level considerations. CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*) fCLKin Input Frequency Range(5) Functional up to 3.1 GHz Output frequency range and timing specified per output type (refer to LVPECL, LVDS, HCSL, LVCMOS output specifications) DC 3.1 GHz VIHD Differential Input High Voltage CLKin driven differentially Vcc V VILD Differential Input Low Voltage GND V VID Differential Input Voltage Swing(6) 0.15 1.3 V VCMD Differential Input Common Mode Voltage VID = 150 mV 0.25 Vcc - 1.2 VVID = 350 mV 0.25 Vcc - 1.1 VID = 800 mV 0.25 Vcc -0.9 VIH Single-Ended Input High Voltage CLKinX driven single-ended (AC or DC coupled), CLKinX* AC coupled to GND or externally biased within VCM range Vcc V VIL Single-Ended Input Low Voltage GND V VI_SE Single-Ended Input Voltage Swing(7)(8) 0.3 2 Vpp VCM Single-Ended Input Common Mode Voltage 0.25 Vcc - 1.2 V ISOMUX Mux Isolation, CLKin0 to CLKin1 fOFFSET > 50 kHz, PCLKinX = 0 dBm fCLKin0 = 100 MHz -84 dBc fCLKin0 = 200 MHz -82 fCLKin0 = 500 MHz -71 fCLKin0 = 1000 MHz -65 CRYSTAL INTERFACE (OSCin, OSCout) FCLK External Clock Frequency Range(5) OSCin driven single-ended, OSCout floating 250 MHz FXTAL Crystal Frequency Range Fundamental mode crystal ESR ≤ 200 Ω (10 to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)(9) 10 40 MHz CIN OSCin Input Capacitance 4 pF

www.ti.com SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 Product Folder Links: LMK00306 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (10) See Typical Characteristics for output operation over frequency. (11) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT - JSOURCE 2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10dBc/10) / (2*π*fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer to the “Noise Floor vs. CLKin Slew Rate”and “RMS Jitter vs. CLKin Slew Rate”plots in Typical Characteristics. (12) 100 MHz and 156.25 MHz input source from Rohde & Schwarz SMA100A Low-Noise Signal Generator and Sine-to-Square-wave Conversion block. (13) 156.25 MHz LVPECL clock source from LMK03806 with 20 MHz crystal reference (crystal part number: ECS-200-20-30BU-DU). JSOURCE = 190 fs RMS (10 kHz to 1 MHz) and 195 fs RMS (12 kHz to 20 MHz). Refer to the LMK03806 datasheet for more information. (14) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations. (15) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs. LVPECL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) fCLKout_FS Maximum Output Frequency Full VOD Swing(5)(10) VOD ≥ 600 mV, RL = 100 Ω differential Vcco = 3.3 V ± 5%, RT = 160 Ω to GND 1.0 1.2 GHz Vcco = 2.5 V ± 5%, RT = 91 Ω to GND 0.75 1.0 fCLKout_RS Maximum Output Frequency Reduced VOD Swing(5)(10) VOD ≥ 400 mV, RL = 100 Ω differential Vcco = 3.3 V ± 5%, RT = 160 Ω to GND 1.5 3.1 GHz Vcco = 2.5 V ± 5%, RT = 91 Ω to GND 1.5 2.3 JitterADD Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz(5)(11)(12) Vcco = 2.5 V ± 5%: RT = 91 Ω to GND, Vcco = 3.3 V ± 5%: RT = 160 Ω to GND, RL = 100 Ω differential CLKin: 100 MHz, Slew rate ≥ 3 V/ns 77 98 fs CLKin: 156.25 MHz, Slew rate ≥ 3 V/ns 54 78 JitterADD Additive RMS Jitter Integration Bandwidth

1 MHz to 20 MHz(11)

Vcco = 3.3 V, RT = 160 Ω to GND, RL = 100 Ω differential CLKin: 100 MHz, Slew rate ≥ 3 V/ns 59 fsCLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns 64 CLKin: 625 MHz, Slew rate ≥ 3 V/ns 30 JitterADD Additive RMS Jitter with LVPECL clock source from LMK03806(11)(13) Vcco = 3.3 V, RT = 160 Ω to GND, RL = 100 Ω differential CLKin: 156.25 MHz, JSOURCE = 190 fs RMS (10 kHz to 1 MHz) fs CLKin: 156.25 MHz, JSOURCE = 195 fs RMS (12 kHz to 20 MHz) Noise Floor Noise Floor fOFFSET ≥ 10 MHz(14)(15) Vcco = 3.3 V, RT = 160 Ω to GND, RL = 100 Ω differential CLKin: 100 MHz, Slew rate ≥ 3 V/ns -162.5 dBc/HzCLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns -158.1 CLKin: 625 MHz, Slew rate ≥ 3 V/ns -154.4 DUTY Duty Cycle(5) 50% input clock duty cycle 45% 55% VOH Output High Voltage TA = 25 °C, DC Measurement, RT = 50 Ω to Vcco - 2 V Vcco - 1.2 Vcco - 0.9 Vcco - 0.7 V VOL Output Low Voltage Vcco - 2.0 Vcco - 1.75 Vcco - 1.5 V VOD Output Voltage Swing(6) 600 830 1000 mV

SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 www.ti.com Product Folder Links: LMK00306 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tR Output Rise Time 20% to 80%(7) RT = 160 Ω to GND, Uniform transmission line up to 10 in. with 50-Ω characteristic impedance, RL = 100 Ω differential,CL ≤ 5 pF 175 300 ps tF Output Fall Time 80% to 20%(7) 175 300 ps LVDS OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) fCLKout_FS Maximum Output Frequency Full VOD Swing(5)(10) VOD ≥ 250 mV, RL = 100 Ω differential 1.0 1.6 GHz fCLKout_RS Maximum Output Frequency Reduced VOD Swing(5)(10) VOD ≥ 200 mV, RL = 100 Ω differential 1.5 2.1 GHz JitterADD Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz(5)(11)(12) RL = 100 Ω differential CLKin: 100 MHz, Slew rate ≥ 3 V/ns 94 115 fs CLKin: 156.25 MHz, Slew rate ≥ 3 V/ns 70 90 JitterADD Additive RMS Jitter Integration Bandwidth Vcco = 3.3 V, RL = 100 Ω differential CLKin: 100 MHz, Slew rate ≥ 3 V/ns 89 fsCLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns 77 CLKin: 625 MHz, Slew rate ≥ 3 V/ns 37 Noise Floor Noise Floor fOFFSET ≥ 10 MHz(14)(15) Vcco = 3.3 V, RL = 100 Ω differential CLKin: 100 MHz, Slew rate ≥ 3 V/ns -159.5 dBc/HzCLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns -157.0 CLKin: 625 MHz, Slew rate ≥ 3 V/ns -152.7 DUTY Duty Cycle(5) 50% input clock duty cycle 45% 55% VOD Output Voltage Swing(6) TA = 25 °C, DC Measurement, RL = 100 Ω differential 250 400 450 mV ΔVOD Change in Magnitude of VOD for Complementary Output States -50 50 mV VOS Output Offset Voltage 1.125 1.25 1.375 V ΔVOS Change in Magnitude of VOS for Complementary Output States -35 35 mV ISA ISB Output Short Circuit Current Single Ended TA = 25 °C, Single ended outputs shorted to GND -24 24 mA ISAB Output Short Circuit Current Differential Complementary outputs tied together -12 12 mA tR Output Rise Time 20% to 80%(7) Uniform transmission line up to 10 inches with 50- Ω characteristic impedance, RL = 100 Ω differential, CL ≤ 5 pF 175 300 ps tF Output Fall Time 80% to 20%(7) 175 300 ps

www.ti.com SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 Product Folder Links: LMK00306 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (16) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading. HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) fCLKout Output Frequency Range(5) RL = 50 Ω to GND, CL ≤ 5 pF DC 400 MHz JitterADD_PCIe Additive RMS Phase Jitter for PCIe 3.0(5) PCIe Gen 3, PLL BW = 2–5 MHz, CDR = 10 MHz CLKin: 100 MHz, Slew rate ≥ 0.6 V/ns 0.03 0.15 ps JitterADD Additive RMS Jitter Integration Bandwidth Vcco = 3.3 V, RT = 50 Ω to GND CLKin: 100 MHz, Slew rate ≥ 3 V/ns 77 fs CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns 86 Noise Floor Noise Floor fOFFSET ≥ 10 MHz(14)(15) Vcco = 3.3 V, RT = 50 Ω to GND CLKin: 100 MHz, Slew rate ≥ 3 V/ns -161.3 dBc/Hz CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns -156.3 DUTY Duty Cycle(5) 50% input clock duty cycle 45% 55% VOH Output High Voltage TA = 25 °C, DC Measurement, RT = 50 Ω to GND 520 810 920 mV VOL Output Low Voltage -150 0.5 150 mV VCROSS Absolute Crossing Voltage(5)(16) RL = 50 Ω to GND, CL ≤ 5 pF 160 350 460 mV ΔVCROSS Total Variation of VCROSS (5)(16) 140 mV tR Output Rise Time 20% to 80%(7)(16) 250 MHz, Uniform transmission line up to 10 inches with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF 300 500 ps tF Output Fall Time 80% to 20%(7)(16) 300 500 ps

SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 www.ti.com Product Folder Links: LMK00306 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (17) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement. LVCMOS OUTPUT (REFout) fCLKout Output Frequency Range(5) CL ≤ 5 pF DC 250 MHz JitterADD Additive RMS Jitter Integration Bandwidth Vcco = 3.3 V, CL ≤ 5 pF 100 MHz, Input Slew rate ≥ 3 V/ns 95 fs Noise Floor Noise Floor fOFFSET ≥ 10 MHz(14)(15) Vcco = 3.3 V, CL ≤ 5 pF 100 MHz, Input Slew rate ≥ 3 V/ns -159.3 dBc/Hz DUTY Duty Cycle(5) 50% input clock duty cycle 45% 55% VOH Output High Voltage 1 mA load Vcco - 0.1 V VOL Output Low Voltage 0.1 V IOH Output High Current (Source) Vo = Vcco / 2 Vcco = 3.3 V 28 mA Vcco = 2.5 V 20 IOL Output Low Current (Sink) Vcco = 3.3 V 28 mA Vcco = 2.5 V 20 tR Output Rise Time 20% to 80%(7)(16) 250 MHz, Uniform transmission line up to 10 inches with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF 225 400 ps tF Output Fall Time 80% to 20%(7)(16) 225 400 ps tEN Output Enable Time(17) CL ≤ 5 pF 3 cycles tDIS Output Disable Time(17) 3 cycles

www.ti.com SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 Product Folder Links: LMK00306 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (18) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions. PROPAGATION DELAY and OUTPUT SKEW tPD_PECL Propagation Delay CLKin-to-LVPECL(7) RT = 160 Ω to GND, RL = 100 Ω differential, CL ≤ 5 pF 180 360 540 ps tPD_LVDS Propagation Delay CLKin-to-LVDS(7) RL = 100 Ω differential, CL ≤ 5 pF 200 400 600 ps tPD_HCSL Propagation Delay CLKin-to-HCSL(7)(16) RT = 50 Ω to GND, CL ≤ 5 pF 295 590 885 ps tPD_CMOS Propagation Delay CLKin-to-LVCMOS(7)(16) CL ≤ 5 pF Vcco = 3.3 V 900 1475 2300 ps Vcco = 2.5 V 1000 1550 2700 tSK(O) Output Skew LVPECL/LVDS/HCSL (5)(16)(18) Skew specified between any two CLKouts with the same buffer type. Load conditions per output type are the same as propagation delay specifications. 30 50 ps tSK(PP) Part-to-Part Output Skew LVPECL/LVDS/HCSL (7)(16)(18) 80 120 ps

6.6 Typical Characteristics

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Consult Table 1 at the end of Typical Characteristics for graph footnotes. Figure 1. LVPECL Output Swing (VOD) vs. Frequency Figure 2. LVDS Output Swing (VOD) vs. Frequency Figure 3. LVPECL Output Swing @ 156.25 MHz Figure 4. LVDS Output Swing @ 156.25 MHz Figure 5. LVPECL Output Swing @ 1.5 GHz Figure 6. LVDS Output Swing @ 1.5 GHz

20 MHz Crystal

40 MHz Crystal

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Consult Table 1 at the end of Typical Characteristics for graph footnotes. Figure 19. LVDS Phase Noise @ 100 MHz Figure 20. HCSL Phase Noise @ 100 MHz Figure 21. Crystal Power Dissipation vs. RLIM See Notes 2 and 3 in Graph Notes table. Figure 22. LVDS Phase Noise in Crystal Mode Table 1. Graph Notes measured (40 Ω max), and Drive Level = 1 mW max (100 µW typical). measured (40 Ω max), and Drive Level = 1 mW max (100 µW typical).

7 Parameter Measurement Information

7.1 Differential Voltage Measurement Terminology

different definitions when used. an input or output voltage is being described. be calculated as twice the value of VOD as described in the first description. to-peak voltage of the differential signal can be measured. VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP). Figure 23. Two Different Definitions for Differential Input Signals Figure 24. Two Different Definitions for Differential Output Signals their Definitions, for more information.

3:1 MUX SYNC CLKoutA0 CLKoutA0* CLKoutA2 CLKoutA2* CLKin0 CLKin0* CLKin1 CLKin1* OSCin OSCout REFout_EN CLKoutA_TYPE[1:0] CLKin_SEL[1:0] REFout (LVCMOS) GND VCCOA VCCOC VCC VCCOA VCCOB VCCOC Bank A (LVPECL, LVDS, HCSL, or Hi-Z) Universal Inputs (Differential/ Single-Ended) Crystal CLKoutB0 CLKoutB0* CLKoutB2 CLKoutB2* VCCOB CLKoutB_TYPE[1:0] 2 Bank B (LVPECL, LVDS, HCSL, or Hi-Z) CLKoutA1 CLKoutA1* CLKoutB1 CLKoutB1* LMK00306 www.ti.com SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 Product Folder Links: LMK00306 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The LMK00306 is a 6-output differential clock fanout buffer with low additive jitter that can operate up to 3.1 GHz. It features a 3:1 input multiplexer with an optional crystal oscillator input, two banks of 3 differential outputs with multi-mode buffers (LVPECL, LVDS, HCSL, or Hi-Z), one LVCMOS output, and 3 independent output buffer supplies. The input selection and output buffer modes are controlled via pin strapping. The device is offered in a 36-pin WQFN package and leverages much of the high-speed, low-noise circuit design employed in the LMK04800 family of clock conditioners.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 VCC and VCCO Power Supplies

such as power dissipation, power supply bypassing, and power supply ripple rejection (PSRR). prevent turning-on the internal ESD protection circuitry.

8.3.2 Clock Inputs

Table 2. Input Selection

1 X OSCin

Table 3 shows the output logic state vs. input state when either CLKin0/CLKin0* or CLKin1/CLKin1* is selected. When OSCin is selected, the output state will be an inverted copy of the OSCin input state. Table 3. CLKin Input vs. Output States

8.3.3 Clock Outputs

Termination and Use of Clock Drivers for more information on output interface and termination techniques. keep the IC level during reflow. Table 4. Differential Output Buffer Type Selection

8.3.3.1 Reference Output

REFout_EN, as shown in Table 5. Table 5. Reference Output Enable

0 Disabled (Hi-Z)

1 Enabled

will be disabled within 3 cycles (tDIS) of the input clock after REFout_EN is toggled low. When REFout is disabled, the use of a resistive loading can be used to set the output to a predetermined level.

0.1 PFR SCMOS

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Driving the Clock Inputs

range. Refer to Termination and Use of Clock Drivers for signal interfacing and termination techniques. rate of 3 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. Slew Rate”plots in Typical Characteristics. 50 Ω to match the characteristic impedance of the transmission line and load termination. Figure 25. Single-Ended LVCMOS Input, AC Coupling where the input slew rate is the highest. delay, Td, of the 50Ω transmission line, where CAC >= 3*Td/50Ω.

0.1 PF50:Trace

0.1 PFR S

Figure 26. Single-Ended LVCMOS Input, DC Coupling over supply voltage and temperature variations. Figure 27. Driving OSCin with a Single-Ended Input

9.2 Crystal Interface

crystal interface is shown in Figure 28. Figure 28. Crystal Interface ~ 1~3 pF) can affect the discrete load capacitor values, C1 and C2.

level necessary to start-up and maintain steady-state operation.

• IRMS is the RMS current through the crystal.
• RESR is the max. equivalent series resistance specified for the crystal
• CL is the load capacitance specified for the crystal
• C0 is the min. shunt capacitance specified for the crystal (4) IRMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active. As shown in Figure 28 , an external resistor, RLIM, can be used to limit the crystal drive level, if necessary. If the power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a suggested value for RLIM is 1.5 kΩ.

9.3 Termination and Use of Clock Drivers

• Transmission line theory should be followed for good impedance matching to prevent reflections.
• Clock drivers should be presented with the proper loads. – LVDS outputs are current drivers and require a closed current loop. – HCSL drivers are switched current outputs and require a DC path to ground via 50 Ω termination. – LVPECL outputs are open emitter and require a DC path to ground.
• Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level; in this case, the signal should normally be AC coupled. It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure the receiver is biased at the optimum DC voltage (common mode voltage).

9.3.1 Termination for DC Coupled Differential Operation

Figure 29. Differential LVDS Operation, DC Coupling,

(b) LVDS DC termination with AC coupling at source and internal termination at load. Double termination at source and load will reduce swing by half.

9.3.2 Termination for AC Coupled Differential Operation

to ensure the receiver is biased to its ideal DC level. termination resistors or not. should be placed before the AC coupling capacitors for proper DC biasing of the driver as shown in Figure 34. recommended to meet the minimum input swing required by the self-terminated receiver. adjusted to meet the startup requirements for the particular application. Figure 33. Differential LVDS Operation with AC Coupling Figure 34. Differential LVDS Operation with AC Coupling input common mode voltage of the receiver.

Figure 35. Differential LVPECL Operation, AC Coupling,

9.3.3 Termination for Single-Ended Operation

unbalanced, single-ended signal. Figure 36. The Thevenin equivalent circuit is also a valid termination as shown in Figure 37 for Vcco = 3.3 V. Figure 36. Single-Ended LVPECL Operation, DC Coupling Figure 37. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent

termination the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 38. Figure 38. Single-Ended LVPECL Operation, AC Coupling

10 Power Supply Recommendations

10.1 Power Supply Sequencing

flow from Vcc to Vcco pins that could occur when Vcc is powered before Vcco.

10.2 Current Consumption and Power Dissipation Calculations

• ICC_CORE is the current for core logic and input blocks and depends on selected input (CLKinX or OSCin).
• ICC_BANK_A is the current for Bank A and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0 mA if disabled).
• ICC_BANK_B is the current for Bank B and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0 mA if disabled).
• ICC_CMOS is the current for the LVCMOS output (or 0 mA if REFout is disabled). (5) Since the output supplies (VCCOA, VCCOB, VCCOC) can be powered from 3 independent voltages, the respective output supply currents (ICCO_BANK_A, ICCO_BANK_B, and ICCO_CMOS) should be calculated separately. ICCO_BANK for either Bank A or B can be directly taken from the corresponding output supply current spec (ICCO_PECL, ICCO_LVDS, or ICCO_HCSL) provided the output loading matches the specified conditions. Otherwise, ICCO_BANK should be calculated as follows: ICCO_BANK = IBANK_BIAS + (N * IOUT_LOAD) where
• IBANK_BIAS is the output bank bias current (fixed value).
• IOUT_LOAD is the DC load current per loaded output pair.
• N is the number of loaded output pairs per bank (N = 0 to 3). (6) Table 6 shows the typical IBANK_BIAS values and IOUT_LOAD expressions for LVPECL, LVDS, and HCSL. For LVPECL, it is possible to use a larger termination resistor (RT) to ground instead of terminating with 50 Ω to VTT = Vcco - 2 V; this technique is commonly used to eliminate the extra termination voltage supply (VTT) and potentially reduce device power dissipation at the expense of lower output swing. For example, when Vcco is 3.3 V, a RT value of 160 Ω to ground will eliminate the 1.3 V termination supply without sacrificing much output swing. In this case, the typical IOUT_LOAD is 25 mA, so ICCO_PECL for a fully-loaded bank reduces to 95 mA (vs. 100 mA with 50 Ω resistors to Vcco – 2 V).

Table 6. Typical Output Bank Bias and Load Currents

SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 www.ti.com Product Folder Links: LMK00306 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated If the device is configured with LVPECL or HCSL outputs, then it is also necessary to calculate the power dissipated in any termination resistors (PRT_ PECL and PRT_HCSL) and in any LVPECL termination voltages (PVTT_PECL). The external power dissipation values can be calculated as follows: PRT_PECL (per LVPECL pair) = (VOH - VTT)2/RT + (VOL - VTT)2/RT (8) PVTT_PECL (per LVPECL pair) = VTT * [(VOH - VTT)/RT + (VOL - VTT)/RT] (9) PRT_HCSL (per HCSL pair) = VOH 2 / RT (10) Finally, the IC power dissipation (PDEVICE) can be computed by subtracting the external power dissipation values from PTOTAL as follows: PDEVICE = PTOTAL - N1*(PRT_PECL + PVTT_PECL) - N2*PRT_HCSL where

• N1 is the number of LVPECL output pairs with termination resistors to VTT (usually Vcco - 2 V or GND).
• N2 is the number of HCSL output pairs with termination resistors to GND. (11)

10.2.1 Power Dissipation Example: Worst-Case Dissipation

This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power dissipation. In this case, the maximum supply voltage and supply current values specified in Electrical Characteristics are used.

• VCC = VCCO = 3.465 V. Max ICC and ICCO values.
• CLKin0/CLKin0* input is selected.
• Banks A and B are configured for LVPECL: all outputs terminated with 50 Ω to VT = Vcco - 2 V.
• REFout is enabled with 5 pF load.
• TA = 85 °C Using the power calculations from the previous section and maximum supply current specifications, we can compute PTOTAL and PDEVICE.
• From Equation 5: ICC_TOTAL = 10.5 mA + 22.5 mA + 22.5 mA + 5.5 mA = 61 mA
• From ICCO_PECL max spec: ICCO_BANK_A = ICCO_BANK_B = 115 mA
• From Equation 7: PTOTAL = 3.465 V * (61 mA + 115 mA + 115 mA + 10 mA) = 1043 mW (per output pair)
• From Equation 10: PRT_HCSL = 0 mW (no HCSL outputs)
• From Equation 11: PDEVICE = 1043 mW - (6 * (25.5 mW + 39.5 mW)) - 0 mW = 653 mW In this worst-case example, the IC device will dissipate about 653 mW or 63% of the total power (1043 mW), while the remaining 37% will be dissipated in the LVPECL emitter resistors (153 mW for 6 pairs) and termination voltage (237 mW into Vcco - 2 V). Based on θJA of 31.8 °C/W, the estimated die junction temperature would be about 21 °C above ambient, or 106 °C when TA = 85 °C.

10.3 Power Supply Bypassing

The Vcc and Vcco power supplies should have a high-frequency bypass capacitor, such as 0.1 uF or 0.01 uF, placed very close to each supply pin. 1 uF to 10 uF decoupling capacitors should also be placed nearby the device between the supply and ground planes. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance.

10.3.1 Power Supply Ripple Rejection

In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00306, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc).

PSRR test setup is shown in Figure 39. Figure 39. PSRR Test Setup

• Ripple amplitude: 100 mVpp on Vcco = 2.5 V
• Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [(2*10(PSRR / 20)) / (π*fCLK)] * 1012 (12) The “PSRR vs. Ripple Frequency” plots in Typical Characteristics show the ripple-induced phase spur levels for the differential output types at 156.25 MHz and 312.5 MHz . The LMK00306 exhibits very good and well-behaved PSRR characteristics across the ripple frequency range for all differential output types. The phase spur levels for LVPECL are below -64 dBc at 156.25 MHz and below -62 dBc at 312.5 MHz. Using Equation 12, these phase spur levels translate to Deterministic Jitter values of 2.57 ps pk-pk at 156.25 MHz and 1.62 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the device improves for Vcco = 3.3 V under the same ripple amplitude and frequency conditions.

10.4 Thermal Management

estimate, TA (ambient temperature) plus device power dissipation times RθJA should not exceed 125 °C. package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

www.ti.com SNAS578D –FEBRUARY 2012–REVISED MARCH 2016 Product Folder Links: LMK00306 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

Common Data Transmission Parameters and their Definitions, Application Note AN-912 (SNLA036)

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 6-Mar-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMK00306SQ/NOPB ACTIVE WQFN NJK 36 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K00306 LMK00306SQE/NOPB ACTIVE WQFN NJK 36 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K00306 LMK00306SQX/NOPB ACTIVE WQFN NJK 36 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K00306 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 6-Mar-2015 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 6-Mar-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK00306SQ/NOPB WQFN NJK 36 1000 367.0 367.0 38.0 LMK00306SQE/NOPB WQFN NJK 36 250 213.0 191.0 55.0 LMK00306SQX/NOPB WQFN NJK 36 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Mar-2015 Pack Materials-Page 2

www.ti.com SQA36A (Rev A)

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