LMK00301SQE/NOPB

LMK00301_13 TI1 | Alldatasheet

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3:1 MUX SYNC CLKoutA0 CLKoutA0* CLKoutA4 CLKoutA4* CLKin0 CLKin0* CLKin1 CLKin1* OSCin OSCout REFout_EN CLKoutA_TYPE[1:0] CLKin_SEL[1:0] REFout (LVCMOS) GND VCCOA VCCOC VCC VCCOA VCCOB VCCOC Bank A

5 Output Pairs

(LVPECL, LVDS, HCSL, or Hi-Z) Universal Inputs (Differential/ Single-Ended) Crystal CLKoutB0 CLKoutB0* CLKoutB4 CLKoutB4* VCCOB CLKoutB_TYPE[1:0] 2 Bank B (LVPECL, LVDS, HCSL, or Hi-Z) LMK00301 www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 LMK003013-GHz10-OutputDifferentialClockBuffer/LevelTranslator Check forSamples: LMK00301 1FEATURES TARGET APPLICATIONS 2• 3:1InputMultiplexer • Clock Distributionand LevelTranslationfor ADCs, DACs, Multi-GigabitEthernet,XAUI,– Two UniversalInputsOperate up to3.1GHz FibreChannel,SATA/SAS, SONET/SDH, CPRI,and Accept LVPECL, LVDS, CML, SSTL, High-FrequencyBackplanesHSTL, HCSL, or Single-EndedClocks

Switches,Routers,LineCards,Timing Cards– One CrystalInputAccepts 10 to40 MHz Crystalor Single-EndedClock • Servers,Computing, PCI Express (PCIe3.0)
Two Banks with5 DifferentialOutputs Each • Remote Radio Unitsand Baseband Units – LVPECL, LVDS, HCSL, or Hi-Z(Selectable DESCRIPTIONPer Bank) The LMK00301 is a 3-GHz, 10-outputdifferential– LVPECL AdditiveJitterwithLMK03806 fanoutbufferintendedforhigh-frequency,low-jitterClock Source at156.25MHz: clock/datadistributionand leveltranslation.The input– 20 fsRMS (10kHz – 1 MHz) clockcan be selectedfrom two universalinputsor one crystalinput.The selected input clock is– 51 fsRMS (12kHz – 20 MHz) distributedto two banks of 5 differentialoutputsand• High PSRR: -65/-76dBc (LVPECL/LVDS) at one LVCMOS output.Both differentialoutputbanks156.25MHz can be independentlyconfiguredas LVPECL, LVDS,• LVCMOS Output withSynchronous Enable or HCSL drivers,or disabled.The LVCMOS output Input has a synchronousenable inputforrunt-pulse-free operationwhen enabledor disabled.The LMK00301• Pin-ControlledConfiguration
3 IndependentVCCO Output Supplies:3.3V/2.5 The LMK00301 provides high performance,V ± 5% versatility,and power efficiency,making itidealfor• IndustrialTemperature Range: -40°C to+85°C replacingfixed-outputbufferdeviceswhileincreasing
48-leadWQFN (7mm x 7 mm) timingmargininthesystem. FunctionalBlock Diagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2011–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

CLKoutA0* CLKoutA1 VCCOA GND OSCin CLKin_SEL0 CLKin_SEL1 CLKoutB4 CLKoutB2* CLKoutB2 CLKoutB1* GND CLKin1* GND REFout_EN CLKoutA1* VCCOA CLKoutA2 CLKoutA2* CLKoutA3 CLKoutA3* CLKoutA4 CLKoutA4* CLKoutA_TYPE0 VCC OSCout GND CLKin0 CLKin0* CLKoutB_TYPE0 GND CLKoutB4* CLKoutB3* CLKoutB3 VCCOB VCCOB CLKoutB1 CLKoutB0* CLKoutB0 NC CLKoutB_TYPE1 CLKin1 VCC REFout VCCOC CLKoutA_TYPE1 GND 4748 46 45 44 43 42 41 40 39 38 37 1413 15 16 17 18 19 20 21 22 23 24 DAP Top Down View LMK00301 SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com Connection Diagram Figure1. 48-Pin

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www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 PIN DESCRIPTIONS (1) Pin # Pin Name(s) Type Description DAP DAP GND DieAttachPad.ConnecttothePCB groundplaneforheatdissipation. 1,2 CLKoutA0,CLKoutA0* O DifferentialclockoutputA0.Outputtypesetby CLKoutA_TYPE pins. 3,4 CLKoutA1,CLKoutA1* O DifferentialclockoutputA1.Outputtypesetby CLKoutA_TYPE pins. Power supplyforBank A Outputbuffers.VCCOA can operatefrom3.3V or 5,8 VCCOA PWR 2.5V.The VCCOA pinsareinternallytiedtogether.Bypass witha 0.1uF low-ESR capacitorplacedveryclosetoeach Vcco pin.(2) 6,7 CLKoutA2,CLKoutA2* O DifferentialclockoutputA2.Outputtypesetby CLKoutA_TYPE pins. 9,10 CLKoutA3,CLKoutA3* O DifferentialclockoutputA3.Outputtypesetby CLKoutA_TYPE pins. 11,12 CLKoutA4,CLKoutA4* O DifferentialclockoutputA4.Outputtypesetby CLKoutA_TYPE pins. 13,18,24, GND GND Ground37,43,48 14,47 CLKoutA_TYPE0, CLKoutA_TYPE1 I Bank A outputbuffertypeselectionpins(3) Power supplyforCore and InputBufferblocks.The Vcc supplyoperates 15,42 Vcc PWR from3.3V.Bypass witha 0.1uF low-ESR capacitorplacedverycloseto each Vcc pin. Inputforcrystal.Can alsobe drivenby a XO, TCXO, orotherexternal16 OSCin I single-endedclock. Outputforcrystal.Leave OSCout floatingifOSCin isdrivenby a single-17 OSCout O ended clock. 19,22 CLKin_SEL0, CLKin_SEL1 I Clockinputselectionpins(3) 20,21 CLKin0,CLKin0* I Universalclockinput0 (differential/single-ended) 23,39 CLKoutB_TYPE0, CLKoutB_TYPE1 I Bank B outputbuffertypeselectionpins(3) 25,26 CLKoutB4*,CLKoutB4 O DifferentialclockoutputB4.Outputtypesetby CLKoutB_TYPE pins. 27,28 CLKoutB3*,CLKoutB3 O DifferentialclockoutputB3.Outputtypesetby CLKoutB_TYPE pins. Power supplyforBank B Outputbuffers.VCCOB can operatefrom3.3V or 29,32 VCCOB PWR 2.5V.The VCCOB pinsareinternallytiedtogether.Bypass witha 0.1uF low-ESR capacitorplacedveryclosetoeach Vcco pin.(2) 30,31 CLKoutB2*,CLKoutB2 O DifferentialclockoutputB2.Outputtypesetby CLKoutB_TYPE pins. 33,34 CLKoutB1*,CLKoutB1 O DifferentialclockoutputB1.Outputtypesetby CLKoutB_TYPE pins. 35,36 CLKoutB0*,CLKoutB0 O DifferentialclockoutputB0.Outputtypesetby CLKoutB_TYPE pins. Not connectedinternally.Pinmay be floated,grounded,orotherwisetiedto

38 NC — any potentialwithintheSupplyVoltagerangestatedinAbsoluteMaximum

Ratings. 40,41 CLKin1*,CLKin1 I Universalclockinput1 (differential/single-ended) 44 REFout O LVCMOS referenceoutput.Enableoutputby pullingREFout_EN pinhigh. Power supplyforREFout Outputbuffer.VCCOC can operatefrom3.3V or 45 VCCOC PWR 2.5V.Bypass witha 0.1uF low-ESR capacitorplacedveryclosetoeach Vcco pin.(2) REFout enableinput.Enablesignalisinternallysynchronizedtoselected46 REFout_EN I clockinput.(3) (1) Any unused outputpinshouldbe leftfloatingwithminimum copperlength(seenoteinClockOutputs),orproperlyterminatedif connectedtoa transmissionline,ordisabled/Hi-Zifpossible.See ClockOutputsforoutputconfigurationand Terminationand Use of ClockDriversforoutputinterfaceand terminationtechniques. (2) The outputsupplyvoltagesorpins(VCCOA ,VCCOB ,and VCCOC )willbe calledVCCO ingeneralwhen no distinctionisneeded,orwhen the outputsupplycan be inferredfromtheoutputbank/type. (3) CMOS controlinputwithinternalpull-downresistor. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com FunctionalDescription The LMK00301 isa 10-outputdifferentialclockfanoutbufferwithlow additivejitterthatcan operateup to3.1 GHz. Itfeaturesa 3:1inputmultiplexerwithan optionalcrystaloscillatorinput,two banks of5 differentialoutputs withmulti-modebuffers(LVPECL, LVDS, HCSL, orHi-Z),one LVCMOS output,and 3 independentoutputbuffer supplies.The inputselectionand outputbuffermodes arecontrolledviapinstrapping.The deviceisofferedina 48-pinWQFN package and leveragesmuch of the high-speed,low-noisecircuitdesign employed in the LMK04800 familyofclockconditioners. VCC and VCCO Power Supplies The LMK00301 has separate3.3 V core (VCC ) and 3 independent3.3 V/2.5V outputpower supplies(VCCOA , VCCOB , VCCOC ) supplies.Outputsupplyoperationat 2.5 V enableslowerpower consumptionand output-level compatibilitywith2.5 V receiverdevices.The outputlevelsforLVPECL (VOH , VOL ) and LVCMOS (VOH ) are referencedtoitsrespectiveVcco supply,whiletheoutputlevelsforLVDS and HCSL arerelativelyconstantover the specifiedVcco range.Refer to Power Supply and Thermal Considerationsforadditionalsupplyrelated considerations,such as power dissipation,power supplybypassing,and power supplyripplerejection(PSRR). NOTE Care shouldbe taken to ensure the Vcco voltagesdo not exceed the Vcc voltageto preventturning-ontheinternalESD protectioncircuitry. Clock Inputs The inputclockcan be selectedfrom CLKin0/CLKin0*,CLKin1/CLKin1*,or OSCin. Clock inputselectionis controlledusingtheCLKin_SEL[1:0]inputsas shown inTable1.RefertoDrivingtheClockInputsforclockinput requirements.When CLKin0 orCLKin1 isselected,thecrystalcircuitispowered down. When OSCin isselected, thecrystaloscillatorcircuitwillstart-upand itsclockwillbe distributedtoalloutputs.RefertoCrystalInterfacefor more information.Alternatively,OSCin may be drivenby a single-endedclock(up to 250 MHz) insteadof a crystal. Table1.InputSelection CLKin_SEL1 CLKin_SEL0 SelectedInput 0 0 CLKin0,CLKin0* 0 1 CLKin1,CLKin1*

1 X OSCin

Table2 shows theoutputlogicstatevs.inputstatewhen eitherCLKin0/CLKin0*orCLKin1/CLKin1*isselected. When OSCin isselected,theoutputstatewillbe an invertedcopy oftheOSCin inputstate. Table2.CLKin Inputvs.Output States Stateof Stateof SelectedCLKin Enabled Outputs CLKinX and CLKinX* Logiclowinputsfloating CLKinX and CLKinX* Logiclowinputsshortedtogether CLKin logiclow Logiclow CLKin logichigh Logichigh

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www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 Clock Outputs The differentialoutputbuffertype forBank A and Bank B outputscan be separatelyconfiguredusing the CLKoutA_TYPE[1:0]and CLKoutB_TYPE[1:0]inputs,respectively,as shown inTable3.For applicationswhere alldifferentialoutputsare not needed, any unused outputpinshouldbe leftfloatingwitha minimum copper length(see note below)to minimizecapacitanceand potentialcouplingand reduce power consumption.Ifan entireoutputbank willnot be used,itisrecommended to disable(Hi-Z)the bank to reduce power.Referto Terminationand Use ofClockDriversformore informationon outputinterfaceand terminationtechniques. NOTE For bestsolderingpractices,theminimum tracelengthforany unused outputpinshould extendtoincludethepinsoldermask. Thisway duringreflow,thesolderhas thesame copperareaas connectedpins.Thisallowsforgood,uniformfilletsolderjointshelpingto keep theIC levelduringreflow. Table3.DifferentialOutput BufferType Selection CLKoutX_ CLKoutX_ CLKoutX BufferType TYPE1 TYPE0 (Bank A or B) 0 0 LVPECL 0 1 LVDS 1 0 HCSL 1 1 Disabled(Hi-Z) ReferenceOutput The referenceoutput(REFout)providesa LVCMOS copy oftheselectedinputclock.The LVCMOS outputhigh levelis referencedto the Vcco voltage.REFout can be enabled or disabledusing the enable inputpin, REFout_EN, as shown inTable4. Table4.ReferenceOutput Enable REFout_EN REFout State

0 Disabled(Hi-Z)

1 Enabled

The REFout_EN inputis internallysynchronizedwith the selectedinputclockby the SYNC block.This synchronizingfunctionpreventsglitchesand runtpulsesfrom occurringon theREFout clockwhen enabledor disabled.REFout willbe enabledwithin3 cycles(tEN )oftheinputclockafterREFout_EN istoggledhigh.REFout willbe disabledwithin3 cycles(tDIS)oftheinputclockafterREFout_EN istoggledlow. When REFout isdisabled,theuse ofa resistiveloadingcan be used tosettheoutputtoa predeterminedlevel. For example,ifREFout isconfiguredwitha 1 kΩ loadto ground,then the outputwillbe pulledto low when disabled. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2)(3) Parameter Symbol Ratings Units SupplyVoltages VCC ,VCCO -0.3to3.6 V InputVoltage VIN -0.3to(VCC + 0.3) V StorageTemperatureRange TSTG -65to+150 °C Lead Temperature(solder4 s) TL +260 °C JunctionTemperature TJ +150 °C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notensurespecificperformancelimits.Forensuredspecificationsand test conditions,see ElectricalCharacteristics.The ensuredspecificationsapplyonlytothetestconditionslisted. (2) Thisdeviceisa high-performanceintegratedcircuitwithan ESD ratingup to2 kV Human Body Model,up to150 V Machine Model,and up to750 V Charged DeviceModel and isESD sensitive.Handlingand assemblyofthisdeviceshouldonlybe done atESD-free workstations. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Parameter Symbol Min Typ Max Units AmbientTemperatureRange TA -40 25 85 °C JunctionTemperature TJ 125 °C Core SupplyVoltageRange VCC 3.15 3.3 3.45 V (1) The outputsupplyvoltagesorpins(VCCOA ,VCCOB ,and VCCOC )willbe calledVCCO ingeneralwhen no distinctionisneeded,orwhen the outputsupplycan be inferredfromtheoutputbank/type. (2) Vcco forany outputbank shouldbe lessthanorequaltoVcc (Vcco≤ Vcc). Package Thermal Resistance Package θJA θJC (DAP) 48-LeadWQFN (1) 28.5°C/W 7.2°C/W (1) Specificationassumes 16 thermalviasconnectthedieattachpad totheembedded copperplaneon the4-layerJEDEC board.These viasplaya key roleinimprovingthethermalperformanceofthepackage.Itisrecommended thatthemaximum number ofviasbe used intheboardlayout.

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www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 ElectricalCharacteristics Unlessotherwisespecified:Vcc = 3.3V ± 5%, Vcco = 3.3V ± 5%, 2.5V ± 5%, -40°C ≤ TA ≤ 85 °C, CLKin driven differentially,inputslewrate≥ 3 V/ns.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,Vcco = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproductcharacterizationand arenotensured.(1) Symbol Parameter Conditions Min Typ Max Units CurrentConsumption (2) CLKinX selected 8.5 10.5 mACore SupplyCurrent,ICC_CORE AllOutputsDisabled OSCin selected 10 13.5 mA AdditiveCore Supply ICC_PECL Current,Per LVPECL 20 27 mA Bank Enabled AdditiveCore Supply ICC_LVDS Current,Per LVDS 26 32.5 mA Bank Enabled AdditiveCore Supply ICC_HCSL Current,Per HCSL 35 42 mA Bank Enabled AdditiveCore Supply ICC_CMOS Current,LVCMOS 3.5 5.5 mA OutputEnabled AdditiveOutputSupply IncludesOutputBank Biasand Load Currents, ICCO_PECL Current,Per LVPECL R T = 50 Ω toVcco -2V 165 197 mA Bank Enabled on alloutputsinbank AdditiveOutputSupply ICCO_LVDS Current,Per LVDS 34 44.5 mA Bank Enabled AdditiveOutputSupply IncludesOutputBank Biasand Load Currents, ICCO_HCSL Current,Per HCSL R T = 50 Ω 87 104 mA Bank Enabled on alloutputsinbank Vcco = 9 10 mAAdditiveOutputSupply 3.3V ± 5%200 MHz,ICCO_CMOS Current,LVCMOS C L = 5 pF Vcco =OutputEnabled 7 8 mA2.5V ± 5% Power Supply RippleRejection(PSRR) Ripple-Induced 156.25MHz -65 PSRR PECL Phase Spur Level(3) dBc 312.5MHz -63DifferentialLVPECL Output Ripple-Induced 100 kHz,100 mVpp 156.25MHz -76 PSRR HCSL Phase Spur Level(3) RippleInjectedon Vcco, dBc 312.5MHz -74DifferentialHCSL Output Vcco = 2.5V Ripple-Induced 156.25MHz -72 PSRR LVDS Phase Spur Level(3) dBc 312.5MHz -63DifferentialLVDS Output CMOS ControlInputs(CLKin_SELn, CLKoutX_TYPEn, REFout_EN) VIH High-LevelInputVoltage 1.6 Vcc V VIL Low-LevelInputVoltage GND 0.4 V IIH High-LevelInputCurrent VIH = Vcc,Internalpull-downresistor 50 µA IIL Low-LevelInputCurrent VIL= 0 V,Internalpull-downresistor -5 0.1 µA (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) See Power Supplyand ThermalConsiderationsformore informationon currentconsumptionand power dissipationcalculations. (3) Power supplyripplerejection,orPSRR, isdefinedas thesingle-sidebandphase spurlevel(indBc)modulatedontotheclockoutput when a single-tonesinusoidalsignal(ripple)isinjectedontotheVcco supply.Assuming no amplitudemodulationeffectsand smallindex modulation,thepeak-to-peakdeterministicjitter(DJ)can be calculatedusingthemeasured single-sidebandphase spurlevel(PSRR) as follows:DJ (pspk-pk)= [(2*10(PSRR /20))/(π *fCLK )]*1E12 Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMK00301

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www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 ElectricalCharacteristics(continued) Unlessotherwisespecified:Vcc = 3.3V ± 5%, Vcco = 3.3V ± 5%, 2.5V ± 5%, -40°C ≤ TA ≤ 85 °C, CLKin driven differentially,inputslewrate≥ 3 V/ns.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,Vcco = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproductcharacterizationand arenotensured.(1) Symbol Parameter Conditions Min Typ Max Units LVPECL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) Vcco = 3.3V ± 5%, 1.0 1.2VOD ≥ 600 mV, R T = 160 Ω toGNDMaximum OutputFrequencyfCLKout_FS R L = 100 Ω GHzFullVOD Swing (8)(9) Vcco = 2.5V ± 5%,differential 0.75 1.0R T = 91 Ω toGND Vcco = 3.3V ± 5%, 1.5 3.1VOD ≥ 400 mV, R T = 160 Ω toGNDMaximum OutputFrequencyfCLKout_RS R L = 100 Ω GHzReduced VOD Swing (8)(9) Vcco = 2.5V ± 5%,differential 1.5 2.3R T = 91 Ω toGND CLKin:100 MHz, 59Slew rate≥ 3 V/nsVcco = 3.3V,AdditiveRMS Jitter R T = 160 Ω toGND, CLKin:156.25MHz,JitterADD IntegrationBandwidth 64 fsR L = 100 Ω Slew rate≥ 2.7V/ns1 MHz to20 MHz (10) differential CLKin:625 MHz, 30Slew rate≥ 3 V/ns CLKin:156.25MHz, JSOURCE = 190 fsRMS 20Vcco = 3.3V,AdditiveRMS Jitterwith (10kHz to1 MHz)R T = 160 Ω toGND,JitterADD LVPECL clocksourcefrom fsR L = 100 Ω CLKin:156.25MHz,LMK03806 (10)(11) differential JSOURCE = 195 fsRMS 51 (12kHz to20 MHz) CLKin:100 MHz, -162.5Slew rate≥ 3 V/nsVcco = 3.3V, NoiseFloor R T = 160 Ω toGND, CLKin:156.25MHz,NoiseFloor -158.1 dBc/HzfOFFSET ≥ 10 MHz (12)(13) R L = 100 Ω Slew rate≥ 2.7V/ns differential CLKin:625 MHz, -154.4Slew rate≥ 3 V/ns DUTY DutyCycle(8) 50% inputclockdutycycle 45 55 % Vcco - Vcco - Vcco -VOH OutputHighVoltage V1.2 0.9 0.7 TA = 25 °C, DC Measurement, Vcco - Vcco - Vcco -VOL OutputLow Voltage R T = 50 Ω toVcco -2 V V2.0 1.75 1.5 VOD OutputVoltageSwing (14) 600 830 1000 mV OutputRiseTimetR 175 300 psR T = 160 Ω toGND, Uniformtransmissionlineup to20% to80% (15) 10 in.with50-Ω characteristicimpedance, OutputFallTime R L = 100 Ω differential,C L ≤ 5 pFtF 175 300 ps80% to20% (15) (8) Specificationisensuredby characterizationand isnottestedinproduction. (9) See TypicalPerformanceCharacteristicsforoutputoperationoverfrequency. (10)Forthe100 MHz and 156.25MHz clockinputconditions,AdditiveRMS Jitter(JADD )iscalculatedusingMethod #1:JADD = SQRT(J OUT -JSOURCE 2),where JOUT isthetotalRMS jittermeasured attheoutputdriverand JSOURCE istheRMS jitteroftheclocksourceappliedto CLKin.Forthe625 MHz clockinputcondition,AdditiveRMS JitterisapproximatedusingMethod #2:JADD = SQRT(2*10 dBc/10)/ (2*π*fCLK ),where dBc isthephase noisepower oftheOutputNoiseFloorintegratedfrom1 to20 MHz bandwidth.The phase noise power can be calculatedas:dBc = NoiseFloor+ 10*log10(20MHz -1 MHz). The additiveRMS jitterwas approximatedfor625 MHz usingMethod #2 because theRMS jitteroftheclocksourcewas notsufficientlylowenough toallowpracticaluse ofMethod #1.Refer tothe“NoiseFloorvs.CLKin Slew Rate”and “RMS Jittervs.CLKin Slew Rate”plotsinTypicalPerformanceCharacteristics. (11)156.25MHz LVPECL clocksourcefromLMK03806 with20 MHz crystalreference(crystalpartnumber:ECS-200-20-30BU-DU).Typical JSOURCE = 190 fsRMS (10kHz to1 MHz) and 195 fsRMS (12kHz to20 MHz). RefertotheLMK03806 datasheetformore information. (12)The noiseflooroftheoutputbufferismeasured as thefar-outphase noiseofthebuffer.Typicallythisoffsetis≥ 10 MHz, butforlower frequenciesthismeasurement offsetcan be as lowas 5 MHz due tomeasurement equipmentlimitations. (13)Phase noisefloorwilldegradeas theclockinputslewrateisreduced.Compared toa single-endedclock,a differentialclockinput (LVPECL, LVDS) willbe lesssusceptibletodegradationinnoiseflooratlowerslewratesdue toitscommon mode noiserejection. However,itisrecommended touse thehighestpossibleinputslewratefordifferentialclockstoachieveoptimalnoisefloorperformance atthedeviceoutputs. (14)See DifferentialVoltageMeasurement TerminologyfordefinitionofVID and VOD voltages. (15)Parameterisspecifiedby design,nottestedinproduction. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com ElectricalCharacteristics(continued) Unlessotherwisespecified:Vcc = 3.3V ± 5%, Vcco = 3.3V ± 5%, 2.5V ± 5%, -40°C ≤ TA ≤ 85 °C, CLKin driven differentially,inputslewrate≥ 3 V/ns.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,Vcco = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproductcharacterizationand arenotensured.(1) Symbol Parameter Conditions Min Typ Max Units LVDS Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) Maximum OutputFrequency VOD ≥ 250 mV,fCLKout_FS 1.0 1.6 GHzFullVOD Swing (16)(17) R L = 100 Ω differential Maximum OutputFrequency VOD ≥ 200 mV,fCLKout_RS 1.5 2.1 GHzReduced VOD Swing (16)(17) R L = 100 Ω differential CLKin:100 MHz, 89Slew rate≥ 3 V/ns AdditiveRMS Jitter Vcco = 3.3V, CLKin:156.25MHz,JitterADD IntegrationBandwidth R L = 100 Ω 77 fsSlew rate≥ 2.7V/ns1 MHz to20 MHz (18) differential CLKin:625 MHz, 37Slew rate≥ 3 V/ns CLKin:100 MHz, -159.5Slew rate≥ 3 V/ns Vcco = 3.3V,NoiseFloor CLKin:156.25MHz,NoiseFloor R L = 100 Ω -157.0 dBc/HzfOFFSET ≥ 10 MHz (19)(20) Slew rate≥ 2.7V/nsdifferential CLKin:625 MHz, -152.7Slew rate≥ 3 V/ns DUTY DutyCycle(16) 50% inputclockdutycycle 45 55 % VOD OutputVoltageSwing (21) 250 400 450 mV Change inMagnitudeofVOD ΔVOD forComplementary -50 50 mV TA = 25 °C,OutputStates DC Measurement, VOS OutputOffsetVoltage 1.125 1.25 1.375 VR L = 100 Ω differential Change inMagnitudeofVOS ΔVOS forComplementary -35 35 mV OutputStates ISA OutputShortCircuitCurrent TA = 25 °C, -24 24 mAISB SingleEnded Singleended outputsshortedtoGND OutputShortCircuitCurrentISAB Complementaryoutputstiedtogether -12 12 mADifferential OutputRiseTime Uniformtransmissionlineup to10 in.tR 175 300 ps20% to80% (22) with50-Ω characteristicimpedance, R L = 100 Ω differential,OutputFallTimetF 175 300 psC L ≤ 5 pF80% to20% (22) (16)Specificationisensuredby characterizationand isnottestedinproduction. (17)See TypicalPerformanceCharacteristicsforoutputoperationoverfrequency. (18)Forthe100 MHz and 156.25MHz clockinputconditions,AdditiveRMS Jitter(JADD )iscalculatedusingMethod #1:JADD = SQRT(J OUT -JSOURCE 2),where JOUT isthetotalRMS jittermeasured attheoutputdriverand JSOURCE istheRMS jitteroftheclocksourceappliedto CLKin.Forthe625 MHz clockinputcondition,AdditiveRMS JitterisapproximatedusingMethod #2:JADD = SQRT(2*10 dBc/10)/ (2*π*fCLK ),where dBc isthephase noisepower oftheOutputNoiseFloorintegratedfrom1 to20 MHz bandwidth.The phase noise power can be calculatedas:dBc = NoiseFloor+ 10*log10(20MHz -1 MHz). The additiveRMS jitterwas approximatedfor625 MHz usingMethod #2 because theRMS jitteroftheclocksourcewas notsufficientlylowenough toallowpracticaluse ofMethod #1.Refer tothe“NoiseFloorvs.CLKin Slew Rate”and “RMS Jittervs.CLKin Slew Rate”plotsinTypicalPerformanceCharacteristics. (19)The noiseflooroftheoutputbufferismeasured as thefar-outphase noiseofthebuffer.Typicallythisoffsetis≥ 10 MHz, butforlower frequenciesthismeasurement offsetcan be as lowas 5 MHz due tomeasurement equipmentlimitations. (20)Phase noisefloorwilldegradeas theclockinputslewrateisreduced.Compared toa single-endedclock,a differentialclockinput (LVPECL, LVDS) willbe lesssusceptibletodegradationinnoiseflooratlowerslewratesdue toitscommon mode noiserejection. However,itisrecommended touse thehighestpossibleinputslewratefordifferentialclockstoachieveoptimalnoisefloorperformance atthedeviceoutputs. (21)See DifferentialVoltageMeasurement TerminologyfordefinitionofVID and VOD voltages. (22)Parameterisspecifiedby design,nottestedinproduction.

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www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 ElectricalCharacteristics(continued) Unlessotherwisespecified:Vcc = 3.3V ± 5%, Vcco = 3.3V ± 5%, 2.5V ± 5%, -40°C ≤ TA ≤ 85 °C, CLKin driven differentially,inputslewrate≥ 3 V/ns.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,Vcco = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproductcharacterizationand arenotensured.(1) Symbol Parameter Conditions Min Typ Max Units HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) fCLKout OutputFrequencyRange (23) R L = 50 Ω toGND, C L ≤ 5 pF DC 400 MHz PCIe Gen 3,AdditiveRMS Phase Jitter CLKin:100 MHz,JitterADD_PCIe PLL BW = 2–5 MHz, 0.03 0.15 psforPCIe 3.0(23) Slew rate≥ 0.6V/nsCDR = 10 MHz CLKin:100 MHz, 77AdditiveRMS Jitter Slew rate≥ 3 V/nsVcco = 3.3V,JitterADD IntegrationBandwidth fsR T = 50 Ω toGND CLKin:156.25MHz,1 MHz to20 MHz (24) 86Slew rate≥ 2.7V/ns DUTY DutyCycle(23) 50% inputclockdutycycle 45 55 % VOH OutputHighVoltage 520 810 920 mVTA = 25 °C, DC Measurement, R T = 50 Ω toGNDVOL OutputLow Voltage -150 0.5 150 mV AbsoluteCrossingVoltageVCROSS 160 350 460 mV(23)(27) R L = 50 Ω toGND, C L ≤ 5 pFTotalVariationofVCROSSΔVCROSS 140 mV(23)(27) OutputRiseTime 250 MHz,tR 300 500 ps20% to80% (27)(28) Uniformtransmissionlineup to10 in. with50-Ω characteristicimpedance, OutputFallTime R L = 50 Ω toGND,tF 300 500 ps80% to20% (27)(28) C L ≤ 5 pF (23)Specificationisensuredby characterizationand isnottestedinproduction. (24)Forthe100 MHz and 156.25MHz clockinputconditions,AdditiveRMS Jitter(JADD )iscalculatedusingMethod #1:JADD = SQRT(J OUT -JSOURCE 2),where JOUT isthetotalRMS jittermeasured attheoutputdriverand JSOURCE istheRMS jitteroftheclocksourceappliedto CLKin.Forthe625 MHz clockinputcondition,AdditiveRMS JitterisapproximatedusingMethod #2:JADD = SQRT(2*10 dBc/10)/ (2*π*fCLK ),where dBc isthephase noisepower oftheOutputNoiseFloorintegratedfrom1 to20 MHz bandwidth.The phase noise power can be calculatedas:dBc = NoiseFloor+ 10*log10(20MHz -1 MHz). The additiveRMS jitterwas approximatedfor625 MHz usingMethod #2 because theRMS jitteroftheclocksourcewas notsufficientlylowenough toallowpracticaluse ofMethod #1.Refer tothe“NoiseFloorvs.CLKin Slew Rate”and “RMS Jittervs.CLKin Slew Rate”plotsinTypicalPerformanceCharacteristics. (25)The noiseflooroftheoutputbufferismeasured as thefar-outphase noiseofthebuffer.Typicallythisoffsetis≥ 10 MHz, butforlower frequenciesthismeasurement offsetcan be as lowas 5 MHz due tomeasurement equipmentlimitations. (26)Phase noisefloorwilldegradeas theclockinputslewrateisreduced.Compared toa single-endedclock,a differentialclockinput (LVPECL, LVDS) willbe lesssusceptibletodegradationinnoiseflooratlowerslewratesdue toitscommon mode noiserejection. However,itisrecommended touse thehighestpossibleinputslewratefordifferentialclockstoachieveoptimalnoisefloorperformance atthedeviceoutputs. (27)AC timingparametersforHCSL orCMOS aredependenton outputcapacitiveloading. (28)Parameterisspecifiedby design,nottestedinproduction. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com ElectricalCharacteristics(continued) Unlessotherwisespecified:Vcc = 3.3V ± 5%, Vcco = 3.3V ± 5%, 2.5V ± 5%, -40°C ≤ TA ≤ 85 °C, CLKin driven differentially,inputslewrate≥ 3 V/ns.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,Vcco = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproductcharacterizationand arenotensured.(1) Symbol Parameter Conditions Min Typ Max Units LVCMOS Output (REFout) fCLKout OutputFrequencyRange (29) C L ≤ 5 pF DC 250 MHz AdditiveRMS Jitter Vcco = 3.3V, 100 MHz, InputSlewJitterADD IntegrationBandwidth 95 fsC L ≤ 5 pF rate≥ 3 V/ns1 MHz to20 MHz (30) NoiseFloor Vcco = 3.3V, 100 MHz, InputSlewNoiseFloor -159.3 dBc/HzfOFFSET ≥ 10 MHz (31)(32) C L ≤ 5 pF rate≥ 3 V/ns DUTY DutyCycle(29) 50% inputclockdutycycle 45 55 % Vcco -VOH OutputHighVoltage V0.11 mA load VOL OutputLow Voltage 0.1 V Vcco = 3.3V 28OutputHighCurrentIOH mA(Source) Vcco = 2.5V 20 Vo = Vcco /2 Vcco = 3.3V 28 IOL OutputLow Current(Sink) mA Vcco = 2.5V 20 OutputRiseTime 250 MHz,tR 225 400 ps20% to80% (33)(34) Uniformtransmissionlineup to10 in. with50-Ω characteristicimpedance, OutputFallTime R L = 50 Ω toGND,tF 225 400 ps80% to20% (33)(34) C L ≤ 5 pF tEN OutputEnableTime (35) 3 cycles C L ≤ 5 pF tDIS OutputDisableTime (35) 3 cycles (29)Specificationisensuredby characterizationand isnottestedinproduction. (30)Forthe100 MHz and 156.25MHz clockinputconditions,AdditiveRMS Jitter(JADD )iscalculatedusingMethod #1:JADD = SQRT(J OUT -JSOURCE 2),where JOUT isthetotalRMS jittermeasured attheoutputdriverand JSOURCE istheRMS jitteroftheclocksourceappliedto CLKin.Forthe625 MHz clockinputcondition,AdditiveRMS JitterisapproximatedusingMethod #2:JADD = SQRT(2*10 dBc/10)/ (2*π*fCLK ),where dBc isthephase noisepower oftheOutputNoiseFloorintegratedfrom1 to20 MHz bandwidth.The phase noise power can be calculatedas:dBc = NoiseFloor+ 10*log10(20MHz -1 MHz). The additiveRMS jitterwas approximatedfor625 MHz usingMethod #2 because theRMS jitteroftheclocksourcewas notsufficientlylowenough toallowpracticaluse ofMethod #1.Refer tothe“NoiseFloorvs.CLKin Slew Rate”and “RMS Jittervs.CLKin Slew Rate”plotsinTypicalPerformanceCharacteristics. (31)The noiseflooroftheoutputbufferismeasured as thefar-outphase noiseofthebuffer.Typicallythisoffsetis≥ 10 MHz, butforlower frequenciesthismeasurement offsetcan be as lowas 5 MHz due tomeasurement equipmentlimitations. (32)Phase noisefloorwilldegradeas theclockinputslewrateisreduced.Compared toa single-endedclock,a differentialclockinput (LVPECL, LVDS) willbe lesssusceptibletodegradationinnoiseflooratlowerslewratesdue toitscommon mode noiserejection. However,itisrecommended touse thehighestpossibleinputslewratefordifferentialclockstoachieveoptimalnoisefloorperformance atthedeviceoutputs. (33)AC timingparametersforHCSL orCMOS aredependenton outputcapacitiveloading. (34)Parameterisspecifiedby design,nottestedinproduction. (35)OutputEnableTime isthenumber ofinputclockcyclesittakesfortheoutputtobe enabledafterREFout_EN ispulledhigh.Similarly, OutputDisableTime isthenumber ofinputclockcyclesittakesfortheoutputtobe disabledafterREFout_EN ispulledlow.The REFout_EN signalshouldhave an edge transitionmuch fasterthanthatoftheinputclockperiodforaccuratemeasurement.

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VOD = | VOH - VOL | VSS = 2·VOD VOD Definition V SS Definition for Output Non-Inverting Clock Inverting Clock VOD VSSVOS VIH VIL GND VID = | VIH ± VIL | VSS = 2·VID VID Definition V SS Definition for Input Non-Inverting Clock Inverting Clock VID VSSVCM LMK00301 SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com Measurement Definitions DifferentialVoltageMeasurement Terminology The differentialvoltageof a differentialsignalcan be describedby two differentdefinitionscausingconfusion when readingdatasheetsorcommunicatingwithotherengineers.Thissectionwilladdressthemeasurement and descriptionof a differentialsignalso thatthe readerwillbe ableto understandand discernbetween the two differentdefinitionswhen used. The firstdefinitionused todescribea differentialsignalistheabsolutevalueofthevoltagepotentialbetween the invertingand non-invertingsignal.The symbol forthisfirstmeasurement istypicallyVID or VOD dependingon if an inputoroutputvoltageisbeingdescribed. The second definitionused todescribea differentialsignalistomeasure thepotentialofthenon-invertingsignal withrespectto the invertingsignal.The symbol forthissecond measurement is VSS and is a calculated parameter.Nowhere inthe IC does thissignalexistwithrespectto ground,itonlyexistsinreferenceto its differentialpair.VSS can be measured directlyby oscilloscopeswithfloatingreferences,otherwisethisvaluecan be calculatedas twicethevalueofVOD as describedinthefirstdescription. Figure2 illustratesthetwo differentdefinitionsside-by-sideforinputsand Figure3 illustratesthetwo different definitionsside-by-sideforoutputs.The VID (orVOD )definitionshow theDC levels,VIH and VOL (orVOH and VOL ), thatthe non-invertingand invertingsignalstogglebetween with respectto ground.VSS inputand output definitionsshow thatiftheinvertingsignalisconsideredthevoltagepotentialreference,thenon-invertingsignal voltagepotentialisnow increasingand decreasingabove and below thenon-invertingreference.Thus thepeak- to-peakvoltageofthedifferentialsignalcan be measured. VID and VOD areoftendefinedas volts(V)and VSS isoftendefinedas voltspeak-to-peak(VPP ). Figure2. Two DifferentDefinitionsforDifferentialInputSignals Figure3. Two DifferentDefinitionsforDifferentialOutput Signals Referto ApplicationNote AN-912 (literaturenumber SNLA036 ),Common Data TransmissionParametersand theirDefinitions,formore information.

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-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 OUTPUT SWING (V) TIME (ns) -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4OUTPUT SWING (V) TIME (ns) -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 OUTPUT SWING (V) TIME (ns) -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 OUTPUT SWING (V) TIME (ns) 100 1000 10000 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT SWING (V) FREQUENCY (MHz) Vcco=2.5 V, Rterm=91 Vcco=3.3 V, Rterm=160 100 1000 10000 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45OUTPUT SWING (V) FREQUENCY (MHz) LMK00301 www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 TypicalPerformance Characteristics Unlessotherwisespecified:Vcc = 3.3V,Vcco = 3.3V,TA = 25 °C, CLKin drivendifferentially,inputslewrate≥ 3 V/ns. LVPECL Output Swing (VOD ) LVDS Output Swing (VOD ) vs. vs. Frequency Frequency Figure4. Figure5. LVPECL Output Swing @ 156.25MHz LVDS Output Swing @ 156.25MHz Figure6. Figure7. LVPECL Output Swing @ 1.5GHz LVDS Output Swing @ 1.5GHz Figure8. Figure9. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMK00301

-165 -160 -155 -150 -145 -140 -135NOISE FLOOR (dBc/Hz) DIFFERENTIAL INPUT SLEW RATE (V/ns) Fclk=625 MHz Foffset=20 MHz LVPECL LVDS CLKin Source 100 150 200 250 300 350 400 RMS JITTER (fs) DIFFERENTIAL INPUT SLEW RATE (V/ns) Fclk=100 MHz Int. BW=1-20 MHz LVPECL LVDS HCSL LVCMOS CLKin Source -170 -165 -160 -155 -150 -145 -140NOISE FLOOR (dBc/Hz) DIFFERENTIAL INPUT SLEW RATE (V/ns) Fclk=100 MHz Foffset=20 MHz LVPECL LVDS HCSL LVCMOS CLKin Source -165 -160 -155 -150 -145 -140 -135NOISE FLOOR (dBc/Hz) DIFFERENTIAL INPUT SLEW RATE (V/ns) Fclk=156.25 MHz Foffset=20 MHz LVPECL LVDS HCSL CLKin Source 0 1 2 3 4 5 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 OUTPUT SWING (V) TIME (ns) 0 1 2 3 4 5 6 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00OUTPUT SWING (V) TIME (ns) Vcco=3.3 V, AC coupled, 50 load Vcco=2.5 V, AC coupled, 50 load LMK00301 SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com TypicalPerformance Characteristics(continued) Unlessotherwisespecified:Vcc = 3.3V,Vcco = 3.3V,TA = 25 °C, CLKin drivendifferentially,inputslewrate≥ 3 V/ns. HCSL Output Swing @ 250 MHz LVCMOS Output Swing @ 250 MHz Figure10. Figure11. Noise Floorvs.CLKin Slew Rate @ 100 MHz Noise Floorvs.CLKin Slew Rate @ 156.25MHz Figure12. Figure13. Noise Floorvs.CLKin Slew Rate @ 625 MHz RMS Jittervs.CLKin Slew Rate @ 100 MHz Figure14. Figure15.

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-50 -25 0 25 50 75 100 250 350 450 550 650 750 850 1350 1450 1550 1650 1750 1850 1950 CLKout PROPAGATION DELAY (ps) TEMPERATURE (° C) REFout PROPAGATION DELAY (ps) Right Y-axis plot LVPECL (0.35 ps/° C) LVDS (0.35 ps/° C) HCSL (0.35 ps/° C) LVCMOS (2.2 ps/° C) .1 1 10 -90 -85 -80 -75 -70 -65 -60 -55 -50 RIPPLE INDUCED SPUR LEVEL (dBc) RIPPLE FREQUENCY (MHz) Fclk=156.25 MHz Vcco Ripple=100 mVpp LVPECL LVDS HCSL .1 1 10 -90 -85 -80 -75 -70 -65 -60 -55 -50 RIPPLE INDUCED SPUR LEVEL (dBc) RIPPLE FREQUENCY (MHz) Fclk=312.5 MHz Vcco Ripple=100 mVpp LVPECL LVDS HCSL 100 150 200 250 300 350 400 450 500 RMS JITTER (fs) DIFFERENTIAL INPUT SLEW RATE (V/ns) Fclk=156.25 MHz Int. BW=1-20 MHz LVPECL LVDS HCSL CLKin Source 100 125 150 175 200 RMS JITTER (fs) DIFFERENTIAL INPUT SLEW RATE (V/ns) Fclk=625 MHz Int. BW=1-20 MHz LVPECL LVDS CLKin Source LMK00301 www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 TypicalPerformance Characteristics(continued) Unlessotherwisespecified:Vcc = 3.3V,Vcco = 3.3V,TA = 25 °C, CLKin drivendifferentially,inputslewrate≥ 3 V/ns. RMS Jittervs.CLKin Slew Rate @ 156.25MHz RMS Jittervs.CLKin Slew Rate @ 625 MHz Figure16. Figure17. PSRR vs.RippleFrequency @ 156.25MHz PSRR vs.RippleFrequency @ 312.5MHz Figure18. Figure19. PropagationDelay vs.Temperature LVPECL Phase Noise @ 100 MHz Figure20. Figure21. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LMK00301

0 500 1k 1.5k 2k 2.5k 3k 3.5k 4k 100 125 150 175 200 CRYSTAL POWER DISSIPATION ( R LIM(

20 MHz Crystal

40 MHz Crystal

-180 -160 -140 -120 -100 -80 -60 PHASE NOISE (dBc/Hz) OFFSET FREQUENCY (Hz) 20 MHz Crystal, Rlim = 1.5 k 40 MHz Crystal, Rlim = 1.0 k LMK00301 SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com TypicalPerformance Characteristics(continued) Unlessotherwisespecified:Vcc = 3.3V,Vcco = 3.3V,TA = 25 °C, CLKin drivendifferentially,inputslewrate≥ 3 V/ns. LVDS Phase Noise @ 100 MHz HCSL Phase Noise @ 100 MHz Figure22. Figure23. CrystalPower Dissipation vs. R LIM LVDS Phase Noise inCrystalMode Figure24. Figure25. (1) The typicalRMS jittervaluesintheplotsshow thetotaloutputRMS jitter(JOUT ) foreach outputbuffertypeand the source clockRMS jitter(JSOURCE ).From these values,the AdditiveRMS Jittercan be calculatedas: JADD = SQRT(J OUT 2 – JSOURCE 2). (2) 20 MHz crystalcharacteristics:Abracon ABL series,AT cut,C L = 18 pF ,C 0 = 4.4pF measured (7pF max),ESR = 8.5Ω measured (40Ω max),and DriveLevel= 1 mW max (100µW typical). (3) 40 MHz crystalcharacteristics:Abracon ABLS2 series,AT cut,C L = 18 pF ,C 0 = 5 pF measured (7pF max),ESR = 5 Ω measured (40Ω max),and DriveLevel= 1 mW max (100µW typical).

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0.1 PF 50:Trace CMOS Driver Rs VCC R B1 R B2 VCC LMK Input 50: VO,PP VO,PP /2 VBB ~ (VO,PP /2) x 0.5 0.1 PF 0.1 PF 50:Trace 50: LMK Input

0.1 PFR SCMOS

www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

APPLICATION INFORMATION

The LMK00301 has two universalinputs(CLKin0/CLKin0*and CLKin1/CLKin1*)thatcan acceptAC- or DC- coupled3.3V/2.5VLVPECL, LVDS, CML, SSTL, and otherdifferentialand single-endedsignalsthatmeet the inputrequirementsspecifiedinElectricalCharacteristics.The devicecan accepta wide range ofsignalsdue to itswide inputcommon mode voltagerange(VCM )and inputvoltageswing(VID)/dynamic range.For 50% duty cycleand DC-balanced signals,AC couplingmay alsobe employed to shiftthe inputsignalto withinthe VCM range.RefertoTerminationand Use ofClockDriversforsignalinterfacingand terminationtechniques. To achievethebestpossiblephase noiseand jitterperformance,itismandatoryfortheinputtohave highslew rateof3 V/ns(differential)orhigher.Drivingtheinputwitha lowerslewratewilldegradethenoisefloorand jitter. For thisreason,a differentialsignalinputisrecommended oversingle-endedbecause ittypicallyprovideshigher slewrateand common-mode-rejection.Refertothe“NoiseFloorvs.CLKin Slew Rate”and “RMS Jittervs.CLKin Slew Rate”plotsinTypicalPerformanceCharacteristics. Whileitisrecommended todrivetheCLKin/CLKin*pairwitha differentialsignalinput,itispossibletodriveit witha single-endedclockprovideditconformstotheSingle-EndedInputspecificationsforCLKin pinslistedin theElectricalCharacteristics.For largesingle-endedinputsignals,such as 3.3V or2.5V LVCMOS, a 50 Ω load resistorshouldbe placednear the inputforsignalattenuationto preventinputoverdriveas wellas forline terminationto minimizereflections.Again,the single-endedinputslew rateshouldbe as highas possibleto minimizeperformancedegradation.The CLKin inputhas an internalbiasvoltageofabout1.4V, so theinputcan be AC coupledas shown inFigure26.The outputimpedance oftheLVCMOS driverplusRs shouldbe closeto 50 Ω tomatch thecharacteristicimpedance ofthetransmissionlineand loadtermination. Figure26. Single-EndedLVCMOS Input,AC Coupling A single-endedclockmay alsobe DC coupledtoCLKinX as shown inFigure27.A 50-Ω loadresistorshouldbe placedneartheCLKinX inputforsignalattenuationand linetermination.Because halfofthesingle-endedswing of the driver(VO,PP / 2) drivesCLKinX, CLKinX* shouldbe externallybiasedto the midpointvoltageof the attenuatedinputswing((VO,PP /2)× 0.5).The externalbiasvoltageshouldbe withinthespecifiedinputcommon voltage(VCM ) range.Thiscan be achievedusingexternalbiasingresistorsinthe kΩ range (RB1 and R B2) or anotherlow-noisevoltagereference.Thiswillensure the inputswing crossesthe thresholdvoltageat a point where theinputslewrateisthehighest. Figure27. Single-EndedLVCMOS Input,DC Coupling withCommon Mode Biasing Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LMK00301

0.1 PF50:Trace

50: CMOS Driver

0.1 PFR S

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com Ifthecrystaloscillatorcircuitisnotused,itispossibletodrivetheOSCin inputwithan single-endedexternal clockas shown inFigure28.The inputclockshouldbe AC coupledtotheOSCin pin,which has an internally- generatedinputbiasvoltage,and theOSCout pinshouldbe leftfloating.WhileOSCin providesan alternative inputto multiplexan externalclock,itisrecommended to use eitheruniversalinput(CLKinX)sinceitoffers higheroperatingfrequency,bettercommon mode and power supplynoiserejection,and greaterperformance oversupplyvoltageand temperaturevariations. Figure28. DrivingOSCin witha Single-EndedInput CrystalInterface The LMK00301 has an integratedcrystaloscillatorcircuitthatsupportsa fundamentalmode, AT-cutcrystal.The crystalinterfaceisshown inFigure29. Figure29. CrystalInterface The loadcapacitance(CL)isspecifictothecrystal,butusuallyon theorderof18 -20 pF.WhileC L isspecified forthecrystal,theOSCin inputcapacitance(CIN = 1 pF typical)ofthedeviceand PCB straycapacitance(CSTRAY ~ 1~3 pF)can affectthediscreteloadcapacitorvalues,C 1 and C 2. Fortheparallelresonantcircuit,thediscretecapacitorvaluescan be calculatedas follows: C L = (C1 *C 2)/(C1 + C 2)+ C IN + C STRAY (1) Typically,C 1 = C 2 foroptimum symmetry,so Equation1 can be rewrittenintermsofC 1 only: C L = C 1 2 /(2*C 1)+ C IN + C STRAY (2) Finally,solveforC 1: C 1 = (CL – C IN – C STRAY )*2 (3) ElectricalCharacteristicsprovidescrystalinterfacespecificationswithconditionsthatensure start-upof the crystal,but itdoes not specifycrystalpower dissipation.The designerwillneed to ensure the crystalpower dissipationdoes not exceed the maximum drivelevelspecifiedby the crystalmanufacturer.Overdrivingthe crystalcan cause prematureaging,frequencyshift,and eventualfailure.Drivelevelshouldbe heldata sufficient levelnecessarytostart-upand maintainsteady-stateoperation. The power dissipatedinthecrystal,PXTAL ,can be computed by: PXTAL = IRMS 2 *R ESR *(1+ C 0/CL)2 where

IRMS istheRMS currentthroughthecrystal.
R ESR isthemax. equivalentseriesresistancespecifiedforthecrystal
C L istheloadcapacitancespecifiedforthecrystal
C 0 isthemin.shuntcapacitancespecifiedforthecrystal (4)

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CLKoutX* HCSL Receiver 50: 50:Traces 50: HCSL Driver Rs Rs CLKoutX CLKoutX* LVDS Receiver 100:100:Trace (Differential) LVDS Driver LMK00301 www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 IRMS can be measured usinga currentprobe(e.g.TektronixCT-6 orequivalent)placedon thelegofthecrystal connectedtoOSCout withtheoscillationcircuitactive. As shown inFigure29,an externalresistor,R LIM,can be used tolimitthecrystaldrivelevel,ifnecessary.Ifthe power dissipatedintheselectedcrystalishigherthanthedrivelevelspecifiedforthecrystalwithR LIM shorted, thena largerresistorvalueismandatorytoavoidoverdrivingthecrystal.However,ifthepower dissipatedinthe crystalislessthanthedrivelevelwithR LIM shorted,thena zerovalueforR LIM can be used.As a startingpoint,a suggestedvalueforR LIM is1.5kΩ. Terminationand Use ofClock Drivers When terminatingclockdriverskeep inmind theseguidelinesforoptimum phase noiseand jitterperformance:

Transmissionlinetheoryshouldbe followedforgood impedance matchingtopreventreflections.
Clockdriversshouldbe presentedwiththeproperloads. – LVDS outputsarecurrentdriversand requirea closedcurrentloop. – HCSL driversareswitchedcurrentoutputsand requirea DC pathtogroundvia50 Ω termination. – LVPECL outputsareopen emitterand requirea DC pathtoground.
Receiversshouldbe presentedwitha signalbiasedtotheirspecifiedDC biaslevel(common mode voltage) forproperoperation.Some receivershave self-biasinginputsthatautomaticallybiasto the propervoltage level;inthiscase,thesignalshouldnormallybe AC coupled. Itispossibletodrivea non-LVPECL ornon-LVDS receiverwitha LVDS orLVPECL driveras longas theabove guidelinesare followed.Check the datasheetof the receiveror inputbeing drivento determinethe best terminationand couplingmethod tobe surethereceiverisbiasedattheoptimum DC voltage(common mode voltage). TerminationforDC Coupled DifferentialOperation For DC coupledoperationofan LVDS driver,terminatewith100 Ω as closeas possibletotheLVDS receiveras shown inFigure30. Figure30. DifferentialLVDS Operation,DC Coupling, No Biasingby theReceiver For DC coupledoperationofan HCSL driver,terminatewith50 Ω togroundnearthedriveroutputas shown in Figure31.Seriesresistors,Rs, may be used tolimitovershootdue tothefasttransientcurrent.Because HCSL driversrequirea DC path to ground,AC couplingisnot allowedbetween the outputdriversand the 50 Ω terminationresistors. Figure31. HCSL Operation,DC Coupling Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LMK00301

CLKoutX* LVPECL Receiver R PU 100:Trace (Differential) R PU Vcco Vcco LVPECL Driver R PDR PDR PU R PDVcco VTT 3.3V 2.5V 120: 250: 82: 62.5: ~1.3V 0.5V CLKoutX CLKoutX* LVPECL Receiver 50: 100:Trace (Differential) 50: Vcco - 2V Vcco - 2V LVPECL Driver LMK00301 SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com For DC coupledoperationof an LVPECL driver,terminatewith50 Ω to Vcco - 2 V as shown inFigure32. Alternativelyterminatewitha Theveninequivalentcircuitas shown inFigure33 forVcco (outputdriversupply voltage)= 3.3 V and 2.5 V. In the Theveninequivalentcircuit,the resistordividerssetthe outputtermination voltage(VTT)toVcco -2 V. Figure32. DifferentialLVPECL Operation,DC Coupling Figure33. DifferentialLVPECL Operation,DC Coupling,Thevenin Equivalent TerminationforAC Coupled DifferentialOperation AC couplingallowsforshiftingthe DC bias level(common mode voltage)when drivingdifferentreceiver standards.SinceAC couplingpreventsthedriverfromprovidinga DC biasvoltageatthereceiver,itisimportant toensurethereceiverisbiasedtoitsidealDC level. When drivingdifferentialreceiverswithan LVDS driver,thesignalmay be AC coupledby addingDC blocking capacitors;however theproperDC biaspointneeds tobe establishedatboththedriversideand thereceiver side.The recommended terminationscheme depends on whether the differentialreceiverhas integrated terminationresistorsornot. When drivinga differentialreceiverwithoutinternal100 Ω differentialtermination,the AC couplingcapacitors shouldbe placedbetween theloadterminationresistorand thereceivertoallowa DC pathforproperbiasingof theLVDS driver.Thisisshown inFigure34(a.)The loadterminationresistorand AC couplingcapacitorsshould be placedas closeas possibleto the receiverinputsto minimizestub length.The receivercan be biased internallyorexternallytoa referencevoltagewithinthereceiver’s common mode inputrangethroughresistorsin thekilo-ohmrange.

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CLKoutX* 0.1 PF 0.1 PF 100:Trace (Differential)100: Receiver with internal termination and biasing through 50: resistors 50: 50: Vbias (b) LVDS DC termination with AC coupling at source and internal termination at load. Double termination at source and load will reduce swing by half. Source termination for proper DC bias of the driver LVDS Driver CLKoutX CLKoutX* 0.1 PF 0.1 PF 100:Trace (Differential) 100: Receiver biasing can be internal or external through resistors in K: range (a) LVDS DC termination with AC coupling at load Vbias LMK00301 www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 When drivinga differentialreceiverwithinternal100 Ω differentialtermination,a source terminationresistor shouldbe placedbeforetheAC couplingcapacitorsforproperDC biasingofthedriveras shown inFigure34(b.) However, witha 100 Ω resistorat the sourceand the load(i.e.doubleterminated),the equivalentresistance seen by theLVDS driveris50 Ω whichcauses theeffectivesignalswingattheinputtobe reducedby half.Ifa self-terminatedreceiverrequiresinputswing greaterthan250 mVpp (differential)as wellas AC couplingtoits inputs,thentheLVDS driverwiththedouble-terminatedarrangementinFigure34(b.)may notmeet theminimum inputswing requirement;alternatively,the LVPECL or HCSL output driverformat with AC couplingis recommended tomeet theminimum inputswingrequiredby theself-terminatedreceiver. When usingAC couplingwithLVDS outputs,theremay be a startupdelayobservedintheclockoutputdue to capacitorcharging.The examples inFigure34 use 0.1μF capacitors,butthisvaluemay be adjustedtomeet the startuprequirementsfortheparticularapplication. Figure34. DifferentialLVDS OperationwithAC Coupling toReceivers (a.)WithoutInternal100 Ω Termination (b.)With Internal100 Ω Termination LVPECL driversrequirea DC pathtoground.When AC couplingan LVPECL signaluse 160 Ω emitterresistors (or91 Ω forVcco = 2.5V) closetotheLVPECL drivertoprovidea DC pathtogroundas shown inFigure38.For properreceiveroperation,thesignalshouldbe biasedtotheDC biaslevel(common mode voltage)specifiedby thereceiver.The typicalDC biasvoltage(common mode voltage)forLVPECL receiversis2 V. Alternatively,a Theveninequivalentcircuitformsa validterminationas shown inFigure35 forVcco = 3.3V and 2.5V.Note:this Thevenincircuitisdifferentfrom theDC coupledexample inFigure33,sincethevoltagedividerissettingthe inputcommon mode voltageofthereceiver. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LMK00301

CLKoutX* (unused) R PD 50:Trace R PU Load Vcco R PD R PU Vcco LVPECL Driver R PU R PDVcco VTT 3.3V 2.5V 120: 250: 82: 62.5: ~1.3V 0.5V CLKoutX CLKoutX* 50: 50:Trace 50: Load Vcco - 2V Vcco - 2V LVPECL Driver CLKoutX CLKoutX* R TR T 0.1 PF 0.1 PF LVPECL Reciever 100:Trace (Differential) R PU R PD Vcco R PU R PD Vcco LVPECL Driver R PU R PDVcco VBB 3.3V 2.5V 82: 62.5: 120: 250: R T 160: 91: LMK00301 SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com Figure35. DifferentialLVPECL Operation,AC Coupling, Thevenin Equivalent TerminationforSingle-EndedOperation A baluncan be used witheitherLVDS or LVPECL driversto convertthe balanced,differentialsignalintoan unbalanced,single-endedsignal. Itispossibletouse an LVPECL driveras one ortwo separate800 mV p-psignals.When DC couplingone ofthe LMK00301 LVPECL driverofa CLKoutX/CLKoutX*pair,be suretoproperlyterminatetheunused driver.When DC couplingon oftheLMK00301 LVPECL drivers,theterminationshouldbe 50 Ω toVcco - 2 V as shown in Figure36.The Theveninequivalentcircuitisalsoa validterminationas shown inFigure37 forVcco = 3.3V. Figure36. Single-EndedLVPECL Operation,DC Coupling Figure37. Single-EndedLVPECL Operation,DC Coupling,Thevenin Equivalent

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CLKoutX* R TR T 0.1 PF 0.1 PF 50:Trace 50: Load 50: LVPECL Driver Vcco 3.3V 2.5V R T 160: 91: LMK00301 www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 When AC couplingan LVPECL driveruse a 160 Ω emitterresistor(or91 Ω forVcco = 2.5V) toprovidea DC pathtogroundand ensurea 50 Ω terminationwiththeproperDC biaslevelforthereceiver.The typicalDC bias voltageforLVPECL receiversis2 V. Ifthecompanion driverisnotused,itshouldbe terminatedwitheithera properAC orDC termination.Thislatterexample ofAC couplinga single-endedLVPECL signalcan be used to measure single-endedLVPECL performanceusinga spectrumanalyzeror phase noiseanalyzer.When using most RF testequipmentno DC biaspoint(0 VDC) isrequiredforsafeand properoperation.The internal50 Ω terminationthetestequipmentcorrectlyterminatestheLVPECL driverbeingmeasured as shown inFigure38. When usingonlyone LVPECL driverofa CLKoutX/CLKoutX* pair,be suretoproperlyterminatedtheunused driver. Figure38. Single-EndedLVPECL Operation,AC Coupling Power Supply and Thermal Considerations CurrentConsumption and Power DissipationCalculations The currentconsumptionvaluesspecifiedinElectricalCharacteristicscan be used tocalculatethetotalpower dissipationand IC power dissipationforany deviceconfiguration.The totalVCC coresupplycurrent(ICC_TOTAL ) can be calculatedusingEquation5: ICC_TOTAL = ICC_CORE + ICC_BANK_A + ICC_BANK_B + ICC_CMOS where

ICC_CORE isthecurrentforcorelogicand inputblocksand depends on selectedinput(CLKinXorOSCin).
ICC_BANK_A isthecurrentforBank A and depends on outputtype(ICC_PECL ,ICC_LVDS ,ICC_HCSL ,or0 mA if disabled).
ICC_BANK_B isthecurrentforBank B and depends on outputtype(ICC_PECL ,ICC_LVDS ,ICC_HCSL ,or0 mA if disabled).
ICC_CMOS isthecurrentfortheLVCMOS output(or0 mA ifREFout isdisabled). (5) Sincetheoutputsupplies(VCCOA ,VCCOB ,VCCOC ) can be powered from 3 independentvoltages,therespective outputsupplycurrents(ICCO_BANK_A ,ICCO_BANK_B ,ICCO_CMOS )shouldbe calculatedseparately. ICCO_BANK foreitherBank A orB can be directlytakenfromthecorrespondingoutputsupplycurrentspecification (ICCO_PECL ,ICCO_LVDS ,orICCO_HCSL )providedtheoutputloadingmatches thespecifiedconditions.Otherwise, ICCO_BANK shouldbe calculatedas follows: ICCO_BANK = IBANK_BIAS + (N *IOUT_LOAD ) where
IBANK_BIAS istheoutputbank biascurrent(fixedvalue).
IOUT_LOAD istheDC loadcurrentperloadedoutputpair.
N isthenumber ofloadedoutputpairsinthebank (N = 0 to5). (6) Table5 shows thetypicalIBANK_BIAS valuesand IOUT_LOAD expressionsforthe3 differentialoutputtypes. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com For LVPECL, itispossibletouse a largerterminationresistor(RT)togroundinsteadofterminatingwith50 Ω to VTT = Vcco - 2 V; thistechniqueiscommonly used toeliminatetheextraterminationvoltagesupply(VTT) and potentiallyreducedevicepower dissipationattheexpense ofloweroutputswing.For example,when Vcco is3.3 V, a R T valueof 160 Ω to ground willeliminatethe 1.3 V terminationsupplywithoutsacrificingmuch output swing.Inthiscase,thetypicalIOUT_LOAD is25 mA, so ICCO_PECL fora fully-loadedbank reducesto158 mA (vs. 165 mA with50 Ω resistorstoVcco -2 V). Table5.TypicalOutput Bank Bias and Load Currents CurrentParameter LVPECL LVDS HCSL IBANK_BIAS 33 mA 34 mA 6 mA IOUT_LOAD (VOH -VTT)/RT + (VOL -VTT)/RT 0 mA (No DC loadcurrent) VOH /RT Once thecurrentconsumptioniscalculatedorknown foreach supply,thetotalpower dissipation(PTOTAL )can be calculatedas: PTOTAL = (VCC *ICC_TOTAL )+ (VCCOA *ICCO_BANK_A )+ (VCCOB *ICCO_BANK_B )+ (VCCOC *ICCO_CMOS ) (7) Ifthe deviceconfigurationhas LVPECL or HCSL outputs,then itisalsonecessaryto calculatethe power dissipatedin any terminationresistors(PRT_ PECL and PRT_HCSL ) and in any terminationvoltages(PVTT ).The externalpower dissipationvaluescan be calculatedas follows: PRT_PECL (perLVPECL pair)= (VOH -VTT)2/RT + (VOL -VTT)2/RT (8) PVTT_PECL (perLVPECL pair)= VTT *[(VOH -VTT)/RT + (VOL -VTT)/RT] (9) PRT_HCSL (perHCSL pair)= VOH 2 /R T (10) Finally,theIC power dissipation(PDEVICE )can be computed by subtractingtheexternalpower dissipationvalues fromPTOTAL as follows: PDEVICE = PTOTAL -N 1*(PRT_PECL + PVTT_PECL )-N 2*PRT_HCSL where

N 1 isthenumber ofLVPECL outputpairswithterminationresistorstoVTT (usuallyVcco -2 V orGND).
N 2 isthenumber ofHCSL outputpairswithterminationresistorstoGND. (11) Power DissipationExample #1:SeparateVcc and Vcco SupplieswithUnused Outputs This example shows how to calculateIC power dissipationfora configurationwithseparateVCC and VCCO suppliesand unused outputs.Because some outputsare not used,the ICCO_PECL valuespecifiedinElectrical Characteristicscannotbe used directly,and outputbank current(ICCO_BANK ) shouldbe calculatedtoaccurately estimatetheIC power dissipation.
CLKin0/CLKin0*inputisselected.
Bank A isconfiguredforLVPECL: 4 pairsused withR T = 50 Ω toVT = Vcco -2 V (1pairunused).
Bank B isconfiguredforLVDS: 3 pairsused withR L = 100 Ω differential(2pairsunused).
REFout isdisabled.
TA = 85 °C Usingthecurrentand power calculationsfromtheprevioussection,we can compute PTOTAL and PDEVICE .
From Equation5:ICC_TOTAL = 8.5mA + 20 mA + 26 mA + 0 mA = 54.5mA
From Table5:IOUT_LOAD (LVPECL) = (1.6V -0.5V)/50Ω + (0.75V -0.5V)/50Ω = 27 mA
From Equation6:ICCO_BANK_A = 33 mA + (4*27 mA) = 141 mA
From Equation7:PTOTAL = (3.3V *54.5mA) + (3.3V *141 mA) + (2.5V *34 mA)] = 730 mW outputpair)
From Equation10:PRT_HCSL = 0 mW (noHCSL outputs)
From Equation11:PDEVICE = 730 mW -(4*(25.5mW + 13.5mW)) -0 mW = 574 mW

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www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 In thisexample,the IC devicewilldissipateabout 574 mW or 79% of the totalpower (730 mW), whilethe remaining21% willbe dissipatedintheemitterresistors(102 mW for4 pairs)and terminationvoltage(54 mW intoVcco -2 V). Based on the thermalresistancejunction-to-case(θJA) of 28.5 °C/W, the estimateddie junctiontemperature wouldbe about16.4°C above ambient,or101.4°C when TA = 85 °C. Power DissipationExample #2:Worst-Case Dissipation Thisexample shows how to calculateIC power dissipationfora configurationto estimateworst-casepower dissipation. In thiscase, the maximum supply voltageand supply currentvalues specifiedin Electrical Characteristicsareused.

Max VCC = VCCO = 3.465V.Max ICC and ICCO values.
CLKin0/CLKin0*inputisselected.
Banks A and B areconfiguredforLVPECL: alloutputsterminatedwith50 Ω toVT = Vcco -2 V.
REFout isenabledwith5 pF load.
TA = 85 °C Using themaximum supplycurrentand power calculationsfrom theprevioussection,we can compute PTOTAL and PDEVICE .
From Equation5:ICC_TOTAL = 10.5mA + 27 mA + 27 mA + 5.5mA = 70 mA
From ICCO_PECL max spec:ICCO_BANK_A = ICCO_BANK_B = 197 mA
From Equation7:PTOTAL = 3.465V *(70mA + 197 mA + 197 mA + 10 mA) = 1642.4mW (peroutputpair)
From Equation10:PRT_HCSL = 0 mW (noHCSL outputs)
From Equation11:PDEVICE = 1642.4mW -(10*(25.5mW + 39.5mW)) -0 mW = 992.4mW Inthisworst-caseexample,theIC devicewilldissipateabout992.4mW or60% ofthetotalpower (1642.4mW), whilethe remaining40% willbe dissipatedin the LVPECL emitterresistors(255 mW for10 pairs)and terminationvoltage(395mW intoVcco -2 V). Based on θJA of28.5°C/W, theestimateddiejunctiontemperaturewould be about28.3°C above ambient,or 113.3°C when TA = 85 °C. Power Supply Bypassing The Vcc and Vcco power suppliesshouldhave a high-frequencybypass capacitor,such as 0.1uF or 0.01uF, placedverycloseto each supplypin.1 uF to 10 uF decouplingcapacitorsshouldalsobe placednearby the device between the supply and ground planes.Allbypass and decouplingcapacitorsshould have short connectionstothesupplyand groundplanethrougha shorttraceorviatominimizeseriesinductance. Power Supply RippleRejection In practicalsystem applications,power supplynoise(ripple)can be generatedfrom switchingpower supplies, digitalASICs orFPGAs, etc.Whilepower supplybypassingwillhelpfilteroutsome ofthisnoise,itisimportantto understandtheeffectofpower supplyrippleon thedeviceperformance.When a single-tonesinusoidalsignalis appliedtothepower supplyofa clockdistributiondevice,such as LMK00301, itcan producenarrow-bandphase modulationas wellas amplitudemodulationon the clockoutput(carrier).In the single-sideband phase noise spectrum,theripple-inducedphase modulationappearsas a phase spurlevelrelativetothecarrier(measuredin dBc). For theLMK00301, power supplyripplerejection,or PSRR, was measured as thesingle-sidebandphase spur level(indBc) modulatedonto the clockoutputwhen a ripplesignalwas injectedonto the Vcco supply.The PSRR testsetupisshown inFigure39. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com Figure39. PSRR TestSetup A signalgeneratorwas used toinjecta sinusoidalsignalontotheVcco supplyoftheDUT board,and thepeak- to-peakrippleamplitudewas measured attheVcco pinsofthedevice.A limitingamplifierwas used toremove amplitudemodulationon thedifferentialoutputclockand convertittoa single-endedsignalforthephase noise analyzer.The phase spurlevelmeasurements were takenforclockfrequenciesof156.25MHz and 312.5MHz underthefollowingpower supplyrippleconditions:

Rippleamplitude:100 mVpp on Vcco = 2.5V
Ripplefrequencies:100 kHz,1 MHz, and 10 MHz Assuming no amplitudemodulationeffectsand smallindexmodulation,thepeak-to-peakdeterministicjitter(DJ) can be calculatedusingthemeasured single-sidebandphase spurlevel(PSRR) as follows: DJ (pspk-pk)= [(2*10(PSRR /20))/(π*fCLK )]*1012 (12) The “PSRR vs.RippleFrequency” plotsinTypicalPerformanceCharacteristicsshow theripple-inducedphase spurlevelsforthedifferentialoutputtypesat156.25MHz and 312.5MHz .The LMK00301 exhibitsverygood and well-behavedPSRR characteristicsacrossthe ripplefrequencyrange foralldifferentialoutputtypes.The phase spur levelsforLVPECL are below -64 dBc at 156.25 MHz and below -62 dBc at 312.5 MHz. Using Equation12,thesephase spurlevelstranslatetoDeterministicJittervaluesof2.57ps pk-pkat156.25MHz and 1.62ps pk-pkat312.5MHz. Testinghas shown thatthePSRR performanceofthedeviceimprovesforVcco = 3.3V underthesame rippleamplitudeand frequencyconditions. Thermal Management Power dissipationintheLMK00301 devicecan be highenough torequireattentiontothermalmanagement. For reliabilityand performancereasonsthedietemperatureshouldbe limitedtoa maximum of125 °C. Thatis,as an estimate,TA (ambienttemperature)plusdevicepower dissipationtimesθJA shouldnotexceed 125 °C. The package ofthedevicehas an exposed pad thatprovidestheprimaryheatremovalpathas wellas excellent electricalgroundingtotheprintedcircuitboard.To maximize theremovalofheatfrom thepackage a thermal landpatternincludingmultipleviastoa groundplanemust be incorporatedon thePCB withinthefootprintofthe package.The exposed pad must be soldereddown toensureadequateheatconductionoutofthepackage. A recommended landand viapatternisshown inFigure40.More informationon solderingWQFN packages can be obtainedat:http://www.ti.com/packaging.

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0.33 mm, typ 1.2 mm, typ 5.0 mm, min LMK00301 www.ti.com SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 Figure40. Recommended Land and ViaPattern To minimizejunctiontemperatureitisrecommended thata simpleheatsinkbe builtintothePCB (iftheground planelayerisnotexposed).Thisisdone by includinga copperarea ofabout2 squareincheson theopposite sideof the PCB from the device.Thiscopper area may be platedor soldercoatedto preventcorrosionbut shouldnot have conformalcoating(ifpossible),which couldprovidethermalinsulation.The viasshown in Figure40 shouldconnectthesetopand bottomcopperlayersand totheground layer.These viasactas “heat pipes” tocarrythethermalenergyaway from thedevicesideoftheboard towhere itcan be more effectively dissipated. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com

REVISION HISTORY

Changes from RevisionF (February2013)toRevisionG Page

Changed TargetApplicationsby addingadditionalapplicationstothesecond and thirdbullets,and removingHigh-
Changed thirdparagraphinDrivingtheClockInputssectiontoincludeCLKin*and LVCMOS text.Revisedtobetter
Added texttosecond paragraphofTerminationforAC CoupledDifferentialOperationtoexplaingraphicupdateto

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www.ti.com 3-May-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LMK00301SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LMK00301 LMK00301SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LMK00301 LMK00301SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LMK00301 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK00301SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK00301SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK00301SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2013 Pack Materials-Page 2

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Summary

LMK00301 3-GHz 10-Output Differential Clock Buffer/Level Translator

Description

LMK00301 3-GHz 10-Output Differential Clock Buffer/Level Translator

Source title LMK00301SQE/NOPB Datasheet(PDF) - Texas Instruments

Read LMK00301SQE/NOPB online.

LMK00301_13 TI1 | Alldatasheet

Document overview

Technical content

5 Output Pairs

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38 NC — any potentialwithintheSupplyVoltagerangestatedinAbsoluteMaximum

1 X OSCin

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0 Disabled(Hi-Z)

1 Enabled

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20 MHz Crystal

40 MHz Crystal

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0.1 PFR SCMOS

APPLICATION INFORMATION

0.1 PF50:Trace

0.1 PFR S

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REVISION HISTORY

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LMK00301SQE/NOPB specifications and overview.

More parts from the same family.