LMH0031VS/NOPB

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SMPTE 292M/259M Digital Video Deserializer / Descrambler

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 LMH0031SMPTE292M/259MDigitalVideoDeserializer/DescramblerwithVideo andAncillaryDataFIFOs Check forSamples: LMH0031 1FEATURES APPLICATIONS 2• SDTV/HDTV SerialDigitalVideo Standard • SDTV/HDTV Serial-to-ParallelDigitalVideo Compliant Interfacesfor:

Supports 270 Mbps, 360 Mbps, 540 Mbps, – Video EditingEquipment 1.483Gbps and 1.485Gbps SerialVideo Data – VTRs Rates withAuto-Detection – Standards Converters
LSB De-DitheringOption – DigitalVideo Routers and Switchers
Uses Low-Cost 27MHz Crystalor Clock – DigitalVideo Processingand EditingOscillatorReference Equipment
FastVCO Lock Time: < 500 µs at1.485Gbps – Video TestPatternGeneratorsand Digital
Built-inSelf-Test(BIST)and Video TestPattern Video TestEquipment Generator(TPG) – Video SignalGenerators (1) PatentApplicationsMade orPending DESCRIPTION• Automatic EDH/CRC Word and Flag Processing The LMH0031 SMPTE 292M / 259M DigitalVideo Deserializer/Descramblerwith Video and Ancillary• AncillaryData FIFO withExtensivePacket Data FIFOs is a monolithicintegratedcircuitthatHandlingOptions deserializesand decodes SMPTE 292M, 1.485Gbps• Adjustable,4-Deep ParallelOutput Video Data (or1.483Gbps)serialcomponent videodata,to20-bitFIFO paralleldata witha synchronizedparallelword-rate clock.Italsodeserializesand decodes SMPTE 259M,• FlexibleControland ConfigurationI/OPort 270Mbps, 360Mbps and SMPTE 344M (proposed)• LVCMOS Compatible ControlInputsand Clock 540Mbps serialcomponent video data, to 10-bitand Data Outputs paralleldata.Functionsperformedby the LMH0031
LVDS and ECL-Compatible,Differential,Serial include:clock/datarecoveryfrom the serialdata, Inputs serial-to-paralleldata conversion,SMPTE standard datadecoding,NRZI-to-NRZconversion,paralleldata• 3.3VI/OPower Supply and 2.5VLogic Power clockgeneration,word framing,CRC and EDH dataSupply Operation checkingand handling,AncillaryData extractionand• Low Power: Typically850mW automaticvideo formatdetermination.The parallel
64-PinTQFP Package video outputfeaturesa variable-depthFIFO which can be adjustedto delay the outputdata up to 4• Commercial Temperature Range 0°C to+70°C paralleldata clockperiods.AncillaryData may be selectivelyextractedfrom the paralleldata through the use of masking and controlbits in the configurationand controlregistersand storedinthe on-chip FIFO. Reverse LSB ditheringis also implemented. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SD/HD Encoder/ Serializer/ Cable Driver LMH0034 Adaptive Cable Equalizer 75: Coaxial Cable 1 PF 75: 1%SMPTE Video Data Input SMPTE 292M or 259M Serial Data VDD LMH0031 SD/HD Decoder/ Deserializer Parallel Ancilliary Data Input SMPTE Video Data Output Parallel Ancilliary Data Output 75: 1 PF LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) The uniquemulti-functionalI/OportoftheLMH0031 providesexternalaccesstofunctionsand datastoredinthe configurationand controlregisters.ThisfeatureallowsthedesignergreaterflexibilityintailoringtheLMH0031 to thedesiredapplication.The LMH0031 isauto-configuredtoa defaultoperatingconditionatpower-onor aftera resetcommand. Separatepower pinsforthePLL, deserializerand otherfunctionalcircuitsimprovepower supply rejectionand noiseperformance. The LMH0031 has a uniqueBuilt-InSelf-Test(BIST)and videoTestPatternGenerator(TPG).The BIST enables comprehensivetestingofthedeviceby theuser.The BIST uses theTPG as inputdataand includesSD and HD component videotestpatterns,referenceblack,PLL and EQ pathologicalsand a 75% saturation,8 vertical colourbarpattern,forallimplementedrasters.The colourbarpatternhas optionaltransitioncodingatchanges in thechroma and luma bardata.The TPG dataisoutputviatheparalleldataport. The LMH0030, SMPTE 292M / 259M DigitalVideo SerializerwithAncillaryData FIFO and IntegratedCable Driver,istheidealcomplement totheLMH0031. The LMH0031 's internalcircuitryispowered from+2.5Voltsand theI/Ocircuitryfroma +3.3Voltsupply.Power dissipationistypically850mW. The deviceispackaged ina 64-pinTQFP. TYPICAL APPLICATION

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TRS & FORMAT DETECTOR CONFIGURATION & CONTROL REGISTERS SMPTE NRZI-NRZ CONVERTER DESCRAMBLER/ DESERIALIZER EDH / CRC GENERATORS/CHECKERS PLL/CLOCK SYSTEM BIST & TPG RESET CONTROL FRAMING CONTROL DV[9:0] RESET SDI ANCILLIARY DATA FIFO MULTI-FUNCTION I/O PORT DV[19:10] AD[9:0] ANC / CTRL ACLK RD / WR I/O[7:0] INT. RESET SYSTEM MASTER CONTROLLER MASTER BUS DE-DITHERING PCLK VIDEO DATA FIFO & OUTPUT VCLK PCLK VIDEO DATA BUS SDI SDI BIAS R BB R REF INPUT DATA SAMPLERS CLOCK/DATA RECOVERY REFERENCE CLOCK/OSCILLATOR XTALi/Ext Clk XTALo PCLK LMH0031 www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Block Diagram Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMH0031

R V V V V V R BB RESET RD/WR SSPLL ANC/CTRL DDSI DDD SSIO SSSI SDI XTALo REF XTALi/Ext Clk VCLK SDI VSSD VDDD VSSIO LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Connection Diagram Figure1. 64-PinTQFP See Package Number PAG0064A

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) CMOS I/OSupplyVoltage(VDDIO –VSSIO ): 4.0V SDI SupplyVoltage(VDDSI –VSSSI): 4.0V DigitalLogicSupplyVoltage(VDDD –VSSD ): 3.0V PLL SupplyVoltage(VDDPLL –VSSPLL ): 3.0V CMOS InputVoltage(Vi): VSSIO −0.15VtoVDDIO +0.15V CMOS OutputVoltage(Vo): VSSIO −0.15VtoVDDIO +0.15V CMOS InputCurrent(singleinput): Vi= VSSIO −0.15V: −5 mA Vi= VDDIO +0.15V: +5 mA CMOS OutputSource/SinkCurrent:CMOS OutputSource/SinkCurrent: ±6 mA±6 mA IBB OutputCurrent: +300 μA IREF OutputCurrent: +300 μA SDI InputVoltage(Vi): VSSSI −0.15VtoVDDSI +0.15V Package ThermalResistance θJA @ 0 LFM Airflow 40.1°C/W θJA @ 500 LFM Airflow 24.5°C/W θJC 5.23°C/W StorageTemp. Range: −65°C to+150°C JunctionTemperature: +150°C Lead Temperature(Soldering4 Sec): +260°C ESD Rating(HBM): 6.0kV ESD Rating(MM): 400 V (1) AbsoluteMaximum Ratingsarethoseparametervaluesbeyond whichthelifeand operationofthedevicecannotbe ensured.The statinghereinofthesemaximums shallnotbe construedtoimplythatthedevicecan orshouldbe operatedatorbeyond thesevalues. The tableof“ElectricalCharacteristics”specifiesacceptabledeviceoperatingconditions. (2) Itisanticipatedthatthisdevicewillnotbe offeredina militaryqualifiedversion.IfMilitary/Aerospacespecifieddevicesarerequired, pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Symbol Parameter Conditions Reference Min Typ Max Units VDDIO CMOS I/OSupplyVoltage VDDIO −VSSIO 3.150 3.300 3.450 V VDDSD SDI SupplyVoltage VDDSI −VSSSI VDDD DigitalLogicSupplyVoltage VDDD –VSSD 2.375 2.500 2.625 V VDDPLL PLL SupplyVoltage VDDPLL –VSSPLL OperatingFreeAirTA 0 +70 °CTemperature Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Required InputConditions(1)(2) Symbol Parameter Conditions Reference Min Typ Max Units VIN InputVoltageRange VSSIO VDDIO VAllLVCMOS Inputstr,tf RiseTime,FallTime 10% –90% 1.0 1.5 3.0 ns SMPTE 259M, LevelC 270 SMPTE 259M, LevelD 360 BR SDI SerialInputData Rate SMPTE 344M SDI,SDI 540 M BPS SMPTE 292M 1,483 SMPTE 292M 1,485 VSSSI VDDSIVCM(SDI) Common Mode Voltage VIN = 125 mV P-P V+1.0V −0.05V VIN(SDI) SDI SerialInputVoltage, 125 800 880 mV P-PSingle-ended VIN(SDI) SDI SerialInputVoltage, SDI,SDI 125 800 880 mV P-PDifferential 20% –80%, SMPTE 259M 0.4 1.0 1.5 nsData Rates tr,tf RiseTime,FallTime 20% –80%, SMPTE 292M 270 psData Rates Ancillary/ControlData ClockfACLK VCLK MHzFrequency DC ACLK DutyCycle,AncillaryClock ACLK 45 50 55 % Ancillary/ControlClockandtr,tf 10% –90% 1.0 1.5 3.0 nsData RiseTime,FallTime SetupTime,AD N toACLK ortS 3.0 1.5 nsION toACLK RisingEdge ControlData Inputor ION ,AD N ,ACLK I/OBus Input TimingDiagramHoldTime,RisingEdge ACLKtH 3.0 1.5 nstoAD N orACLK toION BiasSupplyReferenceR REF Tolerance1% 4.75k ΩResistor fEXT CLK ExternalClockFrequency ExtClk −100 +10027.0 MHzppm ppmfXTAL CrystalFrequency See Figure7 XTALo, XTALi (1) RequiredInputConditionsaretheelectricalsignalconditionsorcomponent valueswhichshallbe suppliedby thecircuitinwhichthis deviceisused inorderforittoproducethespecifiedDC and AC electricaloutputcharacteristics. (2) Functionaland certainotherparametrictestsutilizea LMH0030 as theinputsourcetotheSDI inputsoftheLMH0031. The LMH0030 is DC coupledtotheinputsoftheLMH0031. TypicalVIN = 800 mV, VCM = 2.9V.

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 DC ElectricalCharacteristics Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1)(2). Symbol Parameter Conditions Reference Min Typ Max Units VIH InputVoltageHighLevel 2.0 VDDIO V VIL InputVoltageLow Level VSSIO 0.8AllLVCMOS InputsIIH InputCurrentHighLevel VIH = VDDIO (3) +85 +150 µA IIL InputCurrentLow Level VIL= VSSIO −1 −20 VOH OutputVoltageHighLevel IOH = −2 mA 2.4 2.7 VDDIO VSSIO VSSIOVOL OutputVoltageLow Level IOL = +2 mA VSSIO +0.3 +0.5V AllLVCMOS VVDDIOOutputsVOHV Minimum Dynamic VOH IOH = −2 mA (4) −0.5 VSSIOVOLP Maximum Dynamic VOL IOL = +2 mA (4) +0.4 VSDI SerialData InputVoltage 125 800 880 mV P-P ISDI SerialData InputCurrent SDI,SDI ±1 ±10 µA VTH InputThereshold Over VCM range <100 mV IBB BiasSupplyOutputCurrent R BB = 8.66kΩ 1% −220 −188 µA IREF ReferenceOutputCurrent R REF = 4.75kΩ 1% −290 −262 270M BPS Data Rate 80 120Power SupplyCurrent,2.5VIDD (2.5V) VDDD ,VDDPLL mASupply,Total 1,485MBPS Data Rate 220 340 (1) Currentflowintodevicepinsisdefinedas positive.Currentflowoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedto VSSIO = VSSD = VSSSI = 0V. (2) TypicalvaluesarestatedforVDDIO = VDDSI = +3.3V,VDDD = VDDPLL = +2.5V and TA = +25°C. (3) IIH includesstaticcurrentrequiredby inputpull-downdevices. (4) VOHV and VOLP aremeasured withrespecttoreferenceground.VOLP isthepeak outputLOW voltageorgroundbounce thatmay occur underdynamicsimultaneousoutputswitchingconditions.VOHV isthelowestoutputHIGH voltageoroutputdroopthatmay occurunder dynamicsimultaneousoutputswitchingconditions. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com AC ElectricalCharacteristics Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1). Symbol Parameter Conditions Reference Min Typ Max Units SerialVideo Data Inputs SMPTE 259M, LevelC 270 SMPTE 259M, LevelD 360 BR SDI SerialInputData Rate SMPTE 344M 540 M BPS SMPTE 292M 1,483 SDI,SDISMPTE 292M 1,485 20% –80%, SMPTE 259M 0.4 1.0 1.5 nsData Rates tr,tf RiseTime,FallTime 20% –80%, SMPTE 292M 270 psData Rates ParallelVideo Data Outputs SMPTE 259M, 270M BPS 27.0 SMPTE 267M, 360M BPS 36.0 VideoOutputClockfVCLK SMPTE 344M, 540M BPS VCLK 54.0 MHzFrequency SMPTE 292M, 1,483MBPS 74.176 SMPTE 292M, 1,485MBPS 74.25 PropagationDelay,Video VCLK toDV Ntpd 50% –50% 0.5 2.0 nsClocktoVideoData Valid TimingDiagram DC V DutyCycle,VideoClock VCLK 50±5 % 27MHz 2.0 36MHz 1.4VideoData OutputClocktJIT VCLK nsP-PJitter 54MHz 1.0 74.25MHz 0.5 ParallelAncillary/ControlData Inputs,Multi-functionParallelBus Inputs Ancillary/ControlData ClockfACLK VCLK MHzFrequency ACLK DutyCycle,AncillaryDataDC A ANC Data clock(2) 45 50 55 %Clock tr,tf OutputRiseTime,FallTime 10% –90% 1.0 1.5 3.0 SetupTime,AD N toACLK ortS ION ,AD N ,ACLK 3.0 1.5ION toACLK RisingEdge nsControlData InputorI/OBus TimingDiagram InputHoldTime,RisingEdge ACLKtH 3.0 1.5toAD N orACLK toION ParallelAncillary/ControlData Outputs PropagationDelay,Clocktotpd 8.5ControlData ACLK toAD N50% –50% nsTimingDiagramPropagationDelay,Clocktotpd 11.5AncillaryData Multi-functionParallelI/OBus IO0–IO7tr,tf RiseTime,FallTime 10% –90% 1.0 1.5 3.0 nsTimingDiagram PLL/CDR, Format Detect SD Rates(3) 0.32 1.0 tLOCK Lock DetectTime HD Rates(3) 0.26 1.0 ms tFORMAT FormatDetectTime AllRates 20 (1) TypicalvaluesarestatedforVDDIO = VDDSI = +3.3V,VDDD = VDDPLL = +2.5V and TA = +25°C. (2) When used toclockcontroldataintoorfromtheLMH0031, thedutycyclerestrictiondoes notapply. (3) Measured fromrising-edgeoffirstSDI cycleuntilLock Detectbitgoes high(true).Lock timeincludesCDR phase acquisitiontimeplus PLL locktime.

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Hi-Z test eqpt. t 5k: (attenuation 0dB) C L CMOS outputs VDDIO IOL IOH C L including probe and jig capacitance, 3pF max. S1 - open, S2 - closed for VOH measurement S1 - closed, S2 - open for VOL measurement LMH0031 www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 TestLoads Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMH0031

1.0 PF 1.0 PF 82.5: 82.5: +3.3 Vdc +2.5 Vdc

0 Vdc

2.5V Supply 3.3V Supply 2.5V Supply 3.3V Supply Output loads omitted for clarity. VSSPLL 12, 33, 20, 47, 6, 32, DV0 DV1 DV2 DV3 DV4 DV5 DV6 DV7 DV8 DV9 VCLK RESET DV10 DV11 DV12 DV13 DV14 DV15 DV16 DV17 DV18 DV19 RD / WR ANC / CTRL HD Chroma, SD Luma & Chroma HD Luma 4.7 PF 16V 0.1 PF (x2) (x2) 4.7 PF 16V 0.1 PF (x4) (x4) AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 ACLK IO1 IO0 IO2 IO3 IO4 IO5 IO6 IO7 XTALi/EXT CLK XTALo 825: 825: 8.66k 1 nF SDI SDI 26, 48

27 MHz

CLK. I/P 4.75k R REF Multi- function I/O Bus Ancilliary/ Control Bus LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com TestCircuit

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(ACLK) AD[9:0] INPUT DATA 50% 90% 10% 90% 10% 90% 10% tr, tf tr, tf DV[19:0] OUTPUT DATA tPD AD[9:0] OUTPUT DATA tPD LMH0031 www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Timing Diagram Device Operation INTRODUCTION The LMH0031 SMPTE 292M/259M DigitalVideo Deserializer/Decoderisused indigitalvideosignalorigination and destinationequipment:cameras,videotape recorders,telecines,editors,standardsconverters,videotest and otherequipment.Itdecodes and convertsserialSDTV orHDTV component digitalvideosignalsintoparallel format.The LMH0031 decoder/deserializerprocessesserialdigitalvideo(SDV) signalsconformingto SMPTE 259M, SMPTE 344M (proposed)orSMPTE 292M and operatesatserialdataratesof270 Mbps, 360 Mbps, 540 MHz, 74.176MHz and 74.25MHz. The LMH0031 acceptsECL or LVDS serialdata inputsignals.Outputssignalsare compatiblewithLVCMOS logicdevices. NOTE Inthefollowingexplanations,theselogicalequivalencesare observed:ON ≡ Enabled ≡ Set≡ True≡ Logic_1and OFF ≡ Disabled≡ Reset ≡ False≡ Logic_0. VIDEO DATA PATH The SerialData Inputs (SDI)acceptserialvideodata at SMPTE 259M standarddefinition,SMPTE 344M (proposed)orSMPTE 292M high-definitiondatarates.These inputsacceptstandardECL orLVDS signallevels and may be used single-endedor differentially.Inputsmay be DC or AC coupled,as required,todevicesand circuitssupplyingthe data.Recommended operatingconditionsand allinputDC and AC voltageand current specificationsshallbe observedwhen designingtheinputcouplingcircuits. For convenience,a referencebiassource,pinname R REF , setsthe referencecurrentavailablefrom the input biassource,pinname R BB .The recommended nominalvalueofR REF is4.75kΩ,1%. R BB isprovidedso thatthe SDI inputsmay be suppliedDC biasvoltageviaexternalresistorswhen the inputsare AC-coupled.The bias sourceshouldbe loadedwitha resistanceto the VSS supply.The sourcecurrentavailableat R BB is200µA. Figure2 shows a typicalinputbiasingscheme usingR BB and R REF . Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMH0031

82.5: 1 PF 1 nF 4.75 k: 8.66 k: SDI R BB R REF SDI LMH0031 825: 825:82.5: 1 PF LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Figure2. OptionalInputBiasingScheme The SMPTE descramblerreceivesNRZI serialdata,convertsittoNRZ, thendecodes ittoeither10-bitstandard definitionor20-bithighdefinitionparallelvideodatausingthereversepolynomialX9 + X4 + 1 as specifiedinthe respectivestandard:SMPTE 259M, SMPTE 344M (proposed)or SMPTE 292M. The datareceptionbitorderis LSB-first.Alldataprocessingisdone attheparallelrate. The LMH0031 incorporatescircuitrythatimplementsa method forhandlingdatathathas been subjectedtoLSB dithering.When so enabled,datafromthede-scramblerisroutedforde-dithering.The De-DitherEnable bitin the VIDEO INFO 0 controlregisterenablesthisfunction.De-ditheringof data presentinthe verticalblanking intervalcan be selectivelyenabledby use oftheV De-DitherEnable bitintheVIDEO INFO 0 controlregister. The initialconditionofDe-DitherEnable and V De-DitherEnable isOFF. The descramblersuppliessignalstotheTRS characterdetectorwhichidentifiesthepresenceofthevalidvideo data.The TRS characterdetectorprocessesthe timingreferencesignalswhich controlrasterframing.TRS (sync)charactersare detectedand thevideoisalignedon word boundaries.Data isre-synchronizedwiththe parallelword-rateclock.Interractionand operationof the characteralignmentcontrolsignalsand indicators Framing Mode ,Framing Enable and NSP (New Sync Position)isdescribedlaterinthisdatasheet. The LMH0031 implementsTRS characterLSB-clippingas prescribedinITU-R BT.601.LSB-clippingcauses all TRS characterswitha valuebetween 000h and 003h tobe forcedto000h and allTRS characterswitha value between 3FCh and 3FFh tobe forcedto3FFh.Clippingisdone afterdescramblingand de-dithering.

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Once the PLL attainslock,the video format detectorprocessesthe receiveddata to determinethe raster characteristics(videodataformat)and configuretheLMH0031 tohandleit.Thisassuresthattheparalleloutput datawillbe properlyformatted,thatthecorrectdatarateisselectedand thatAncillaryData and CRC/EDH data are correctlydetectedand checked.Supportedparalleldataformatsor sub-formatsmay belongtoany one of severalcomponent standards:SMPTE 125M, SMPTE 267M, SMPTE 260M, 274M, 295M or 296M. Referto Table 4 forthe supportedformats.(See alsothe ApplicationInformationsectionforhandlingof otherraster formatsorformatextensionsdevelopedafterthisdevicewas designed).The detectedvideostandardinformation ispassed to the devicecontrolsystem and saved inthe controlregistersfrom whence itmay be read by the user. The LMH0031 may be configuredto operatein a singlevideoformatby loadingthe appropriateFORMAT SET[4:0]controldataintotheFORMAT 0 controlregister.Also,theLMH0031 may be configuredtohandleonly thestandard-definitiondataformatsby settingtheSD ONLY bitoronlythehigh-definitiondataformatsby setting the HD ONLY bitinthe FORMAT 0 controlregister.When both bitsare reset,the defaultcondition,the part automaticallydetectsthedatarateand range. Alignedand de-processedparalleldata passes intoa variable-depthvideo FIFO priorto output.Video FIFO depth from 0 to 4 registersissetby a 3-bitword writtenintothe VIDEO FIFO Depth[2:0]bitsinthe ANC 0 controlregister.The videoFIFO permitsadjustmentoftheparallelvideodataoutputtimingordelayata parallel word rate.The occurenceof correspondingTRS indicatorbits,EAV, SAV and NSP, in the controlregister correspondstotheinputregisterpositionoftheFIFO.Thispositioningpermitsa look-aheadfunctioninwhichthe alignmentstatusofthevideodatacan be determinedup tofourparallelclockperiodspriortotheappearanceof thatdataattheparalleldataoutput. The parallelvideodataisoutputon DV[19:0].The 20-bitparallelvideodataisorganizedso thatforHDTV data, the upper-order10 bitsDV[19:10]are luminance(luma)informationand the lower10 bitsDV[9:0]are colour difference(chroma)information.SDTV data use the lower-order10-bitsDV[9:0]forboth luma and chroma information.(The SDTV paralleldataisalsoduplicatedon DV[19:10]).VCLK istheparalleloutputword rateclock signal.The frequencyofVCLK isappropriatetoeithertheHD orSD databeingprocessed.Data isvalidbetween the fallingedges of a VCLK cycle.Data may be clockedintoexternaldeviceson the rising-edgeof VCLK . The DV[19:0]and VCLK signalsareLVCMOS-compatible. ANCILLARY/CONTROL DATA PATH The 10-bitancillaryand ControlData PortAD[9:0]servestwo functionsintheLMH0031. AncillaryData from theAncillaryData FIFO isoutputfromthisportafteritsrecoveryfromthevideodatastream.The utilizationand flowof AncillaryData from the deviceismanaged by a system of controlbits,masks and IDs storedinthe controldata registers.This portalsoprovidesread/writeaccess to contentsof the configurationand control registers.The signalsRD/WR ,ANC/ CTRL and A CLK controldataflowthroughtheport. CONTROL DATA FUNCTIONS Control data is inputto and output from the LMH0031 using the lower-order8 bitsAD[7:0] of the ancillary/ControlData Port.Thiscontroldata initializes,monitorsand controlsoperationof the LMH0031. The upper two bitsAD[9:8]of the portfunctionas handshakingsignalswiththe deviceaccessingthe port.When eithera controlregisterreadorwriteaddressisbeingwrittentotheport,AD[9:8]must be drivenas 00b (0XXh, where XX are AD[7:0]).When controldataisbeingwrittentotheport,AD[9:8]must be drivenas 11b (3XXh, where XX areAD[7:0]).When controldataisbeingreadfromtheport,theLMH0031 willoutputAD[9:8]as 10b (2XXh,where XX areoutputdataAD[7:0])and may be ignoredby themonitoringsystem. NOTE Aftereithera manual orpower-onreset,A CLK must be toggledthree(3)timestocomplete initiallizationoftheAncillaryand ControlData Port. The sequence ofclockand controlsignalsforreadingcontroldatafromtheancillary/controldataportisshown in Figure3.Controldata read mode isinvokedby making theANC/ CTRL inputlow and theRD/WR inputhigh. The 8-bitaddressofthecontrolregistersettobe accessed isinputtotheporton bitsAD[7:0].To identifythe data as an address,AD[9:8]must be drivenas 00b. The completeaddress word willbe 0XXh, where 0 is AD[9:8]and XX are AD[7:0].The addressiscapturedon the risingedge ofA CLK . When controldata isbeing readfromtheport,theLMH0031 willoutputAD[9:8]as 10b (2XXh,where XX areoutputdataAD[7:0])and may be ignoredby the monitoringsystem.Data being outputfrom the selectedregisteris drivenby the port Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMH0031

ADDR DATA DATA ADDR ADDR DATAAD[7:0] WRITE EXTERNAL BUS MUST RELEASE INTERNAL BUS WILL RELEASE ACLK READ READ AD[9:8] AD[9] AD[8] DRIVEN REC'D DRIVEN REC'D DRIVEN DRIVEN AD[9] AD[8] AD[8] AD[9] AD[8] AD[9:8] LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com immediatelyfollowingthe risingedge of A CLK or when the address signalisremoved. For optimum system timing,thesignalsdrivingtheaddresstotheportshouldbe removed immediatelyaftertheaddressisclocked intotheportand beforeorsimultaneouslywiththefallingedge ofA CLK attheend ofthataddresscycle.Output dataremainsstableuntilthenextrisingedge ofA CLK and may be writtenintoexternaldevicesatany timeafter theremovaloftheaddresssignal.Thissecond clockresetstheportfromdrivetoreceiveand readiestheportfor anotheraccesscycle. Example: Read theFull-fieldFlagsviatheAD port. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-high. 3. Present001h toAD[9:0]as theregisteraddress. 4. ToggleA CLK . 5. Releasethebus drivingtheAD port. 6. Read thedatapresenton theAD port.The Full-fieldFlagsarebitsAD[4:0]. 7. ToggleA CLK toreleasetheAD port. Figure4 shows thesequence ofclockand controlsignalsforwritingcontroldatatotheancillary/controldataport. The controldata writemode issimilarto the read mode. Controldata writemode isinvokedby making the ANC/ CTRL inputlow and theRD/WR inputlow.The 8-bitaddressofthecontrolregistersettobe accessed is inputtotheporton bitsAD[7:0].When a controlregisterwriteaddressisbeingwrittentotheport,AD[9:8]must be drivenas 00b (0XXh, where XX are AD[7:0]).The address iscapturedon the risingedge of A CLK . The addressdataisremoved on thefallingedge ofA CLK .Next,thecontroldataispresentedtotheportbitsAD[7:0] and writtenintotheselectedregisteron thenextrisingedge ofA CLK .When controldataisbeingwrittentothe port,AD[9:8]must be drivenas 11b (3XXh,where XX are AD[7:0]).Controldatawrittenintotheregistersmay be readoutnon-destructivelyinmost cases. Example: Setup (withoutenabling)the TPG Mode viathe AD portusingthe 1125 line,30 frame,74.25MHz, interlacedcomponent (SMPTE 274M) colourbarsas testpattern.The TPG may be enabledaftersetupusingthe Multi-functionI/Oportorby thecontrolregisters. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-low. 3. Present00Dh toAD[9:0]as theTest0 registeraddress. 4. ToggleA CLK . 5. Present327h toAD[9:0]as theregisterdata. 6. ToggleA CLK . Figure3. ControlData Read Timing (2read and 1 writecycleshown)

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Figure4. ControlData WriteTiming AncillaryData Functions The LMH0031 can recoverAncillaryData from theserialdatastream.ThisAncillaryData and relatedcontrol charactersare definedintherelevantSMPTE standardsand may resideinthehorizontaland verticalblanking intervals.The datacan consistofdifferenttypesofmessage packetsincludingaudiodata.The serialAncillary Data space must be formattedaccordingto SMPTE 291M. The LMH0031 supports AncillaryData in the chrominance channel (C’r/C’b) only for high-definitionoperation.AncillaryData forstandarddefinition followstherequirementsofSMPTE 125M. The AncillaryData FIFO issizedtohandlea maximum lengthANC dataType 1 or Type 2 packetwithoutthe ANC Flag,259 words.DefinedinSMPTE 291M, thepacketconsistsoftheAncillaryData Flag,a 3-wordData ID and Data Count,255 8-or10-bitUser Data Words and a Checksum. The designoftheLMH0031 AncillaryData FIFO alsoallowsstorageofup to8 shorterlengthmessages withtotallengthnotexceeding259 words including allID information.AncillaryData iscopiedfrom the data stream intothe AncillaryData FIFO. The parallel AncillaryData willstillbe presentintheparallelchroma outputDV[9:0].ancillaryflaginformationisnotextracted intotheFIFO. CopyingofANC datafromthevideodataintotheFIFO iscontrolledby theANC Mask and ANC ID bitsinthe controlregisters.A system of flags,ANC FIFO Empty ,ANC FIFO 90% Full,ANC FIFO Fulland ANC FIFO Overrun are used to monitorFIFO status.The detailsand functionsof these and othercontrolwords are explainedlaterinthisdatasheet. Figure5 shows the relationshipof clock,data and controlsignalsforreadingAncillaryData from the port AD[9:0]. In AncillaryData read mode, 10-bitAncillaryData isroutedfrom the AncillaryData FIFO and read fromtheportAD[9:0]ata ratedeterminedby A CLK . AncillaryData read (output)mode isinvokedby making theANC/ CTRL inputhighand theRD/WR inputhigh. AncillaryData isclockedfromtheFIFO on theL-H transitionofA CLK .Data may be readfromtheporton rising edges ofA CLK ,afterthespecifiedpropagationdelay,untiltheFIFO isemptied.Data may onlybe readfromthe portwhen intheAncillaryData mode. AncillaryData cannotbe writtentotheport. To conservepower when theAncillaryData functionisnotbeingused,theinternalAncillaryData FIFO clockis disabled.Thisclockmust be enabledbeforeAncillaryData may be replicatedintothe FIFO foroutput.This internalFIFO clockiscontrolledby FIFO CLOCK ENABLE , bit-6of the ANC 5 register(address17h).The defaultconditionofFIFO CLOCK ENABLE isOFF. AfterenablingtheinternalFIFO clockby turningthisbitON, A CLK must be toggledthree(3)timestopropagatetheenabletotheclocktree. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMH0031

AD[9:0] READ DATA DATA DATADATADATA DATA DATA LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Figure5. AncillaryData Read Timing MULTI-FUNCTION I/OPORT The multi-functionI/O port can be configuredto provideimmediateaccess to many controland indicator functionsthatarestoredwithintheLMH0031 ’s configurationand controlregisters.The individualpinscomprising thisportareassignedas inputoroutputforselectedfunctionsstoredinthecontroldataregisters. The multi-functionI/Oportisconfiguredby way of an 8x6-bitregisterbank consistingof registersI/Opin 0 CONFIG throughI/Opin 7 CONFIG .The contentsoftheseregistersdeterminewhethertheportbitsfunctionas inputsoroutputsand towhichcontrolfunctionorindicatoreach portbitisassigned.Portbitsmay be assignedto accessdifferentfunctionsand indicatorsorany orallportbitsmay be assignedtoaccessthesame functionor indicator(outputmode only).The same indicatororfunctionshouldnotbe assignedtomore thanone portbitas an input.Controlsand indicatorsthatareaccessibleby theportand theircorrespondingselectionaddressesare given in the I/O Pin ConfigurationRegisterAddresses,Table 6. Table 2 gives the controlregisterbit assignments. Data resultingfromdeviceoperationwillbe senttotheselectedI/Oportbit.Thissame dataisalsostoredinthe configurationand controlregisters.Mapping thecontroland indicatorfunctionsinthismanner means thatdevice operationwillbe immediatelyreflectedattheI/Oportpinstherebyensuringmore reliablereal-timeoperationof thedevicewithinand by thehostsystem. When a multifunctionI/Oportbitisused as inputtoa controlregisterbit,datamust be presentedtotheI/Oport bitand clockedintotheregisterbitusingA CLK as shown inFigure6.Porttimingforbitwriteoperationsisthe same as fortheANC/ CTRL portoperation. Figure6. I/OPortData WriteTiming Example: Program multi-functionI/Oportbit-0as theCRC Luma Errorbitoutput. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-low. 3. Present00Fh toAD[9:0]as theI/OPIN 0 CONFIG registeraddress. 4. ToggleA CLK . 5. Present310h toAD[9:0]as theregisterdata. 6. ToggleA CLK .

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 EDH/CRC SYSTEM The LMH0031 has EDH and CRC charactergenerationand checking circuitry.The EDH system functionsas describedinSMPTE Recommended PracticeRP-165.The CRC system functionsas specifiedinSMPTE 292M. The EDH/CRC polynomial generators/checkersaccept paralleldata from the de-serializingsystem and generatetheEDH and CRC checkwords forcomparisonwiththosereceivedinthedata. The EDH Enable bitinthecontrolregisterenablestheEDH generationand checkingsystem.IncomingSDTV dataischecked forerrorsand theEDH flagsare updatedautomatically.EDH errorsare reportedintheEDH0, EDH1, and EDH2 registersetsoftheconfigurationand controlregisters. Updated ornew EDH check words and flagsmay be generatedand insertedinthedata.EDH check words are generatedusingthepolynomialX16 + X12 + X6 + 1 per SMPTE RP165. Generationand automaticinsertionof new or correctedEDH check words iscontrolledby EDH Force and EDH Enable bitsinthecontrolregisters. EDH check words and statusflagsareinsertedintheparalleldataatthecorrectpositionsintheAncillaryData space and formattedper SMPTE 291M. Aftera reset,theinitialstateofallEDH and CRC check charactersis 00h. The SMPTE 292M highdefinitionvideostandardemploys CRC (cyclicredundancycheck codes)errorchecking insteadofEDH. The CRC consistsoftwo 18-bitwords generatedusingthepolynomialX18 + X5 + X4 + 1 per SMPTE 292M. One CRC isused forluminanceand one forchrominancedata.The CRCs appear inthedata stream followingthe EAV and linenumber characters.The CRCs are checked and errorsare reportedinthe EDH0, EDH1, and EDH2 registersetsoftheconfigurationand controlregisters. PHASE-LOCKED LOOP /CLOCK-DATA RECOVERY SYSTEM The phase-lockedloop and clock-datarecovery(PLL/CDR) system generatesallinternaltimingand datarate clocksfortheLMH0031. The PLL/CDR system consistsoffivemain functionalblocks:1)theinputbufferwhich receivestheincomingdata,2)inputdatasamplerswhichoversamplethedatacoming fromtheinputbuffer,3)a PLL (VCO, dividerchain,phase-frequencydetectorand internalloopfilter)whichgeneratessamplingand other system clocks,4)a digitalCDR system torecovertheoversampledserialinputdatafromthesamplersand the digitalsystemcontroland 5)a ratedetectcontrollerwhichsequencesthePLL tofindthedatarate. Using an oversamplingtechnique,the timinginformationencoded inthe serialdata isextractedand used to synchronizetherecoveredclockand data.The paralleldatarateand otherclocksignalsare derivedfrom the regeneratedserialclock.The paralleldatarateclockis1/10thoftheserialdatarateclockforstandarddefinition or 1/20thof the serialdata clockfrequencyforhighdefinition.The data interfacebetween the CDR and the digitalprocessingblockuses 10-bitdataplustherequiredclocks. The PLL isheldincoarsefrequencylockby an external27MHz clocksignal,EXT CLK ,orby an external27MHz crystaland internaloscillator.Upon power-on,EXT CLK isthedefaultreference.The internaloscillatorand an externalcrystalmay be used as the referenceby settingthe OSCEN bitinthe CDR register. The reference clockreduceslocklatencyand enhances formatand auto-ratedetectionrobustness.PLL acquisition,dataphase alignmentand formatdetectiontimeis20ms or lessat1.485Mbps.The VCO has separateVDDPLL and VSSPLL power supplyfeeds,pins51 and 52,whichmay be suppliedpower viaan externallow-passfilter,ifdesired. Figure7. Crystaland Load Circuit A 27MHz crystaland loadcircuitmay be used toprovidethereferenceclock.A fundamentalmode crystalwith the followingparametersis used: frequency27MHz, frequencytolerance±30ppm, load capacitance18pF, maximum drivelevel100µW, equivalentseriesresistance<50Ω,operatingtemperaturerange0°C to70°C. Refer toFigure7 fora typicalloadcircuitand connectioninformation. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com The LMH0031 indicatesthatthePLL islockedtotheincomingdatarateand thattheCDR has acquireda phase oftheserialdataby settingtheLock DetectbitintheVideo Info0 controlregister.Indicationofthestandard beingprocessedisretainedintheFORMAT[4:0] bitsintheFORMAT 1 controldataregister.Format datafrom thisregistercan be programmed foroutputon the multi-functionI/Oport.The power-on defaultassignsLock Detectas I/OPortbit4. POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT The LMH0031 requirestwo power supplies,2.5V forthecorelogicfunctionsand 3.3V fortheI/Ofunctions.The suppliesmust be appliedto the devicein propersequence. The 3.3V supplymust be appliedpriorto or recommended thatthe3.3V supplybe configuredordesignedso as tocontrolapplicationofthe2.5V supplyin ordertosatisfythissequencingrequirement. The LMH0031 has an automatic,power-on-resetcircuit.Reset initializesthedeviceand clearsTRS detection circuitry,alllatches,registers,countersand polynomialgenerators/checkersand resetstheEDH/CRC characters to00h.An active-HIGH-true,manual resetinputisavailableatpin49.The resetinputhas an internalpull-down deviceand may be consideredinactivewhen unconnected. Important:When power isfirstappliedtothedeviceor followinga reset,theancillaryand ControlData Port must be initializedtoreceivedata.Thisisdone by togglingA CLK threetimes. TEST PATTERN GENERATOR (TPG) AND BUILT-INSELF-TEST (BIST) The LMH0031 includesan on-board,parallelvideotestpatterngenerator(TPG).Four testpatterntypesare availablein both HD and SD formats,NTSC and PAL standards,and 4x3 and 16x9 rastersizes.The test patternsare:flat-fieldblack,PLL pathological,equalizer(EQ) pathologicaland a 75%, 8-colourverticalbar pattern.The pathologicalsfollowrecommendationscontainedinSMPTE RP 178-1996 regardingthe testdata used.The colourbar patternhas optionalbandwidthlimitingcodinginthe chroma and luma data transitions between bars.The VPG FILTER ENABLE bitintheVIDEO INFO 0 controlregisterenablesthecolourbarfilter function.The testpatterndataisavailableatthevideodataoutputs,DV[19:0]witha correspondingparallelrate clock,VCLK ,appropriatetotheparticularstandardand formatselected. The TPG alsofunctionsas a built-inself-test(BIST)whichcan be used toverifydevicefunctionality.The BIST functionperformsa comprehensivego/no-gotestofthedevice.The testmay be runusingany oftheHD colour barpatternsorone oftwo SD patterns,eitherthe270 Mb/s NTSC colourbarorthePAL PLL pathological,as the testdata pattern.Data isinputfrom the digitalprocessingblock,processedthroughthe deviceand testedfor errorsusingeithertheEDH system forSD ortheCRC system forHD. ClocksignalsfromtheCDR blocksupply timingforthetestdata.The CDR must be supplieda 27MHz referenceclockviatheXTALi/ExtClk input(or usingtheinternaloscillatorand crystal)duringtheTPG orBIST function.A go/no-goindicationisloggedinthe Pass/FailbitoftheTEST 0 controlregisterset.Thisbitmay be assignedas an outputon themultifunctionI/O port. TPG and BIST operationisinitiatedby loadingthe code forthe desiredtestpatternintothe Test Pattern Select[5:0]bitsand by settingtheTPG Enable bitoftheTEST 0 register.Note thatwhen attemptingtouse the TPG orBIST immediatelyafterthedevicehas been resetorpowered on,theTPG defaultstothe270Mbps SD rate.The devicemust be configuredforthedesiredtestpatternby loadingtheappropriatecode intotheTEST 0 register.IfHD operationisdesired,selectionofthedesiredHD testpatternissufficienttoenablethedeviceto configureitselftorun atthecorrectrateand generatevaliddata.Table5 givestheavailabletestpatternsand codes. The Pass/Failbitinthecontrolregistergivesthedeviceteststatusindication.Ifno errorshave been detected, thisbitwillbe settologic-1approximately2 fieldintervalsafterTPG Enable isset.Iferrorshave been detected in the internalcircuitryof the LMH0031, Pass/Failwillremain resetto a logic-0.TPG or BIST operationis stoppedby resettingtheTPG Enable bit.ParalleloutputdataispresentattheDV[19:0]outputsduringTPG or BIST operation. Example: EnabletheTPG Mode touse theNTSC 270Mbps colourbarsas theBIST and TPG pattern.Enable TPG operationusingtheI/Oport. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-low. 3. Present00Dh toAD[9:0]as theTEST 0 registeraddress.

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 4. ToggleA CLK . 5. Present343h toAD[9:0]as theregisterdata(525 line,30 frame,27MHz, NTSC 4x3,colourbars(SMPTE 125M)). 6. ToggleA CLK . 7. The PASS/ FAIL indicator,TEST 0 register,Bit7,shouldbe readfortheresultofthetest.Alternatively,this bitmay be mapped to a convenientbitof the Multi-functionI/O bus. The testpatterndata and clockis availableattheDV[19:0]and VCLK outputs. CONFIGURATION AND CONTROL REGISTERS The configurationand controlregistersstoredatawhich determinestheoperationalmodes oftheLMH0031 or whichresultfromitsoperation.Many oftheseregistersmay be assignedas externalI/Ofunctionswhicharethen availableon themulti-functionI/Obus.These functionsaresummarized inTable1 and detailedinTable2.The power-ondefaultconditionforthemulti-functionI/OportisindicatedinTable1 and detailedinTable6. Table1.Configurationand ControlData RegisterSummary (1) AvailableonRegisterFunction Bits Read or Write InitialCondition NotesI/OBus EDH and CRC Operations CRC Error(SD/HD) 1 R Reset Output See (2)I/O5 CRC ErrorLuma 1 R Reset Output CRC ErrorChroma 1 R Reset Output CRC Replace 1 R/W OFF No See (3) Full-FieldFlags 5 R Reset No ActivePictureFlags 5 R Reset No ANC Flags 5 R Reset No EDH Force 1 R/W OFF Input EDH Enable 1 R/W ON Input F/FFlagError 1 R Reset Output A/P FlagError 1 R Reset Output ANC FlagError 1 R Reset Output AncillaryData Operations ANC Checksum Force 1 R/W OFF Input ANC Checksum Error 1 R Reset Output ANC FIFO Empty 1 R Set Output See (2)I/O6 ANC FIFO 90% Full 1 R Reset Output ANC FIFO Full 1 R Reset Output ANC FIFO Overrun 1 R Reset Output ANC ID 16 R/W 0000h No ANC Mask 16 R/W FFFFh No MSG Track 1 R/W OFF No MSG FlushStatic 1 R/W OFF No FIFO FlushStatic 1 R/W OFF No FullMSG Available 1 R OFF Output ShortMSG Detect 1 R OFF Output FIFO ClockEnable 1 R/W OFF No FIFO ExtractEnable 1 R/W OFF Input Video FIFO Operation VideoFIFO Depth 3 R/W 000b No (1) ON = SET = logic-1,OFF = RESET = logic-0(positivelogic). (2) ConnectedtomultifunctionI/Oportatpower-on. (3) Specialorrestrictedfunctionality.Refertotextfordetails. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Table1.Configurationand ControlData RegisterSummary (1)(continued) AvailableonRegisterFunction Bits Read or Write InitialCondition NotesI/OBus Video Format Operations FormatSet 5 R/W 00000B No SD Only 1 R/W OFF No HD Only 1 R/W OFF No Format 5 R Output Format4I/O3 H 1 R Output See (2)I/O2 V 1 R Output See (2)I/O1 F 1 R Output See (2)I/O0 FramingMode 1 R/W ON No FramingEnable 1 R/W ON Input New Sync Position(NSP) 1 R Output SAV 1 R Output EAV 1 R Output See (2)I/O7 De-scrambleEnable 1 R/W ON No NRZI Enable 1 R/W ON No LSB ClippingEnable 1 R/W ON No Sync DetectEnable 1 R/W ON No De-DitherEnable 1 R/W OFF Input Vert.De-DitherEnable 1 R/W OFF Input Lock Detect 1 R Output See (4)I/O4 Unscrambled 1 R/W OFF No See (5) VideoData Out TPG and BIST Operations TestPatternSelect 6 R/W 000000b Input 525/27MHz/Black TPG Enable 1 R/W OFF Input Pass/Fail 1 R Output VPG FilterEnable 1 R/W OFF Input ReferenceClock Operations ReferenceClock 2 R/W 00b No EXT CLK Enabled ExternalVclk 1 R/W OFF No See (5) MultifunctionI/OBus Operations I/OBus PinConfig. 48 R/W See Table6 No (4) ConnectedtomultifunctionI/Oportatpower-on. (5) Specialorrestrictedfunctionality.Refertotextfordetails. Table2.ControlRegisterBitAssignments Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EDH 0 (registeraddress 01h) CRC ERROR EDH FORCE EDH ENABLE F/FUES F/FIDA F/FIDH F/FEDA F/FEDH EDH 1 (registeraddress 02h) CRC CRC ERROR CRC ERROR A/P UES A/P IDA A/P IDH A/P EDA A/P EDHREPLACE LUMA CHROMA EDH 2 (registeraddress 03h) F/FFLAG A/P FLAG ANC FLAG ANC UES ANC IDA ANC IDH ANC EDA ANC EDHERROR ERROR ERROR ANC 0 (registeraddress 04h) VIDEO VIDEO VIDEO ANC FIFO ANC FIFO ANC FIFO ANC CHECK- ANC CHECK- FIFO-DEPTH(2) FIFO-DEPTH(1) FIFO-DEPTH(0) OVERRUN EMPTY FULL SUM ERROR SUM FORCE

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Table2.ControlRegisterBitAssignments (continued) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ANC 1 (registeraddress 05h) ANC ID(7) ANC ID(6) ANC ID(5) ANC ID(4) ANC ID(3) ANC ID(2) ANC ID(1) ANC ID(0) ANC 2 (registeraddress 06h) ANC ID(15) ANC ID(14) ANC ID(13) ANC ID(12) ANC ID(11) ANC ID(10) ANC ID(9) ANC ID(8) ANC 3 (registeraddress 07h) ANC MASK(7) ANC MASK(6) ANC MASK(5) ANC MASK(4) ANC MASK(3) ANC MASK(2) ANC MASK(1) ANC MASK(0) ANC 4 (registeraddress 08h) ANC ANC ANCANC MASK(15) ANC MASK(14) ANC MASK(13) ANC MASK(9) ANC MASK(8)MASK(12) MASK(11) MASK(10) ANC 5 (registeraddress 17h) FIFO EXTRACT FIFO CLOCK FULL MSG FIFO FLUSH MSG FLUSHreserved reserved MSG TRACKENABLE ENABLE AVAILABLE STATIC STATIC ANC 6 (registeraddress 18h) ANC FIFO SHORT MSG ANC PARITY reserved reserved reserved reserved VANC90% FULL DETECT MASK FORMAT 0 (registeraddress 0Bh) FRAMING FORMAT FORMAT FORMAT FORMAT FORMATSD ONLY HD ONLYMODE SET(4) SET(3) SET(2) SET(1) SET(0) FORMAT 1 (registeraddress 0Ch) F V H FORMAT(4) FORMAT(3) FORMAT(2) FORMAT(1) FORMAT(0) TEST 0 (registeraddress 0Dh) TEST TEST TEST TEST TESTTEST PATTERNPASS/FAIL TPG ENABLE PATTERN PATTERN PATTERN PATTERN PATTERNSELECT(5) SELECT(4) SELECT(3) SELECT(2) SELECT(1) SELECT(0) VIDEO INFO 0 (registeraddress 0Eh) VERT. DE-DE-DITHER VPG FILTER LOCK FRAMINGDITHER EAV SAV NSPENABLE ENABLE DETECT ENABLEENABLE VIDEO CONTROL 0 (registeraddress 55h) EXTERNAL SYNC DETECT LSB CLIP DE-Scramblereserved reserved NRZI ENABLE reservedVCLK ENABLE ENABLE ENABLE REFERENCE CLOCK (registeraddress 67h) reserved reserved reserved reserved reserved INT_OSC EN CLK EN reserved MULTI-FUNCTION I/OBUS PIN CONFIGURATION I/OPIN 0 CONFIG (registeraddress 0Fh) reserved reserved PIN 0 SEL[5] PIN 0 SEL[4] PIN 0 SEL[3] PIN 0 SEL[2] PIN 0 SEL[1] PIN 0 SEL[0] I/OPIN 1 CONFIG (registeraddress 10h) reserved reserved PIN 1 SEL[5] PIN 1 SEL[4] PIN 1 SEL[3] PIN 1 SEL[2] PIN 1 SEL[1] PIN 1 SEL[0] I/OPIN 2 CONFIG (registeraddress 11h) reserved reserved PIN 2 SEL[5] PIN 2 SEL[4] PIN 2 SEL[3] PIN 2 SEL[2] PIN 2 SEL[1] PIN 2 SEL[0] I/OPIN 3 CONFIG (registeraddress 12h) reserved reserved PIN 3 SEL[5] PIN 3 SEL[4] PIN 3 SEL[3] PIN 3 SEL[2] PIN 3 SEL[1] PIN 3 SEL[0] I/OPIN 4 CONFIG (registeraddress 13h) reserved reserved PIN 4 SEL[5] PIN 4 SEL[4] PIN 4 SEL[3] PIN 4 SEL[2] PIN 4 SEL[1] PIN 4 SEL[0] I/PPIN 5 CONFIG (registeraddress 14h) reserved reserved PIN 5 SEL[5] PIN 5 SEL[4] PIN 5 SEL[3] PIN 5 SEL[2] PIN 5 SEL[1] PIN 5 SEL[0] I/OPIN 6 CONFIG (registeraddress 15h) reserved reserved PIN 6 SEL[5] PIN 6 SEL[4] PIN 6 SEL[3] PIN 6 SEL[2] PIN 6 SEL[1] PIN 6 SEL[0] I/OPIN 7 CONFIG (registeraddress 16h) reserved reserved PIN 7 SEL[5] PIN 7 SEL[4] PIN 7 SEL[3] PIN 7 SEL[2] PIN 7 SEL[1] PIN 7 SEL[0] Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Table3.ControlRegisterAddresses AddressRegisterName Hexadecimal EDH 0 01 EDH 1 02 EDH 2 03 ANC 0 04 ANC 1 05 ANC 2 06 ANC 3 07 ANC 4 08 ANC 5 17 ANC 6 18 FORMAT 0 0B FORMAT 1 0C TEST 0 0D VIDEO INFO 0 0E I/OPIN 0 CONFIG 0F I/OPIN 1 CONFIG 10 I/OPIN 2 CONFIG 11 I/OPIN 3 CONFIG 12 I/OPIN 4 CONFIG 13 I/OPIN 5 CONFIG 14 I/OPIN 6 CONFIG 15 I/OPIN 7 CONFIG 16 VIDEO CONTROL 0 55 VIDEO CONTROL 1 56 REFERENCE CLOCK 67 EDH 0 (register01h) The EDH Full-FieldflagsF/F UES ,F/F IDA,F/F IDH,F/F EDA andF/F EDH aredefinedinSMPTE RP 165.The flagsareupdatedautomaticallywhen theEDH functionisenabledand dataisbeingreceived. The EDH ENABLE bit,when set,enablesoperationof the EDH generatorfunctionduringSD operation.The defaultconditionofthisbitisset(ON). The EDH FORCE bit,when set,causes updated EDH packetsto be insertedin the paralleloutputdata regardlessofthepreviousconditionofEDH checkwordsand flagsintheinputserialdata.Thisfunctionmay be used insituationswhere videocontenthas been editedthusmaking thepreviousEDH informationinvalid.The defaultconditionofthisbitisreset(OFF). The CRC ERROR bitindicatesthaterrorsineitherthe EDH checksums (SD) or CRC checkwords (HD) were detectedinthe serialinputdata.Thisbitisa combined functionwhich indicatesthe presenceof eitherEDH errorsduringSD operationorCRC errorsduringHD operation. EDH 1 (register02h) The EDH ActivePictureflagsA/P UES ,A/P IDA,A/P IDH,A/P EDA andA/P EDH are definedinSMPTE RP 165.The flagsareupdatedautomaticallywhen theEDH functionisenabledand dataisbeingreceived. Specifictypesof CRC errorsinincomingHD serialdata are reportedinthe CRC ERROR LUMA and CRC ERROR CHROMA bits. The CRC REPLACE bit,when set,causes theCRCs intheincomingdatatobe replacedwithCRCs calculated by theLMH0031. The bitisnormallyreset(OFF).

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 EDH 2 (register03h) The EDH AncillaryData flagsANC UES ,ANC IDA,ANC IDH,ANC EDA andANC EDH aredefinedinSMPTE RP 165.The flagsareupdatedautomaticallywhen theEDH functionisenabledand dataisbeingreceived. The statusof EDH flagerrorsin incomingSD serialdata are reportedin the ffFlagError, apFlagErrorand ancFlagErrorbits.Each ofthesebitsisthelogical-ORofthecorrespondingEDH and EDA flags. ANC 0 (Address 04h) The V FIFO Depth[2:0]bitscontrolthedepthofthevideoFIFO whichpreceedstheparalleloutputdatadrivers. The depthcan be setfrom0 to4 stagesby writingthecorrespondingbinarycode intothesebits.Forexample:to set the Video FIFO depth at two registers,load 11010XXXXXb intothe ANC 0 controlregister(where X representstheotherfunctionalbitsofthisregister). NOTE When changingsome but not allbitsina registerand to retainunchanged otherdata previouslystoredintheregister,readtheregister’s contentsand logically-ORthiswiththe new data.Then writethemodifieddataback intotheregister. FlagsforANC FIFO EMPTY ,ANC FIFO 90% FULL ,ANC FIFO FULL and ANC FIFO OVERRUN areavailable intheconfigurationand controlregisterset.These flagscan alsobe assignedas outputson themulti-function I/Oport.ANC FIFO EMPTY when setindicatesthattheFIFO containsno data.ANC FIFO 90% FULL indicates when theFIFO isat90% ofcapacity.Sinceitisvirtuallyimpossibleforthehostprocessortobeginextracting datafromtheFIFO afterithas been flaggedas fullwithoutthepossibilityofan overrunconditionoccurring,ANC FIFO 90% FULL isused as an advanced command tothehosttobeginextractingdatafrom theFIFO. To be used properly,ANC FIFO 90% FULL should be assignedas an outputon the multi-functionI/O portand monitoredby thehostsystem.Otherwise,inadvertentlossofancillarypacketdatacouldoccur.ANC FIFO FULL when setindicatesthattheFIFO registersarecompletelyfilledwithdata. The ANC FIFO OVERRUN flagindicatesthatan attempttowritedataintoa fullFIFO has occurred.ANC FIFO OVERRUN can be resetby readingthebit'sstatusviatheancillary/Controlport.Ifan overrunoccurrs,thestatus oftheFIFO message trackingwillbe invalidated.Inthisevent,theFIFO shouldbe flushedtoresetthemessage trackingpointers.Any messages thenintheFIFO willbe lost. The ANC Checksum Force bit,under certainconditions,enablestheoverwritingofAncillaryData checksums receivedin the data.Calculationand insertionof new AncillaryData checksums is controlledby the ANC Checksum Force bit.Ifa checksum errorisdetected(calculatedand receivedchecksums do notmatch)and the ANC Checksum Force bitisset,theANC Checksum Errorbitissetand a new checksum isinsertedinthe AncillaryData replacingthepreviousone.Ifa checksum errorisdetectedand theANC Checksum Force bitis not set,the checksum mismatch is reportedvia the ANC Checksum Error bit.ANC Checksum Error is availableas an outputon themultifunctionI/Oport. ANC 1 AND 2 (Addresses 05h and 06h) The extractionofAncillaryData packetsfromvideodataintotheFIFO iscontrolledby theANC MASK[15:0] and ANC ID[15:0]bitsinthecontrolregisters.The ANC ID[7:0]registernormallyissettoa valid8-bitcode used for component AncillaryData packetDID identificationas specifiedinSMPTE 291M-1998. Similarly,ANC ID[15:8] normallyissettoa valid8-bitcode used forcomponent AncillaryData packetSDID/DBN identification. ANC 3 AND 4 (Addresses 07h and 08h) The ANC MASK[7:0] isan 8-bitword thatcan be used toselectivelycontrolextractionofpacketswithspecific DIDs (orDID ranges)intothe FIFO. When the ANC MASK[7:0] issetto FFh, packetswithany DID can be extractedintotheFIFO.When any bitorbitsoftheANC MASK[7:0] aresettoa logic-1,thecorrespondingbitor bitsof the ANC ID[7:0]are a don't-carewhen matchingDIDs of packetsbeing extracted.When the ANC MASK[7:0] issetto00h,theANC DID ofincomingpacketsmust match exactly,bit-for-bittheANC ID[7:0]setin thecontrolregisterforthepacketstobe extractedintotheFIFO.The initialvalueoftheANC MASK[7:0] isFFh and theANC ID[7:0]is00h. Similarly,ANC MASK[15:8] isan 8-bitword thatcan be used to selectivelycontrolextractionof packetswith specificSDID/DBN (orSDID/DBN ranges)intotheFIFO.Operationand use ofthesebitsisthesame as forANC MASK[7:0] previouslydiscussed. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com ANC 5 (Address 17h) The FIFO EXTRACT ENABLE bitinthecontrolregistersenablesthedevicetoextractor copy AncillaryData fromthevideodatastreamand placeitintheANC FIFO.From theredatamay be outputviatheparallelancillary port.Data extractionis enabled when thisbitis set to a logic-1.This bitcan be used to delay automatic extractionand thereforethe outputof parallelAncillaryData.FIFO EXTRACT ENABLE shouldbe asserted duringan SAV or EAV to avoidtimingproblemswithAncillaryData extraction.Access to data inthe FIFO is controlledby theRD/WR ,ANC/ CTRL and A CLK controlsignals. To conservepower when theAncillaryData functionisnotbeingused,theinternalAncillaryData FIFO clockis disabled.Thisclockmust be enabledbeforeAncillaryData may be replicatedintothe FIFO foroutput.FIFO CLOCK ENABLE ,bit-6oftheANC 5 register(address17h),when set,enablesthisclocktopropagatetothe FIFO.The defaultconditionofFIFO CLOCK ENABLE isOFF. AfterenablingtheinternalFIFO clockby turning thisbitON, A CLK must be toggledthree(3)timestopropagatetheenabletotheclocktree.A CLK shouldremain runningatalltimeswhen theANC FIFO isinuse.Otherwise,message trackingand relatedfunctionswillnot operatecorrectly. The LMH0031 can keep trackof up to 8 ANC data packetsinthe ANC FIFO. Incomingpacketlengthversus availablespace inthe FIFO isalsotracked.The MSG TRACK bitinthe controlregisters,when set,enables trackingofpacketsintheFIFO.OtherfunctionsforcontrolofpackettrafficintheFIFO areFIFO FLUSH STAT and MSG FLUSH STAT .Iftheuserwishestohandlemore than8 messages, theMSG TRACK bitshouldbe turned off(reset).The operationFIFO FLUSH STAT willno longerwork and the functionFULL MSG AVAILABLE willno longerbe a reliableindicatorthatmessages are availableintheFIFO. The usermay still effectivelyuse theFIFO by monitoringthestatesofANC FIFO EMPTY ,ANC FIFO FULL ,ANC FIFO 90%FULL and ANC FIFO OVERRUN . SettingtheFIFO FLUSH STAT bittoa logic-1flushestheFIFO. FIFO FLUSH STAT may notbe setwhilethe FIFO is being accessed (Read or Write).FIFO FLUSH STAT is automaticallyresetafterthisoperationis complete. When MSG FLUSH STAT issettoa logic-1,theoldestmessage packetintheFIFO isflushedwhen dataisnot beingwrittentotheFIFO.MSG FLUSH STAT isautomaticallyresetafterthisoperationiscomplete. The FULL MSG AVAILABLE bitin the controlregisters,when set,notifiesthe host system thatcomplete packetsresideintheAncillaryData FIFO.When thisbitisnotset,themessages intheFIFO areincompleteor partial.Thisfunctionisnotaffectedby MSG TRACK .The FULL MSG AVAILABLE functionismost usefulwhen mapped tothemultifunctionI/Oportas an output. ANC 6 (Address 18h) The ANC FIFO 90% FULL flagbitindicateswhen the ANC FIFO is90% full.Thisbitmay be mapped to the multi-functionI/Oport.The purposeofthisflagistoprovidea signalwhichgivesthehostsystem timetobegin readingfrom theFIFO beforeithas thechance tooverflow.Thiswas done because itisvirtuallyimpossibleto monitortheFIFO FULL flagand beginextractingfromtheFIFO beforean overrunconditionoccurs. The SHORT MSG DETECT flagbitindicateswhen shortANC messages have been detected.i.e.An ANC header was detectedbeforethelastfullmessage was recovered.Thisbitmay be mapped tothemulti-function I/Oport. The ANC PARITY MASK bitwhen setdisablesparitycheckingforDID and SDID words intheANC datapacket. When reset,paritycheckingisenabled;and,ifa parityerroroccurs,thepacketwillnotbe extracted. The VANC bit,when set,enablesextractionof ANC data presentinthe verticalblankinginterval(bothactive videoand horizontalblankingportionsoftheline). FORMAT 0 (Address 0Bh) The LMH0031 may be settoprocessa singlevideoformatby writingtheappropriatedataintotheFORMAT 0 register.The Format Set[4:0]bitsconfinethe LMH0031 to recognizeand processonlyone of the fourteen specifiedtypeofSD orHD formatsdefinedby a particularSMPTE specification.The Format Set[4:0]bitsmay notbe used toconfinedeviceoperationtoa rangeofstandards.The availableformatsand codes aredetailedin Table4.Generallyspeaking,theFormat Set[4:0]codes indicateorgrouptheformatsas follows:Format Set[4] issetfortheHD dataformats,resetforSD dataformats.Format Set[3]issetforPAL dataformats(withthe exceptionof the SMPTE 274M 24-frameprogressiveformat),resetforNTSC data formats.Format Set[2:0] furthersub-dividethestandardsas giveninthetable.

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Table4.Video RasterFormat Parameters Format Frame ActiveCode Format Spec.(1) Lines ActiveLines SamplesRate Samples[4,3,2,1,0]

00001 SDTV, 54 RP 174 60I 525 507/487* 3432 2880

00010 SDTV, 36 SMPTE 267 60I 525 507/487* 2288 1920

00011 SDTV, 27 SMPTE 125 60I 525 507/487* 1716 1440

01001 SDTV, 54 ITU-R BT 601.5 50I 625 577 3456 2880 01010 SDTV, 36 ITU-R BT 601.5 50I 625 577 2304 1920 01011 SDTV, 27 ITU-R BT 601.5 50I 625 577 1728 1440 10001 HDTV, 74.25 SMPTE 260 30I 1125 1035 2200 1920 10010 HDTV, 74.25 SMPTE 274 30I 1125 1080 2200 1920 10011 HDTV, 74.25 SMPTE 274 30P 1125 1080 2200 1920 11001 HDTV, 74.25 SMPTE 274 25I 1125 1080 2640 1920 11010 HDTV, 74.25 SMPTE 274 25P 1125 1080 2640 1920 11100 HDTV, 74.25 SMPTE 295 25I 1250 1080 2376 1920 11101 HDTV, 74.25 SMPTE 274 24P 1125 1080 2750 1920 10100 HDTV, 74.25 SMPTE 296 (1,2) 60P 750 720 1650 1280 (1) Spec.isensuredby design. The HD Only bitwhen settoa logic-1lockstheLMH0031 intothehighdefinitiondatarangeand frequency.In systems designedto handleonlyhighdefinitionsignals,enablingHD Only reducesthe timerequiredforthe LMH0031 toestablishfrequencylockand determinetheHD formatbeingprocessed. The SD Only bitwhen set to a logic-1locksthe LMH0031 intothe standarddefinitiondata ranges and frequencies.Insystemsdesignedtohandleonlystandarddefinitionsignals,enablingSD Only reducesthetime requiredfortheLMH0031 toestablishfrequencylockand determinetheformatbeingprocessed.When SD Only and HD Only aresettologic-0,thedeviceoperatesinSD/HD mode. The Framing Mode bitintheFormat 0 registerand Framing Enable intheVideo Info0 registercombine with Framing Enable to controlthe manner in which the LMH0031 alignsframing.When Framing Mode and Framing Enable arebothreset,theLMH0031 alignson thefirstvalidTRS character.IfanotherTRS occursthat isnot on a word boundary,the NSP bitissetuntilthe nextTRS thatison a word boundary occurs.When Framing Mode issettoa logic-1,theLMH0031 operatessimilarlytotheCLC011 when NSP istiedtoFE. An alternativeconfigurationthatoperatesidenticallycan be achievedwiththe LMH0031 by mapping NSP as an outputand Framing Enable as an inputon theMultifunctionI/Obus and externallyconnectingthem.Inthiscase Framing Mode shouldbe resetto a logic-0.When Framing Mode isresetand Framing Enable isset,the LMH0031 realignson everyvalidTRS. The initialstateofFraming Mode issetfollowinga resetoratpower-on. FORMAT 1 (Address 0Ch) The LMH0031 automaticallydeterminesthe formatof the incomingserialdata.The resultof thisoperationis storedintheFORMAT 1 register.The Format[4:0]bitsidentifywhichofthemany possiblevideodatastandards thattheLMH0031 can processisbeingreceived.These formatcodes followthesame arrangementas forthe Format Set[4:0]bits.These formatsand codes aregiveninTable4.BitFormat[4]when setindicatesthatHD dataisbeingprocessed.When reset,SD dataisindicated.Format[3]when setindicatesthatPAL dataisbeing processed.When resetNTSC dataisbeingprocessed.Format[2:0]correspondwithone ofthesub-standards giveninthetable.Note thattheLMH0031 does notdistinguishorlogthedataratedifferencesbetween HD data at74.25Mhz and 74.25MHz/1.001. The H, V,and F bitscorrespondtoinputTRS databits6,7 and 8,respectively.The meaning and functionofthis dataisthesame forbothstandarddefinition(SMPTE 125M) and highdefinition(SMPTE 292M luminanceand colourdifference)videodata.Polarityislogic-1equalsHIGH-true.These bitsare registeredforthedurationof theapplicablefield. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com TEST 0 REGISTER (Address 0Dh) The Test PatternSelectbitsdeterminewhich testpatternisoutputwhen the Test PatternGenerator(TPG) mode ortheBuilt-inSelf-Test(BIST)mode isenabled.Table5 givesthecodes correspondingtothevarioustest patterns.AllHD colourbartestpatternsareinherentlyBIST data.BIST testpatternsforSD are:NTSC, 27MHz, 4x3 ColourBarsand PAL, 27MHz, 4x3 PLL Pathological. The TPG Enable bitwhen setto a logic-1enablesthe Test PatternGeneratorfunctionand built-inself-test (BIST). The Pass/Failbitindicatestheresultofthebuilt-inself-test.Thisbitisa logic-1fora pass condition. Table5.TestPatternSelectionCodes (1) TestPatternSelectWord Bits> Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1=HD 1=Progressive 00=Black 0=Interlaced 01=PLL Path. Video RasterStandard 0=SD 1=PAL 10=EQ Path. 0=NTSC 11=ColourBars 1125 Line,74.25MHz, 30 Frame InterlacedComponent (SMPTE 260M) Ref.Black 1 0 0 0 0 0 PLL Path. 1 0 0 0 0 1 EQ Path. 1 0 0 0 1 0 ColourBars 1 0 0 0 1 1 1125 Line,74.25MHz, 30 Frame InterlacedComponent (SMPTE 274M) Ref.Black 1 0 0 1 0 0 PLL Path. 1 0 0 1 0 1 EQ Path. 1 0 0 1 1 0 ColourBars 1 0 0 1 1 1 1125 Line,74.25MHz, 25 Frame InterlacedComponent (SMPTE 274M) Ref.Black 1 0 1 0 0 0 PLL Path. 1 0 1 0 0 1 EQ Path. 1 0 1 0 1 0 ColourBars 1 0 1 0 1 1 1125 Line,74.25MHz, 25 Frame InterlacedComponent (SMPTE 295M) Ref.Black 1 0 1 1 0 0 PLL Path. 1 0 1 1 0 1 EQ Path. 1 0 1 1 1 0 ColourBars 1 0 1 1 1 1 1125 Line,74.25MHz, 30 Frame ProgressiveComponent (SMPTE 274M) Ref.Black 1 1 0 0 0 0 PLL Path. 1 1 0 0 0 1 EQ Path. 1 1 0 0 1 0 ColourBars 1 1 0 0 1 1 1125 Line,74.25MHz, 25 Frame ProgressiveComponent (SMPTE 274M) Ref.Black 1 1 0 1 0 0 PLL Path. 1 1 0 1 0 1 EQ Path. 1 1 0 1 1 0 ColourBars 1 1 0 1 1 1 1125 Line,74.25MHz, 24 Frame ProgressiveComponent (SMPTE 274M) Ref.Black 1 1 1 0 0 0 PLL Path. 1 1 1 0 0 1 EQ Path. 1 1 1 0 1 0 (1) Note:BIST testpatternsforSD are:NTSC 4x3 ColourBarsand PAL 4x3 PLL Pathological.

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Table5.TestPatternSelectionCodes (1)(continued) TestPatternSelectWord Bits> Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ColourBars 1 1 1 0 1 1 750 Line,74.25MHz, 60 Frame ProgressiveComponent (SMPTE 296M) Ref.Black 1 1 1 1 0 0 PLL Path. 1 1 1 1 0 1 EQ Path. 1 1 1 1 1 0 ColourBars 1 1 1 1 1 1

525 Line,30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M)

Ref.Black 0 0 0 0 0 0 PLL Path. 0 0 0 0 0 1 EQ Path. 0 0 0 0 1 0 ColourBars(SD BIST) 0 0 0 0 1 1 625 Line,25 Frame, 27 MHz, PAL 4x3 (ITU-TBT.601) Ref.Black 0 1 0 0 0 0 PLL Path.(SD BIST) 0 1 0 0 0 1 EQ Path. 0 1 0 0 1 0 ColourBars 0 1 0 0 1 1

525 Line,30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M)

Ref.Black 0 0 0 1 0 0 PLL Path. 0 0 0 1 0 1 EQ Path. 0 0 0 1 1 0 ColourBars 0 0 0 1 1 1 625 Line,25 Frame, 36 MHz, PAL 16x9 (ITU-TBT.601) Ref.Black 0 1 0 1 0 0 PLL Path. 0 1 0 1 0 1 EQ Path. 0 1 0 1 1 0 ColourBars 0 1 0 1 1 1

525 Line,30 Frame, 54 MHz (NTSC)

Ref.Black 0 0 1 0 0 0 PLL Path. 0 0 1 0 0 1 EQ Path. 0 0 1 0 1 0 ColourBars 0 0 1 0 1 1

625 Line,25 Frame, 54 MHz (PAL)

Ref.Black 0 1 1 0 0 0 PLL Path. 0 1 1 0 0 1 EQ Path. 0 1 1 0 1 0 ColourBars 0 1 1 0 1 1 VIDEO INFO 0 REGISTER (Address 0Eh) Re-synchronizationof the parallelvideooutputdata withthe parallelrateclockiscontrolledby the functions Framing Enable, Framing Mode and NSP . For operatingdetailsabout these controlbits,referto the preceedingsectionabout Format Registers0 and 1 and the Format Mode bit.Framing Enable may be assignedas an inputon themulti-functionI/Oport. The NSP (New Sync Position)bitindicatesthata new or out-of-placeTRS characterhas been detectedinthe inputdata.Thisbitissettoa logic-1and remainssetforatleastone horizontallineperiodorunlessre-activated by a subsequentnew orout-of-placeTRS. Itisresetby an EAV TRS character. The EAV (end of activevideo)and SAV (startof activevideo)bitstrackthe occurrenceof the corresponding TRS characters. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com The Lock Detectisa logic-1when theloopislockedand theCDR has acquireda phase oftheincomingserial data.Thisbitmay be programmed as an outputon themulti-functionI/Obus.Thisbitismapped toI/Oportbit4 inthedefaultcondition. The VPG FilterEnable bitwhen setenablesoperationoftheVideo PatternGeneratorfilter.Operationofthis filtercauses theinsertionoftransitioncodes inthechroma and luma dataofcolourbartestpatternswhere these patternschange from one bar tothenext.Thisfilterreducesthemagnitudeofout-of-bandfrequencyproducts whichareproducedby abrupttransitionsinthechroma and luma datawhen fedtoD-to-Aconvertersand picture monitors. The LMH0031 incorporatescircuitrythatimplementsa method forhandlingdatathathas been subjectedtoLSB dithering. Data from the de-scramblerisroutedforde-dithering.Controlof thiscircuitryisviathe De-Dither Enable bitinthe VIDEO INFO 0 controlregister.Recovery of data thathas been ditheredduringthe vertical blankingintervalcan be selectivelyenabledby use oftheV De-DitherEnable bitintheVIDEO INFO 0 control register.The initialconditionofDe-DitherEnable and V De-DitherEnable isOFF. VIDEO CONTROL 0 (registeraddress 55h) The EXTERNAL VCLK bitisa specialapplicationfunctionwhichenablesuse ofan externalVCXO as a substitute forthe internallygeneratedVCLK . Additionalcircuitryisenabled withinthe LMH0031 which providesphase- frequencydetectionand controlvoltageoutputforthe VCXO. An externalloopfilterand voltageamplifierare requiredtointerfacethecontrolvoltageoutputtotheVCXO frequencycontrolinput.When thisfunctionisused, the R BB outputfunctionischanged from the biassupplyoutputto the controlvoltageoutputof the phase- frequencydetector.The VCLK outputchanges function,becoming the inputforthe VCXO signal.Use of this functionand requiredexternalsupportcircuitryisexplainedintheApplicationInformationsection. The SYNC DETECT ENABLE bit,when set,enablesdetectionofTRS characters.Thisbitisnormallyset(ON). The LSB CLIP ENABLE bit,when set,causes thetwo LSBs ofTRS characterstobe setto00b as describedin ITU-R BT.601.Thisfunctionisnormallyset(ON). The NRZI ENABLE bit,when set,enablesdatatobe convertedfromNRZI toNRZ. Thisbitisnormallyset(ON). The DE-SCRAMBLE ENABLE bit,when set,enables de-scramblingof the incoming data accordingto requirementsofSMPTE 259M orSMPTE 292M. Thisbitisnormallyset(ON). CAUTION The defaultstateofthisregisteris36h.Ifany ofthenormaloperatingfeaturesofthe descramblerare turnedoff,thisregister’s defaultdata must be restoredto resume normaldeviceoperation. REFERENCE CLOCK REGISTER (Address 67h) The Reference Clock registercontrolsoperationoftheCDR referenceclocksource.The CLKEN bitwhen reset toa logic-0enablestheoscillatorsignaltobe used by theLMH0031 as a reference.The defaultstateofthisbit atpower-onisenabled.Ingeneral,thisfunctionand bitshouldnotbe disabled.The INT_OSC EN bitenablesthe internalcrystaloscillatoramplifier.By defaultthisbitisa logic-0and isthereforeinactiveatpower-on.The device expectsan external27MHz referencereferenceclocksourceto be connectedto the XTALi/Ext Clk pinand activatedatpower-on. I/OPIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h) The I/OPin ConfigurationRegistersare used tomap individualbitsofthemulti-functionI/Oporttoselected bitsof the Configurationand ControlRegisters.Table 6 givesthe pinselectcodes forthe Configurationand Controlregisterfunctionsthatmay be mapped totheport.Pin[n]Select[5]controlswhethertheportpinisinput oroutput.The portpinwillbe an inputwhen thisbitissetand an outputwhen reset.Input-onlyfunctionsmay not be configuredas outputsand viceversa.The remainingfivePin[n]Select[4:0]bitsidentifytheparticularControl Registerbittobe mapped.

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www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Example: Program,viatheAD port,I/Oportbit0 as outputfortheCRC Luma Errorbitinthecontrolregisters. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-low. 3. Present00Fh toAD[9:0]as theI/OPIN 0 CONFIG registeraddress. 4. ToggleA CLK . 5. Present310h to AD[9:0]as the registerdata,the bitaddress of the CRC Luma Errorbitin the control registers. 6. ToggleA CLK . Table6.ControlRegisterBit,Pin[n]SEL[5:0]Codes forI/OPortPin Mapping (1) Pin[n]SEL[5:0]Codes I/PorRegisterBit Power-On StatusO/P[5] [4] [3] [2] [1] [0] HEX reserved 0 0 0 0 0 0 00 O/P FF FlagError 0 0 0 0 0 1 01 O/P AP FlagError 0 0 0 0 1 0 02 O/P ANC FlagError 0 0 0 0 1 1 03 O/P CRC Error(SD/HD) 0 0 0 1 0 0 04 O/P I/OPortBit5 Addresses05h and 06h arereserved ANC FIFO 90% FULL 0 0 0 1 1 1 07 O/P SHORT MSG DETECT 0 0 1 0 0 0 08 O/P FULL MSG AVAIL 0 0 1 0 0 1 09 O/P Addresses0Ah through0Ch arereserved SAV 0 0 1 1 0 1 0D O/P EAV 0 0 1 1 1 0 0E O/P I/OPortBit7 NSP 0 0 1 1 1 1 0F O/P CRC Luma Error 0 1 0 0 0 0 10 O/P CRC Chroma Error 0 1 0 0 0 1 11 O/P F 0 1 0 0 1 0 12 O/P I/OPortBit0 V 0 1 0 0 1 1 13 O/P I/OPortBit1 H 0 1 0 1 0 0 14 O/P I/OPortBit2 Format[0] 0 1 0 1 0 1 15 O/P Format[1] 0 1 0 1 1 0 16 O/P Format[2] 0 1 0 1 1 1 17 O/P Format[3] 0 1 1 0 0 0 18 O/P Format[4] 0 1 1 0 0 1 19 O/P I/OPortBit3 (SD/HD) FIFO Full 0 1 1 0 1 0 1A O/P FIFO Empty 0 1 1 0 1 1 1B O/P I/OPortBit6 Lock Detect 0 1 1 1 0 0 1C O/P I/OPortBit4 Pass/Fail 0 1 1 1 0 1 1D O/P FIFO Overrun 0 1 1 1 1 0 1E O/P ANC Chksum Error 0 1 1 1 1 1 1F O/P EDH Force 1 0 0 0 0 0 20 I/P TestPatternSelect[0] 1 0 0 0 0 1 21 I/P TestPatternSelect[1] 1 0 0 0 1 0 22 I/P TestPatternSelect[2] 1 0 0 0 1 1 23 I/P TestPatternSelect[3] 1 0 0 1 0 0 24 I/P TestPatternSelect[4] 1 0 0 1 0 1 25 I/P TestPatternSelect[5] 1 0 0 1 1 0 26 I/P (1) Note:AllLVCMOS inputshave internalpull-downdevicesexceptVCLK and ACLK. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LMH0031

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Table6.ControlRegisterBit,Pin[n]SEL[5:0]Codes forI/OPortPin Mapping (1)(continued) Pin[n]SEL[5:0]Codes I/PorRegisterBit Power-On StatusO/P[5] [4] [3] [2] [1] [0] HEX EDH Enable 1 0 0 1 1 1 27 I/P TPG Enable 1 0 1 0 0 0 28 I/P Addresses29h through2Bh arereserved VPG FilterEnable 1 0 1 1 0 0 2C I/P De-DitherEnable 1 0 1 1 0 1 2D I/P FramingEnable 1 0 1 1 1 0 2E I/P FIFO ExtractEnable 1 0 1 1 1 1 2F I/P PIN DESCRIPTIONS Pin Name Description

1 AD9 AncillaryData Output,ControlData Input

2 AD8 AncillaryData Output,ControlData Input

3 AD7 AncillaryData Output,ControlData Input

4 AD6 AncillaryData Output,ControlData Input

5 AD5 AncillaryData Output,ControlData Input

6 VSSD NegativePower SupplyInput(2.5Vsupply,DigitalLogic)

7 AD4 AncillaryData Output,ControlData Input

8 AD3 AncillaryData Output,ControlData Input

9 AD2 AncillaryData Output,ControlData Input

10 AD1 AncillaryData Output,ControlData Input

11 AD0 AncillaryData Output,ControlData Input

12 VDDD PositivePower SupplyInput(2.5Vsupply,DigitalLogic)

13 ACLK ancillary/ControlClockInput

14 IO7 Multi-FunctionI/OPort

15 IO6 Multi-FunctionI/OPort

16 IO5 Multi-FunctionI/OPort

17 IO4 Multi-FunctionI/OPort

18 IO3 Multi-FunctionI/OPort

19 IO2 Multi-FunctionI/OPort

20 VSSIO NegativePower SupplyInput(3.3Vsupply,I/O)

21 DV19 ParallelVideoOutput(HD=Luma)

22 DV18 ParallelVideoOutput(HD=Luma)

23 DV17 ParallelVideoOutput(HD=Luma)

24 DV16 ParallelVideoOutput(HD=Luma)

25 DV15 ParallelVideoOutput(HD=Luma)

26 VDDIO PositivePower SupplyInput(3.3Vsupply,I/O)

27 DV14 ParallelVideoOutput(HD=Luma)

28 DV13 ParallelVideoOutput(HD=Luma)

29 DV12 ParallelVideoOutput(HD=Luma)

30 DV11 ParallelVideoOutput(HD=Luma)

31 DV10 ParallelVideoOutput(HD=Luma)

32 VSSD NegativePower SupplyInput(2.5Vsupply,DigitalLogic) 33 VDDD PositivePower SupplyInput(2.5Vsupply,DigitalLogic)

34 DV9 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

35 DV8 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

36 DV7 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

ProductFolderLinks:LMH0031

www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name Description

37 DV6 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

38 DV5 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

39 VSSD NegativePower SupplyInput(2.5Vsupply,DigitalLogic)

40 DV4 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

41 DV3 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

42 DV2 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

43 DV1 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

44 DV0 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

45 IO1 Multi-FunctionI/OPort

46 IO0 Multi-FunctionI/OPort

47 VSSIO NegativePower SupplyInput(3.3Vsupply,I/O) 48 VDDIO PositivePower SupplyInput(3.3Vsupply,I/O)

49 RESET Manual ResetInput(HighTrue)

50 VCLK ParallelVideoData ClockOutput

51 VDDPLL PositivePower SupplyInput(2.5Vsupply,PLL) 52 VSSPLL NegativePower SupplyInput(2.5Vsupply,PLL)

53 R REF CurrentReferenceResistor

54 R BB SDI BiasSupplyResistor

55 VSSSI NegativePower SupplyInput(3.3Vsupply,SerialInput)

56 SDI SerialData Complement Input

57 SDI SerialData TrueInput

58 VDDSI PositivePower SupplyInput(3.3Vsupply,SerialInput) 59 VSSIO NegativePower SupplyInput(3.3Vsupply,I/O)

60 XTALi/EXT CLK CrystalorExternal27MHz ClockInput

61 XTALo Crystal(OscillatorOutput)

62 VDDD PositivePower SupplyInput(2.5Vsupply,DigitalLogic)

63 ANC/ CTRL ancillary/ControlData PortFunctionControlInput

64 RD/WR ancillary/ControlData PortRead/WriteControlInput

SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com ApplicationInformation A typicalapplicationcircuitfor the LMH0031 is shown in the ApplicationCircuitdiagram. This circuit demonstratesthecapabilitiesoftheLMH0031 and allowsitsevaluationina nativeconfiguration.An assembled demonstrationboardisavailable,partnumber SD131EVK. The boardmay be orderedthroughany ofTI'ssales offices.Complete circuitboard layoutsand schematicsfortheSD131EVK are availableon TI'sWEB site.For latestavailabilityinformation,pleasesee:www.ti.com/appinfo/interface. PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuitboardlayoutand stack-upfortheLMH0031 shouldbe designedtoprovidenoise-freepower tothedevice. Good layoutpracticealsowillseparatehighfrequencyor high-levelinputsand outputsfrom low-levelinputsto minimizeunwanted straynoisepickup,feedbackand interference.Power system performancemay be greatly improved by using thindielectrics(4 to 10 mils)forpower/groundsandwiches.This increasesthe intrinsic capacitanceofthePCB power system whichimprovespower supplyfiltering,especiallyathighfrequencies,and makes the valueand placementof externalbypass capacitorslesscritical.Externalbypass capacitorsshould includebothRF ceramicand tantalumelectrolytictypes.RF capacitorsmay use valuesintherange0.01µF to 0.1µF.Tantalumcapacitorsmay be intherange2.2µF to10 µF.Voltageratingfortantalumcapacitorsshould be atleast5X thepower supplyvoltagebeingused.Itisrecommended practicetouse two viasateach power pinoftheLMH0031 as wellas allRF bypass capacitorterminals.Dual viasreducetheinterconnectinductance by up tohalf,therebyextendingtheeffectivefrequencyrangeofthebypasscomponents. The outerlayersof the PCB may be floodedwithadditionalVSS (ground)plane.These planeswillimprove shieldingand isolationas wellas increasetheintrinsiccapacitanceofthepower supplyplanesystem.Naturally, tobe effective,theseplanesmust be tiedtotheVSS power supplyplaneatfrequentintervalswithvias.Frequent viaplacementalsoimprovessignalintegrityon signaltransmissionlinesby providingshortpaths forimage currentswhich reduces signaldistortion.The planesshouldbe pulledback from alltransmissionlinesand component mountingpads a distanceequaltothewidthofthewidesttransmissionlineor thethicknessofthe dielectricseparatingthetransmissionlinefromtheinternalpower orgroundplane(s)whicheverisgreater.Doing so minimizeseffectson transmissionlineimpedances and reduces unwanted parasiticcapacitancesat component mountingpads. Inespeciallynoisypower supplyenvironments,such as isoftenthecase when usingswitchingpower supplies, separatefilteringmay be used attheLMH0031's PLL and serialinputpower pins.The LMH0031 was designed forthissituation.The I/O,digitalsection,PLL and serialinputpower supplyfeedsareindependent(seetableand BlockDiagram fordetails).Supplyfilteringmay taketheformofL-sectionorpi-section,L-C filtersinserieswith these VDD inputs.Such filtersare availablein a singlepackage from severalmanufacturers.Device power suppliesmust be eithersequenced as describedin POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT and ideallyshouldbe appliedsimultaneouslyas froma common source. MAINTAINING OUTPUT DATA INTEGRITY The way inwhichtheTRS and othervideodatacharactersarespecifiedand arethereforeoutputinparallelform can resultinthesimultaneousswitchingofmany oftheLMH0031 ’s CMOS outputs.Such switchingcan leadto theproductionofoutputhighleveldrooporlowlevelgroundbounce.Giveninthespecifications,VOLP isthepeak outputLOW voltageor ground bounce and VOHV isthe lowestoutputHIGH voltageor outputdroop thatmay occurunder dynamic simultaneousoutputswitchingconditions.VOHV and VOLP are measured withrespectto referenceground.CarefulattentiontoPCB layout,power pinconnectionstothepower planesand timingofthe outputdata clockingcan reduce these effects.Considerationmust alsobe givento the timingallocatedto externalcircuitswhichsample theoutputs. The effectsofsimultaneousoutputswitchingon outputlevelsmay be minimizedby adoptinggood PCB layout and dataoutputtimingpractices,especiallycriticalatHD datarates.The power pinsfeedingtheI/Oshouldhave low inductanceconnectionstothepower and ground planes.Itisrecommended thattheseconnectionsuse at leasttwo viasper power or ground pin.Shortinterconnectingtracesconsistentwithgood layoutpracticesand solderingrulesmust be used.Samplingor clockingofdataby externaldevicesshouldbe so timedas totake maximum advantageofthesteady-stateportionoftheparalleloutputdatainterval.The LMH0031 isdesignedso thatvideodatawillbe stableatthepositive-goingtransitionofVCLK .Data shouldnotbe sampled closetothe data transitionintervalsassociatedwiththe negative-goingclockedge. The specifiedpropagationdelayand clockto data timingparametersmust be observed.When data isbeing sampled from the videodata port togetherwiththeANC portand/orI/Oport,itisrecommended thatthesamplingclocksbe synchronizedwiththe videoclock,VCLK ,tominimizepossibleeffectsfromgroundbounce oroutputdroopon sampled signallevels.

ProductFolderLinks:LMH0031

www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 PROCESSING NON-SUPPORTED RASTER FORMATS The number and type of HD rasterformatshas proliferatedsincethe LMH0031 was designed.Though not specificallycapableoffullyorautomaticallyprocessingthesenew formats,theLMH0031 may stillbe capableof deserializingthem.The userisencouragedtoexperimentwithprocessingtheseformats,keepinginmind that theLMH0031 has notbeen testedtohandleformatsotherthanthosedetailedinTable4.Therefore,theresults from attemptsto processnon-supportedformatsisnot ensured.The followingguidelinesconcerningdevice setupareprovidedtoaidtheuserinconfiguringtheLMH0031 toattemptlimitedprocessingoftheseotherraster formats. Ingeneral,thedeviceisconfiguredtodefeatitsautomaticformatdetectionfunctionand tolimitoperationtoa generalHD format.(The user shouldconsultTable 4 forguidanceon the formatgroups similarto the non- supportedone tobe processed).Sincemost non-supportedformatsare intheHD group,theLMH0031 should be configuredtooperateinHD-ONLY mode by settingbit-5oftheFORMAT 0 register(address0Bh).Also,the deviceshouldbe furtherconfiguredby loadingtheFORMAT SET[4:0]bitsofthisregisterwiththegeneralHD sub-formatcode.Inaddition,sincecontroldataisbeingwrittentotheport,AD[9:8]must be drivenas 11b.The completedataword forthisgeneralHD sub-formatcode withHD-ONLY bitsetis33Fh.Sincethisformatdiffers fromthoseinthetable,theEAV/SAV indicatorsaredisabled.Withouttheseindicators,linenumberingand CRC processingare disabledand ANC dataextractionwillnotfunction.Outputvideochroma and luma datawillbe word-aligned.Post-processingoftheparalleldataoutputfrom theLMH0031 willbe needed toimplementCRC checkingorlinenumber tracking. USING EXTERNAL VCXO FOR VCLK The EXTERNAL VCLK bitofVIDEO CONTROL 0 (registeraddress55h) isa specialapplicationfunctionwhich enablesuse ofan externalVCXO as a substitutefortheinternallygeneratedVCLK .Additionalcircuitryisenabled withinthe LMH0031 which providesphase-frequencydetectionand controlvoltageoutputforthe VCXO. An externalloop filterand voltageamplifierare requiredto interfacethe controlvoltageoutputto the VCXO frequencycontrolinput.When thisfunctionisused,the R BB outputfunctionischanged from the biassupply outputto the controlvoltageoutputof the phase-frequencydetector.The VCLK outputchanges function, becoming theinputfortheVCXO signal. Figure8 shows an example usingdualVCXOs forVCLK tohandlebothstandardand highdefinitionvideo. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LMH0031

100 k: 182 k: VCTRL FOUT LMC7101 +3.3V VCTRL FOUT +3.3V NC7SZ126

74.25 MHz

27.00 MHz

22.1 k: 100 pF 10 nF 4.75 k: DV[19:0] To other logic or serializer CAUTION! Read text before using this circuit. NC7SZ125 NC7SZ08 CLC031 IO3 - SD/HD CLC031 IO4 - Lock Detect OE OE 22.1: 22.1: LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Figure8. Using Dual VCXOs forVCLK Example The controlvoltageoutputfromR BB isexternallyfilteredby theloopfilterconsistingofa 22.1kΩ resistorinseries witha 10nF capacitor,combined inparallelwitha 100pF capacitor.Thisgivesa loopbandwidthof1.5kHz.Since thecontrolvoltageislimitedtoaround2.1V,itrequiresa levelshiftertogettheentirepullrangeon theVCXO. TI'sLMC7101 isrecommended with100kΩ and 182kΩ resistorsas shown inFigure8 toprovidea gainof1.55, sufficienttodrivea 3.3VVCXO. Recommended VCXOs from SaRonix (141 JeffersonDrive,Menlo Park, CA 94025, USA) includethe ST1308AAB-74.25 forhigh definitionand the ST1307BAB-27.00 forstandarddefinition.Dual VCXOs require some supportinglogictoselecttheappropriateVCXO. Thisrequirestheuse ofFormat4 and Lock Detect,whicharemapped atpower-ontoI/OPortBit3 and I/OPortBit4,respectively.These two signalspass throughan AND gate(FairchildSemiconductor'sNC7SZ08 orsimilar).Itsoutputishighwhen bothLock Detect and Format[4]are high,which indicatesa validhigh-definitionsignalispresent.The VCXOs are bufferedto controlthetransitiontimesand toalloweasy selection.The outputoftheAND gateisused tocontroltheOutput Enable (OE) functionof the buffers.The 74.25MHz VCXO isbufferedwiththe NC7SZ126 withthe AND gate outputconnectedtotheOE pinoftheNC7SZ126, and the27.00MHz VCXO isbufferedwiththeNC7SZ125 with the AND gate outputconnectedto the OE pin of the NC7SZ125. This circuituses the 27.00MHz VCXO as defaultand enablesthe 74.25MHz VCXO when a validhigh-definitionsignalispresent.The outputsfrom the buffersare daisy-chainedtogetherand sentto the LMH0031's VCLK inadditionto otherdevices,such as the LMH0030 serializer.

ProductFolderLinks:LMH0031

www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013

REVISION HISTORY

www.ti.com 24-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMH0031VS NRND TQFP PAG 64 160 TBD Call TI Call TI 0 to 70 L031 LMH0031VS/NOPB ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 L031 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 24-Nov-2013 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 4040282/C 11/96 Gage Plane 0,17 0,27 7,50 TYP SQ 9,80 1,05 0,95 11,80 12,20 1,20 MAX 10,20 SQ 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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Product Information

LMH0031VS/NOPB specifications and overview.

Summary

SMPTE 292M/259M Digital Video Deserializer / Descrambler

Description

SMPTE 292M/259M Digital Video Deserializer / Descrambler

Source title LMH0031VS/NOPB Datasheet(PDF) - Texas Instruments

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LMH0031 TI1 | Alldatasheet

Document overview

Technical content

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0 Vdc

27 MHz

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00001 SDTV, 54 RP 174 60I 525 507/487* 3432 2880

00010 SDTV, 36 SMPTE 267 60I 525 507/487* 2288 1920

00011 SDTV, 27 SMPTE 125 60I 525 507/487* 1716 1440

26 SubmitDocumentationFeedback Copyright© 2006–2013,Texas InstrumentsIncorporated

525 Line,30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M)

525 Line,30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M)

525 Line,30 Frame, 54 MHz (NTSC)

625 Line,25 Frame, 54 MHz (PAL)

28 SubmitDocumentationFeedback Copyright© 2006–2013,Texas InstrumentsIncorporated

1 AD9 AncillaryData Output,ControlData Input

2 AD8 AncillaryData Output,ControlData Input

3 AD7 AncillaryData Output,ControlData Input

4 AD6 AncillaryData Output,ControlData Input

5 AD5 AncillaryData Output,ControlData Input

7 AD4 AncillaryData Output,ControlData Input

8 AD3 AncillaryData Output,ControlData Input

9 AD2 AncillaryData Output,ControlData Input

10 AD1 AncillaryData Output,ControlData Input

11 AD0 AncillaryData Output,ControlData Input

13 ACLK ancillary/ControlClockInput

14 IO7 Multi-FunctionI/OPort

15 IO6 Multi-FunctionI/OPort

16 IO5 Multi-FunctionI/OPort

17 IO4 Multi-FunctionI/OPort

18 IO3 Multi-FunctionI/OPort

19 IO2 Multi-FunctionI/OPort

21 DV19 ParallelVideoOutput(HD=Luma)

22 DV18 ParallelVideoOutput(HD=Luma)

23 DV17 ParallelVideoOutput(HD=Luma)

24 DV16 ParallelVideoOutput(HD=Luma)

25 DV15 ParallelVideoOutput(HD=Luma)

27 DV14 ParallelVideoOutput(HD=Luma)

28 DV13 ParallelVideoOutput(HD=Luma)

29 DV12 ParallelVideoOutput(HD=Luma)

30 DV11 ParallelVideoOutput(HD=Luma)

31 DV10 ParallelVideoOutput(HD=Luma)

34 DV9 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

35 DV8 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

36 DV7 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

30 SubmitDocumentationFeedback Copyright© 2006–2013,Texas InstrumentsIncorporated

37 DV6 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

38 DV5 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

40 DV4 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

41 DV3 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

42 DV2 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

43 DV1 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

44 DV0 ParallelVideoOutput(HD=Chroma, SD=Luma & Chroma)

45 IO1 Multi-FunctionI/OPort

46 IO0 Multi-FunctionI/OPort

49 RESET Manual ResetInput(HighTrue)

50 VCLK ParallelVideoData ClockOutput

53 R REF CurrentReferenceResistor

54 R BB SDI BiasSupplyResistor

56 SDI SerialData Complement Input

57 SDI SerialData TrueInput

60 XTALi/EXT CLK CrystalorExternal27MHz ClockInput

61 XTALo Crystal(OscillatorOutput)

63 ANC/ CTRL ancillary/ControlData PortFunctionControlInput

64 RD/WR ancillary/ControlData PortRead/WriteControlInput

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