LMH0030VS/NOPB

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 LMH0030SMPTE292M/259MDigitalVideoSerializerwithVideoandAncillaryDataFIFOs andIntegratedCableDriver Check forSamples: LMH0030 1FEATURES APPLICATIONS 2• SDTV/HDTV SerialDigitalVideo Standard • SDTV/HDTV Parallel-to-SerialDigitalVideo Compliant Interfacesfor:

Supports 270 Mbps, 360 Mbps, 540 Mbps, – Video Cameras 1.4835Gbps and 1.485Gbps SDV Data Rates – VTRs withAuto-Detection – Telecines
Low Output Jitter:125ps max, 85ps typical – DigitalVideo Routers and Switchers
Low Power: Typically430mW – DigitalVideo Processingand Editing
No ExternalSerialData Rate Settingor VCO Equipment FilteringComponents Required* – Video TestPatternGeneratorsand Digital
FastPLL Lock Time: < 150µs Typicalat1.485 Video TestEquipment Gbps – Video SignalGenerators
AdjustableDepth Video FIFO forTiming Alignment DESCRIPTION
Built-inSelf-Test(BIST)and Video TestPattern The LMH0030 SMPTE 292M/259M DigitalVideo Generator(TPG)* (1) Serializerwith AncillaryData FIFO and Integrated Cable Driveris a monolithicintegratedcircuitthat• Automatic EDH/CRC Word and Flag encodes, serializesand transmitsbit-paralleldigitalGenerationand Insertion video data conformingto SMPTE 125M and 267M• On-Chip AncillaryData FIFO and Insertion standarddefinition,10-bitwide component videoand ControlCircuitry SMPTE 260M, 274M, 295M and 296M high-definition, 20-bit wide component video standards. The• FlexibleControland ConfigurationI/OPort LMH0030 operatesatSMPTE 259M serialdatarates• LVCMOS Compatible Data and ControlInputs of270 Mbps, 360 Mbps, theSMPTE 344M serialdataand Outputs rateof540 Mbps, and theSMPTE 292M serialdata
75Ω ECL-Compatible,Differential,SerialCable- ratesof1483.5and 1.485Gbps. The serialdataclock DriverOutputs frequencyis internallygenerated and requiresno externalfrequency setting,trimming or filtering• 3.3VI/OPower Supply and 2.5VLogic Power components.Supply Operation
64-pinTQFP Package (1) *Patentapplicationsmade orpending. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SD/HD Encoder/ Serializer/ Cable Driver LMH0034 Adaptive Cable Equalizer 75: Coaxial Cable 1PF 75: SMPTE Video Data Input SMPTE 292M or 259M Serial Data VDD LMH0031 SD/HD Decoder/ Deserializer Parallel Ancilliary Data Input SMPTE Video Data Output Parallel Ancilliary Data Output 75: 1PF LMH0030 SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) The LMH0030 performsfunctionswhich include:parallel-to-serialdata conversion,SMPTE standarddata encoding,NRZ toNRZI dataformatconversion,serialdataclockgenerationand encodingwiththeserialdata, automaticvideorateand formatdetection,ancillarydata packetmanagement and insertion,and serialdata outputdriving.The LMH0030 has circuitryforautomaticEDH/CRC characterand flaggenerationand insertion per SMPTE RP-165 (standarddefinition)or SMPTE 292M (high definition).OptionalLSB ditheringis implementedwhichpreventspathologicalpatterngeneration.Unique totheLMH0030 areitsvideoand ancillary dataFIFOs.The videoFIFO allowsthevideodatatobe delayedfrom0 to4 paralleldataclockperiodsforvideo timingpurposes.The ancillarydataportand on-chipFIFO and controlcircuitrystoreand insertancillaryflags, datapacketsand checksums intotheancillarydataspace.The LMH0030 alsohas an exclusivebuilt-inself-test (BIST)and videotestpatterngenerator(TPG) withSD and HD component videotestpatterns:referenceblack, PLL and EQ pathologicalsand colorbarsin4:3and 16:9rasterformatsforNTSC and PAL standards*.The color barpatternsfeatureoptionalbandwidthlimitingcodinginthechroma and luma transitions. The LMH0030 has a uniquemulti-functionI/Oportforimmediateaccess to controland configurationsettings. This portmay be programmed to provideexternalaccess to controlfunctionsand indicatorsas inputsand outputs.The designercan thuscustomizetheLMH0030 tofitthedesiredapplication.Atpower-uporaftera reset command, theLMH0030 isauto-configuredtoa defaultoperatingcondition.Separatepower pinsfortheoutput driver,PLL and theserializerimprovepower supplyrejection,outputjitterand noiseperformance. The LMH0030 's internalcircuitryis powered from +2.5V and the I/O circuitryfrom a +3.3V supply.Power dissipationistypically430mW at1.485Gbps includingtwo 75Ω AC-coupledand back-matchedoutputloads.The deviceispackaged ina 64-pinTQFP. TypicalApplication

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TRS & FORMAT DETECTOR CONFIGURATION & CONTROL REGISTERS SMPTE SCRAMBLER NRZI CONVERTER SERIALIZER EDH / CRC GENERATORS PLL SYSTEM BUILT-IN SELF-TEST & TEST PATTERN GENERATOR RESET CONTROL INPUT DATA LATCH VCLK DV[9:0] RESET SDO R REF PRE SDO ANCILLIARY DATA FIFO MULTI-FUNCTION I/O PORT DV[19:10] AD[9:0] ANC /CTRL ACLK RD/WR PCLK SCLK I/O[7:0] R REF LVL INT. RESET SYSTEM MASTER CONTROLLER PCLK SCLK PCLK PCLK PCLK MASTER BUS DITHERINGPCLK VIDEO DATA FIFO VCLK PCLK LMH0030 www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 Block Diagram Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Connection Diagram Figure1. 64-PinTQFP See Package Number PAG0064A

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) Itisanticipatedthatthisdevicewillnot be offeredina militaryqualifiedversion. CMOS I/OSupplyVoltage(VDDIO –VSSIO ): 4.0V SDO SupplyVoltage(VDDSD –VSSSD ): 4.0V DigitalLogicSupplyVoltage(VDDD –VSSD ): 3.0V PLL DigitalSupplyVoltage(VDDPLL –VSSPLL ): 3.0V PLL AnalogSupplyVoltage(VDDPLLA –VSSPLLA ),(VDDZ −VSSD ): 3.0V CMOS InputVoltage(Vi): VSSIO −0.15VtoVDDIO +0.15V CMOS OutputVoltage(Vo): VSSIO −0.15VtoVDDIO +0.15V CMOS InputCurrent(singleinput): Vi= VSSIO −0.15V: −5 mA Vi= VDDIO +0.15V: +5 mA CMOS OutputSource/SinkCurrent: ±10 mA SDO OutputSinkCurrent: 40 mA Package ThermalResistance θJA @ 0 LFM Airflow 47°C/W θJA @ 500 LFM Airflow 27°C/W θJC 6.5°C/W StorageTemp. Range: −65°C to+150°C JunctionTemperature: +150°C Lead Temperature(Soldering4 Sec): +260°C ESD Rating(HBM): 2 kV ESD Rating(MM): 250V (1) “AbsoluteMaximum Ratings”arethoseparametervaluesbeyond whichthelifeand operationofthedevicecannotbe ensured.The statinghereinofthesemaximums shallnotbe construedtoimplythatthedevicecan orshouldbe operatedatorbeyond thesevalues. The tableof“ElectricalCharacteristics”specifiesacceptabledeviceoperatingconditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISemiconductorSalesOffice/Distributorsforavailabilityand specifications. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Conditions Reference Min Typ Max Units VDDIO CMOS I/OSupplyVoltage VDDIO −VSSIO 3.150 3.300 3.450 V VDDSD SDO SupplyVoltage VDDSD −VSSSD 3.150 3.300 3.450 V VDDD DigitalLogicSupplyVoltage VDDD –VSSD 2.375 2.500 2.625 V VDDPLL PLL SupplyVoltage VDDPLL –VSSPLL 2.375 2.500 2.625 V VDDZ AnalogSupplyVoltage VDDZ –VSSD 2.375 2.500 2.625 V VIL CMOS InputVoltage,Low VSSIO VLevel VIH CMOS InputVoltageHigh VDDIO VLevel TA OperatingFreeAir 0 +70 °CTemperature tJIT VideoClockJitter VCLK 30 psP-P Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1)(2). Symbol Parameter Conditions Reference Min Typ Max Units VIH InputVoltageHighLevel AllLVCMOS 2.0 VDDIO V InputsVIL InputVoltageLow Level VSSIO 0.8 V IIH InputCurrentHighLevel VIH = VDDIO +90 +150 µA IIL InputCurrentLow Level VIL= VSSIO −1 −20 µA VOH CMOS OutputVoltageHigh IOH = −6.6mA AllLVCMOS 2.4 2.7 VDDIO VLevel Outputs VOL CMOS OutputVoltageLow IOL = +6.6mA VSSIO VSSIOVSSIO VLevel +0.3 +0.5V VSDO SerialDriverOutputVoltage TestCircuit,TestLoads SDO, SDO 720 800 880 mV P-PShallApply IDD (3.3V) Power SupplyCurrent,3.3V VCLK = 27 MHz, NTSC color VDDIO ,VDDSD Supply,Total Bar Pattern,TestCircuit, 48 65 mA TestLoads ShallApply IDD (3.3V) Power SupplyCurrent,3.3V VCLK = 74.25MHz, NTSC VDDIO ,VDDSD Supply,Total colorBar Pattern,Test 66 90 mACircuit,TestLoads Shall Apply IDD (2.5V) Power SupplyCurrent,2.5V VCLK = 27 MHz, NTSC color VDDD ,VDDZ , Supply,Total Bar Pattern,TestCircuit, VDDPLL 66 85 mA TestLoads ShallApply IDD (2.5V) Power SupplyCurrent,2.5V VCLK = 74.25MHz, NTSC VDDD ,VDDZ , Supply,Total colorBar Pattern,Test VDDPLL 85 110 mACircuit,TestLoads Shall Apply (1) Currentflowintodevicepinsisdefinedas positive.Currentflowoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedto VSS = 0V. (2) TypicalvaluesarestatedforVDDIO = VDDSD = +3.3V,VDDD = VDDPLL = +2.5V and TA = +25°C. AC ELECTRICAL CHARACTERISTICS Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1). Symbol Parameter Conditions Reference Min Typ Max Units fVCLK ParallelVideoClock VCLK 27 74.25 MHzFrequency DC V VideoClockDutyCycle VCLK 45 50 55 % fACLK AncillaryClockFrequency ACLK VCLK MHz DC A AncillaryClockDuty ACLK 45 50 55 %Cycle tr,tf InputClockand Data Rise 10% –90% VCLK ,ACLK ,DV N , 1.0 1.5 3.0 nsTime,FallTime AD N BR SDO SerialData Rate (2)(3)SDO, SDO 270 1,485 M bps tr,tf RiseTime,FallTime 20% –80%,(3) SDO, SDO 270 ps tr,tf RiseTime,FallTime 20% –80%,(2) SDO, SDO 500 ps OutputOvershoot (4) SDO, SDO 5 % (1) TypicalvaluesarestatedforVDDIO = VDDSD = +3.3V,VDDD = VDDPLL = +2.5V and TA = +25°C. (2) R L = 75Ω,AC-coupled@ 270 M bps,R REF LVL = R REF PRE = 4.75kΩ 1%, See TestLoads and TestCircuit. (3) R L = 75Ω,AC-coupled@ 1,485M bps,R REF LVL = R REF PRE = 4.75kΩ 1%, See TestLoads and TestCircuit. (4) Specificationisensuredby design.

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 AC ELECTRICAL CHARACTERISTICS (continued) Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1). Symbol Parameter Conditions Reference Min Typ Max Units tj SerialOutputJitter, 270 M bps,(2)(5)(6)(7) SDO, SDO 270 350 psP-PIntrinsic tj SerialOutputJitter, 1,485M bps,(3)(5)(6)(7) SDO, SDO 85 125 psP-PIntrinsic tLOCK Lock Time See (2)(8)(9)(SD Rates) 15 ms tLOCK Lock Time See (3)(8)(9)(HD Rates) 15 ms tS SetupTime,VideoData TimingDiagram,(4) DV N toVCLK 1.5 2.0 ns tH HoldTime,VideoData TimingDiagram,(4) VCLK toDV N 1.5 2.0 ns tS SetupTime,Anc.Data TimingDiagram,(4) AD N toACLK 1.5 2.0 nsPort tH HoldTime,Anc.Data Port TimingDiagram,(4) ACLK toAD N 1.5 2.0 ns (5) Intrinsictimingjitterismeasured inaccordancewithSMPTE RP 184-1996,SMPTE RP 192-1996and theapplicableserialdata transmissionstandard,SMPTE 259M-1997 orSMPTE 292M-1998.A colorbartestpatternisused.The valueoffSCLK is270 MHz or 360 MHz forSMPTE 259M, 540MHz forSMPTE 344M, or1485 MHz forSMPTE 292M serialdatarates.See TimingJitterBandpass section. (6) IntrinsicjitterisdefinedinaccordancewithSMPTE RP 184-1996as:jitteratan equipmentoutputintheabsence ofinputjitter.As appliedtothisdevice,theinputportisVCLK and theoutputportisSDO orSDO. (7) Specificationisensuredby characterization. (8) Measured fromrising-edgeoffirstDV CLK cycleuntilLock Detectoutputgoes high(true).Lock timeincludesformatdetectiontimeplus PLL locktime. (9) Averagevaluemeasured between risingedges computed overatleastone videofield. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMH0030

10Hz >1/10 fSCLK slopes: 20dB/decade 0dB Passband ripple < ±1dB Stopband rejection >20dB 75: C L SDO SDO 75: test eqpt. (attenuation 0dB) 1.0PF VDDSD 75: C L 50: test eqpt. (attenuation 3.5dB) 1.0PF 24.9: 5.5-30pF* * risetime compensation VDDSD SDO SDO Hi-Z test eqpt. t 5k: (attenuation 0dB) C L CMOS outputs VDDIO IOL IOH C L including probe and jig capacitance, 3pF max. S1 - open, S2 - closed for VOH measurement S1 - closed, S2 - open for VOL measurement LMH0030 SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com TestLoads Timing JitterBandpass

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1.0 PF 4.7 PF 16V 4.75k 4.75k 1.0 PF 0.1 PF 75: 75: 4.7 PF 16V 0.1 PF (x3) (x3) (x4) (x4) +3.3 Vdc +2.5 Vdc

0 Vdc

+3.3V +3.3V 5 4 10, 17, 43 16, 37 DV0 DV1 DV2 DV3 DV4 DV5 DV6 DV7 DV8 DV9 VCLK SDO VDDSD VDDZ VDDIO RESET LMH0030 DV10 DV11 DV12 DV13 DV14 DV15 DV16 DV17 DV18 DV19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 ACLK 54, 55 RD/WR IO1 IO0 VSSIO VSSD VDDD ANC/CTRL VDDLS IO2 IO3 IO4 IO5 IO6 IO7 R REF PRE R REF LVL SDO VDDPLLD VSSPLLA VSSSD 2.5V Supply 3.3V Supply 2.5V Supply 3.3V Supply HD Chroma, SD Luma & Chroma HD Luma Output loads omitted for clarity. VSSLS VDDPLLA VSSPLLD LMH0030 www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 TestCircuit Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMH0030

(ACLK) DV[19:0] (AD[9:0]) 50% 90% 10% 90% 10% 90% 10% tr, tf tr, tf LMH0030 SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Timing Diagram DEVICE OPERATION The LMH0030 SDTV/HDTV Serializerisused indigitalvideosignaloriginationequipment:cameras,videotape recorders,telecinesand videotestand otherequipment.ItconvertsparallelSDTV or HDTV component digital videosignalsintoserialformat.Logiclevelswithinthisequipment are normallyproduced by LVCMOS logic devices.The encoderproducesserialdigitalvideo(SDV) signalsconformingtoSMPTE 259M, SMPTE 344M, or VIDEO DATA PATH The inputdata registeraccepts10-bitstandarddefinitionor 20-bithighdefinitionparalleldataand associated parallelclocksignalshavingLVCMOS-compatible levels.Allparallelvideodatainputs,DV[19:0],have internal pull-downdevices.VCLK does nothave an internalpull-downdevice.Parallelvideodatamay conformtoany of severalSMPTE standards:125M, 267M, 260M, 274M, 295M or296M. Some segmented frameformatsarenot supported.For HDTV data,theupper10 bitsoftheDV inputareluminance(luma)informationand thelower10 bitsare colordifference(chrominanceor chroma) information.For SDTV data,thelowerorder10 bitscontain bothluma and chroma information.OutputfromthisregisterfeedsthevideoFIFO,videoformatdetectioncircuit, TRS characterdetector,SMPTE scrambler,EDH/CRC generators,serializer/NRZIconverterand the device controlsystem. Data from the inputdata registerpasses intoa 4-registerdeep video FIFO priorto encoding and other processing.The depthofthisFIFO issetby theVIDEO FIFO Depth[2:0]bitsoftheANC 0 controlregister. The video formatdetectorautomaticallydeterminestherastercharacteristics(videodataformat)oftheparallel inputdataand configurestheLMH0030 toproperlyhandlethedata.Thisassuresthatthedatawillbe properly formatted,thatthecorrectdatarateisselectedand thatancillarydata,linenumbers (HD) and CRC/EDH data are correctlyinserted.Indicationof the standardbeing processedisstoredin the FORMAT[4:0] bitsin the FORMAT 1 controldataregister.Thisformatdatacan be programmed foroutputon themulti-functionI/Oport. The LMH0030 normallyoperatesinan auto-format-detectionmode. Itmay optionallybe configuredtoprocess onlya singlevideoformatby writingtheappropriateFORMAT SET[4:0]controldataintotheFORMAT 0 control register.The defaultstateofFORMAT SET[4:0]is0000b.Also,theLMH0030 may be configuredtohandleonly thestandard-definitiondataformatsby settingtheSD ONLY bitoronlythehigh-definitiondataformatsby setting the HD ONLY bitintheFORMAT 0 controlregister.When both of thesebitsare resetthe partautomatically selectsthedatarate. The TRS characterdetectorprocessesthe timingreferencesignalswhich controlrasterframing.The TRS detectorsuppliescontrolsignalsto the system controllerto identifythe presenceof the validvideodata.The system controllersuppliesnecessarycontrolsignalstotheEDH/CRC controlblock.TRS characterLSB-clipping as prescribedinITU-R BT.601 isused.LSB-clippingcauses allTRS characterswitha valuebetween 000h and 003h tobe forcedto000h and allTRS characterswitha valuebetween 3FCh and 3FFh tobe forcedto3FFh. Clippingisdone priortoscramblingand EDH/CRC charactergeneration. The LMH0030 incorporatescircuitryforLSB dithering. The DitherEnable bitinthe VIDEO INFO 0 register when setenablesdithering.The V DitherEnable bitintheVIDEO INFO 0 controlregisterwhen setenables ditheringduringtheverticalblankinginterval.The initialconditionofDitherEnable and V DitherEnable isOFF.

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 The SMPTE scrambler accepts10-bitstandarddefinitionor 20-bithigh definitionparallelvideo data and encodes itusingthe polynomialX9 + X4 + 1 as specifiedinthe respectivestandard:SMPTE 259M, SMPTE 344M, orSMPTE 292M. The dataisthenserializedand senttotheNRZ-to-NRZI converterbeforebeingoutput. The transmissionbitorderisLSB-first. The NRZ-to-NRZI converteracceptsNRZ serialdatafromtheSMPTE scrambler.The dataisconvertedtoNRZI formatusingthepolynomial(X + 1).The converter'soutputgoes totheoutputcabledriveramplifier. ANCILLARY/CONTROL DATA PATH The 10-bit,bi-directionalAncillaryand ControlData Portperformstwo distinctfunctionsintheLMH0030. First, itisused toselectivelyloadancillarydataintotheAncillaryData FIFO forinsertionintothevideodatastream. The utilizationand flowofancillarydatawithinthedeviceismanaged by a system ofcontrolbits,masks and IDs inthecontroldataregisters.Second, thisportprovidesread/writeaccess tocontentsoftheconfigurationand controlregisters. Ancillaryand controldataare inputviathe10-bitAncillary/ControlData Port,AD[9:0].The stateoftheRD/WR controlinputdetermineswhetherdataisreadorwrittentotheregistersorwrittentotheAncillaryData FIFO.The stateoftheANC/ CTRL controlinputselectswhichoftheancillarydataorcontroldatasub-systemsisaccessed throughtheport. The ACLK inputcontrolsdataflowthroughtheport.The operationand frequencyofACLK isindependentofthe videodataclock,VCLK .However,thefrequencyofACLK must be lessthanorequaltoVCLK .There isno low frequencylimitforACLK when itisbeingused forcontrolregisteraccess.When theANC/ CTRL inputisa logic- high,ACLK affectsonlythe ancillarydata FIFO operation.When the ANC/ CTRL inputisa logic-low,ACLK affectsonlythecontrolregisteroperation. InputsAD[9:0],RD/WR and ANC/ CTRL have internalpulldown devices.ACLK does nothave an internalpull down device. CONTROL DATA READ FUNCTIONS Control data is writtento and read from the LMH0030 using the lower-order8 bitsAD[7:0] of the Ancillary/ControlData Port.Thiscontroldata initializes,monitorsand controlsoperationof the LMH0030. The uppertwo bitsAD[9:8]oftheportarehandshakingsignalswiththedeviceaccessingtheport.AD[9:8]must be drivenas 00b (0XXh,where XX areAD[7:0])when eithera controlregisterreadorwriteaddressisbeingwritten totheport.AD[9:8]must be drivenas 11b (3XXh,where XX areAD[7:0])when controldataisbeingwrittento theport.When controldataisbeingreadfromtheport,theLMH0030 willoutputAD[9:8]as 10b (2XXh,where XX areoutputdataAD[7:0])and may be ignoredby themonitoringsystem. NOTE When power isfirstappliedto the deviceor afteritisreset,theAncillaryand Control Data Port must be initializedto receivedata.Thisisdone by togglingACLK three(3) times. Figure2 shows thesequence ofclockand controlsignalsforreadingcontroldatafromtheancillary/controldata port.The ControlData Read mode isenteredby making theANC/ CTRL inputlow and theRD/WR inputhigh. Next,the8-bitaddressofthecontrolregistersettobe accessedisplacedon portbitsAD[7:0].When a control registerreadaddressisbeingwrittentotheport,AD[9:8]must be drivenas 00b (0XXh,where XX areAD[7:0]). ACLK isthentoggled.The addressiscapturedon therisingedge ofACLK .Observe theportinputholdtiming specification. Data from theselectedregisterisdrivenby theportwithina few nanoseconds immediatelyfollowingtherising edge of ACLK . To avoid contentionwith the port,the address drivershould be turnedoffor tri-stated immediatelyaftertheaddressisclockedintothedevice.Data may be readby externaldevicesatany timeafter theremovaloftheaddresssignal.Outputdatawillbe drivenuntilthenextrisingedge ofACLK .When thehost system finishesreadingthe data,toggleACLK again.Thissecond clockresetsthe portfrom driveto receive mode and readiestheportforanotheraccesscycle.When controldataisbeingreadfromtheport,theLMH0030 willoutputAD[9:8]as 10b (2XXh, where XX are outputdata AD[7:0])and may be ignoredby the monitoring system. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMH0030

ADDR DATA DATA ADDR ADDR DATAAD[7:0] WRITE EXTERNAL BUS MUST RELEASE INTERNAL BUS WILL RELEASE ACLK READ READ AD[9:8] AD[9] AD[8] DRIVEN REC'D DRIVEN REC'D DRIVEN DRIVEN AD[9] AD[8] AD[8] AD[9] AD[8] AD[9:8] LMH0030 SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Example: Read theFull-fieldFlagsviatheAD port. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-high. 3. Present001h toAD[9:0]as theregisteraddress. 4. ToggleACLK . 5. Releasethebus drivingtheAD port. 6. Read thedatapresenton theAD port.The Full-fieldFlagsarebitsAD[4:0]. 7. ToggleACLK toreleasetheAD port. Figure2. ControlData Read Timing (2read and 1 writecycleshown) CONTROL DATA WRITE FUNCTIONS Figure3 shows thesequence ofclockand controlsignalsforwritingcontroldatatotheancillary/controldataport. The controldata writemode issimilartothereadmode. The controldatawritemode isstartedby making both the ANC/ CTRL inputlow and the RD/WR inputlow.Next,the 8-bitaddressof the controlregistersetto be accessed isplacedon portbitsAD[7:0]. When a controlregisterwriteaddress isbeing writtento the port, AD[9:8]must be drivenas 00b (0XXh,where XX are AD[7:0]).ToggleACLK .The addressiscapturedon the risingedge ofACLK .Remove theaddressafterclockingitintothedeviceon orbeforethefallingedge ofACLK . Observe theportinputholdtimingspecification. Next,thecontrolregisterdataisplacedon theAD[7:0]port.ACLK isagaintoggled.The dataiswrittentothe selectedregisteron therisingedge ofACLK .When controldataisbeingwrittentotheport,AD[9:8]must be drivenas 11b (3XXh, where XX are AD[7:0]).Remove the registerdata afterclockingitintothe deviceon or beforethefallingedge ofACLK .Observe theportinputholdtimingspecification. Example: Setup (withoutenabling)the TPG Mode viathe AD portusingthe 1125 line,30 frame,74.25MHz, interlacedcomponent (SMPTE 274M) colorbarsas testpattern.The TPG may be enabledaftersetupusingthe Multi-functionI/Oportorby thecontrolregisters. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-low. 3. Present00Dh toAD[9:0]as theTest0 registeraddress. 4. ToggleACLK . 5. Present327h toAD[9:0]as theregisterdata. 6. ToggleACLK .

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ADDR DATA DATA ADDR ADDR DATAAD[7:0] AD[9:8] AD[9] AD[8] DRIVEN AD[9] AD[8] AD[9:8] DRIVEN WRITE WRITE WRITE LMH0030 www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 Figure3. ControlData WriteTiming ANCILLARY DATA FUNCTIONS The LMH0030 can multiplexAncillaryData intothe serialcomponent videodata stream.The ancillarydata packetstructure,formattingand controlwords are givenin standardSMPTE 291M. The data may residein portionsof the horizontaland verticalblankingintervals.The data can consistof differenttypesof message packetsincludingaudiodata.The LMH0030 supportsancillarydataintheHANC and VANC areasofstandard definitioncomponent videoand in the chrominancechannel(C’r/C’b) onlyforhigh-definitionoperation.As it appliesto embedded (multiplexed)audio data,thisfunctionfollowsthe recommended practiceforAES/EBU defaultLevelA datahandling. Figure4 shows thesequence ofclock,dataand controlsignalsforwritingAncillaryData totheport.Inancillary data writemode, 10-bitancillarydata iswrittenintothe AD[9:0]portand subsequentlyintothe ancillarydata FIFO. From the FIFO, the ancillarydata can be insertedintothe ancillarydata areas inthe serialvideodata stream.Ancillarydatamay be writtentotheFIFO onlywhen intheancillarydatamode. Ancillarydatacannotbe readfromtheFIFO throughtheAD Port. The processof loadingancillarydata intothe FIFO isdone duringthe activevideoportionof the videoline. Occurrenceoftheactivevideolineintervalisindicatedby theH-bitinthefourthword oftheTRS sequence.The H-bitisavailableon I/OPortbit-2. The ancillarydatawriteprocessbeginsby making theANC/ CTRL inputhighand theRD/WR inputlow.Next,the datawords are presentedtotheportinsequence as specifiedinSMPTE 291M beginningwiththeDID word. Data presentedtotheportwithintherequiredsetupand holdtimeparameterswillbe writtenintotheFIFO on the risingedge ofACLK .The userhas theoptionofincludinga checksum intheANC inputdataor ofhavingthe LMH0030 calculateand append thechecksum.The LMH0030 willappend theAncillaryData Flagtoeach packet automaticallybeforemultiplexingwiththevideodata. The processofwritingancillarydatatotheFIFO iseffectivelya double-bufferedwriteoperation.Therefore,in ordertoproperlywritethelastword ofthedatapacket,theCRC, whethersuppliedwiththeANC datapacketor internallygenerated,totheFIFO,ACLK must be toggledtwo additionaltimesafterthelastdataword isclocked intotheport(orwhen theCRC isbeinggeneratedinternallyand appended).Inthecase where multiplepackets arebeingloadedtotheFIFO,theadditionalclocksareissuedafterthelastword ofthefinalpacketisreceived by theport. WritingofancillarydatatotheFIFO,packethandlingand insertionintothevideodatastreamarecontrolledby a system ofmasking and controlbitsinthecontrolregisters.These and otherancillarydatacontrolfunctionssuch as CHKSUM ATTACH IN areexplainedindetaillaterinthisdatasheet. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMH0030

AD[9:0] WRITE DATA DATA DATADATADATA DATA DATA LMH0030 SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Figure4. AncillaryData WriteTiming MULTI-FUNCTION I/OPORT The Multi-functionI/O port can be configuredto provideimmediateaccess to many controland indicator functionswithintheLMH0030 configurationand controlregisters.The individualpinscomprisingthisportmay be assignedas inputoroutputforselectedbitsinthecontroldataregisters.The multi-functionI/Oportisconfigured by way ofan 8x6-bitregisterbank,I/Opin 0 CONFIG throughI/Opin 7 CONFIG .The pinconfigurationregisters containcodes which assigna controlregisterbitto a particularI/O pin.Controlsand indicatorsthatare accessibleby the portand theircorrespondingselectionaddresses are given in the I/O Pin Configuration RegisterAddresses,Table6.Table2 givesthecontrolregisterbitassignments. CAUTION When writingdataintothecontrolregistersviathemulti-functionI/Oport,ACLK must be toggledto registerthe data as shown inFigure5. Itisnot necessaryto toggle ACLK when readingdatafromthemulti-functionI/Oport. Example: Program multi-functionI/Oportbit-0as theSAV bitoutput. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-low. 3. Present00Fh toAD[9:0]as theI/OPIN 0 CONFIG registeraddress(seeTable3). 4. ToggleACLK . 5. Present30Dh toAD[9:0]as theregisterdata(seeTable6). 6. ToggleACLK . Figure5. I/OPortData WriteTiming

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 EDH/CRC SYSTEM The LMH0030 has EDH and CRC charactergenerationand insertioncircuitry.The EDH system functionsas describedinSMPTE Recommended PracticeRP-165.The CRC system functionsas specifiedinSMPTE 292M. The EDH/CRC polynomialgeneratorsacceptparalleldatafrom theinputregisterand generatetheEDH and CRC check words forinsertionintheserialdata.Incomingparalleldataischecked forerrorsand theEDH flags areupdatedautomatically.EDH check words and statusflagsforSDTV dataaregeneratedusingthepolynomial X16 + X12 + X6 + 1 per SMPTE RP165. EDH check words are insertedintheserialdatastreamatthecorrect positionsintheancillarydataspace and formattedperSMPTE 291M. Generationand automaticinsertionofthe EDH check words iscontrolledby EDH Force and EDH Enable bitsinthecontrolregisters.Aftera reset,the initialstateofallEDH and CRC checkcharactersis00h. The SMPTE 292M highdefinitionvideostandardemploys CRC (cyclicredundancycheck codes)errorchecking insteadofEDH. The CRC consistsoftwo 18-bitwords generatedusingthepolynomialX18 + X5 + X4 + 1 per SMPTE 292M. One CRC isused forluminanceand one forchrominancedata.CRC data isinsertedat the requiredplaceinthevideodataaccordingtoSMPTE 292M. The CRCs appearinthedatastreamfollowingthe EAV and linenumber characters. EDH and CRC errorsarereportedintheEDH0, EDH1, and EDH2 registersetsoftheconfigurationand control registers. PHASE-LOCKED LOOP SYSTEM The phase-lockedloop (PLL)system generatestheoutputserialdataclockat10x (standarddefinition)or20x (highdefinition)the paralleldata clockfrequency.Thissystem consistsof a VCO, dividers,phase-frequency detectorand internalloopfilter.The VCO free-runningfrequencyisinternallyset.The paralleldataclockVCLK is thereferenceforthePLL. The PLL automaticallygeneratestheappropriatefrequencyfortheserialclockrate. Loop filteringisinternaltotheLMH0030. The VCO has separateanalogand digitalpower supplyfeeds:VDDPLLA pin62,VSSPLLA pin61,VDDPLLD pin1,and VSSPLLD pin2.These may be separatelysuppliedpower viaexternal low-passfilters,ifdesired.PLL acquisitiontimeislessthan200µs @ 1485 Mbps. The VCO haltswhen theVCLK signalisnotpresentorisinactive. A LOCK DETECT indicatorfunctionisavailableas a bitintheVIDEO INFO 0 controlregisters.LOCK DETECT isa logic-1when thePLL islockedand a validformathas been detected.Itcan be assignedas an outputon the multifunctionI/Oport.By defaultLOCK DETECT isassignedas I/OPortbit4 afterpower-on or reset. This functionalsoincludeslogictocheck thestabilityofthedeviceafterthedigitallogicresetisreleasedfollowing PLL lock.Ifthe system isnot fullystable,the logicisautomaticallyreset.LOCK DETECT alsocombines the functionofindicatingthattheLMH0030 has detectedthevideoformatbeingreceived.Thisformatdetectfunction involvesdeterminationofthemajorrasterparameterssuch as linelength,number ofvideolinesina frame,and so forth.Thisisdone so thatinformationlikelinenumberingcan be correctlyinserted.The PLL itselfwillhave lockedin 200 microseconds(HD rates)or less.However, resolutionof allrasterparametersmay take the majorityofa frame. SERIAL DATA OUTPUT DRIVER The serialdata outputs providelow-skewcomplimentaryor differentialsignals.The outputbufferisa current- mode designand isintendedtodriveAC-coupledand terminated,75Ω coaxialcables.The driverautomatically adjustsitsoutputslew ratedependingupon thedataratebeingprocessed.Outputlevelsare 800 mV P-P ±10% into75Ω AC-coupledloads.The 75Ω resistorsconnectedto the SDO outputsfunctionboth as drain-loadand back-matchingresistors.Seriesback-matchingresistorsarenotused withthisoutputtype. The serialoutputleveliscontrolledby the valueof R REF LVL and R REF PRE connectedto pin53 and pin52, respectively.The R REF LVL resistorsetsthe peak-to-peaklevelof the outputsignalto the requiredSMPTE nominal level.The R REF PRE resistorsets the value of a pre-emphasiscurrentwhich is activeduringthe transitiontimesof the HD-rateoutputsignal.The valueof R REF LVL isnormally4.75 KΩ, ±1%. The valueof R REF PRE isnormally4.75KΩ,±1%. The voltagepresentatthesepinsisapproximately+1.3Vdc.The transition timesofthisoutputbufferdesignautomaticallyadjustand aredifferentfortheHD and SD datarateconditions. The outputbufferisquiescentwhen thedeviceisinan out-of-lockcondition.The outputwillbecome activeafter thePLL islockedand a validformathas been detected.Separatepower feedsareprovidedfortheserialoutput driver:VSSSD ,pins54,55,and 59;VDDSD ,pin51;and VDDLS ,pin57. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com CAUTION This outputbufferisnot designedor specifiedfordriving50Ω or otherimpedance loads. NOTE The SMPTE returnlossspecificationishighlydependent on board designand can be challengingto meet withthe LMH0030's integratedcabledriver.In orderto meet the SMPTE returnlossspecification,itisrecommended touse an externalcabledriversuch as theLMH0002 HD/SD SDI cabledriveron theoutputoftheLMH0030. POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT The LMH0030 requirestwo power supplies,2.5V forthecorelogicfunctionsand 3.3V fortheI/Ofunctions.The suppliesmust be appliedto the devicein propersequence. The 3.3V supplymust be appliedpriorto or recommended thatthe3.3V supplybe configuredordesignedso as tocontrolapplicationofthe2.5V supplyin ordertosatisfythissequencingrequirement. The LMH0030 has an automatic,power-on-resetcircuit.Reset initializesthedeviceand clearsTRS detection circuitry,alllatches,registers,countersand polynomialgenerators,setsthe EDH/CRC charactersto 00h and disablestheserialoutput.Table1 liststheinitialconditionsoftheconfigurationand controlregisters.An active- HIGH-true,manual resetinputisavailableatpin64.The resetinputhas an internalpull-downdeviceand may be consideredinactivewhen unconnected. Important:When power isfirstappliedtothedeviceorfollowinga reset,theAncillaryand ControlData Port must be initializedtoreceivedata.Thisisdone by togglingACLK threetimes. TEST PATTERN GENERATOR (TPG) AND BUILT-INSELF-TEST (BIST) The LMH0030 includesa built-intestpatterngenerator(TPG).Four testpatterntypesareavailableforalldata rates,allHD and SD formats,NTSC and PAL standards,and 4x3 and 16x9 rastersizes.The testpatternsare: flat-fieldblack,PLL pathological,equalizer(EQ) pathologicaland a 75%, 8-colorverticalbar pattern.The pathologicalsfollowtherecommendationsofSMPTE RP 178-1996 regardingthetestdataused.The colorbar patternhas optionalbandwidthlimitingcodinginthechroma and luma datatransitionsbetween bars.The VPG FILTER ENABLE bitin the VIDEO INFO 0 controlregisterenablesthe colorbar filterfunction.The default conditionofVPG FILTER ENABLE isOFF. The TPG alsofunctionsas a built-inself-test(BIST)which can verifydevicefunctionality.The BIST function performsa comprehensivego/no-gotestofthedevice.The testmay be run usingany oftheHD colorbar test patternsorone oftwo SD testpatterns,eithera 270 Mbps NTSC full-fieldcolorbarora PAL PLL pathological, as thetestdatapattern.Data issuppliedinternallyintheinputdataregister,processedthroughthedeviceand testedforerrorsusingeithertheEDH system forSD ortheCRC system forHD. A go/no-goindicationislogged inthePass/FailbitoftheTEST 0 controlregisterset.Thisbitmay be assignedas an outputon themultifunction I/Oport. TPG and BIST operationisinitiatedby loadingthecode forthedesiredtestpatternintotheTest PatternSelect [5:0]bitsof the TEST 0 register.Table 5 gives the availabletestpatternsand codes. (Recallalso the requirementtoinitializetheancillarydataportcontrollogicby clockingACLK atleastthree(3)completecycles beforeattemptingtoloadthefirstregisteraddress).Inthedefaultpower-onstate,TPG Enable appearsas bit7 on themulti-functionI/Oport.The TPG isrun by applyingtheappropriatefrequencyattheVCLK inputforthe formatand rateselectedand thensettingtheTPG Enable inputon themulti-functionI/Oport,orby settingthe TPG Enable bitintheTEST 0 register. Important:IftheTPG Enable inputoftheI/Oportisinitsdefaultmapping and isnotbeingused toenablethe TPG mode, attemptingtoenableTPG operationby settingbit6 oftheTEST 0 registerwillnotcause theTPG to operate.Thisisbecause thelow logiclevelattheI/Oportinputpulldownoverridesthehighlevelbeingwrittento theregister.The resultistheTPG does notrun.

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 The Pass/FailbitintheTEST 0 controlregisterindicatestheteststatus.Ifno errorshave been detected,thisbit willbe settologic-1approximately2 fieldintervalsafterTPG Enable isset.Iferrorshave been detectedinthe internalcircuitryoftheLMH0030, Pass/Failwillremainresettoa logic-0.The TPG orBIST ishaltedby resetting TPG Enable.The serialoutputdataispresentattheSDO outputsduringTPG orBIST operation. CAUTION When attemptingtouse theTPG orBIST immediatelyafterapplyingpower orresetting the device,the TPG defaultsto the 270 Mbps SD rateand expectsa VCLK clock frequencyof27MHz as input.Thisisbecause thecode forthetestpatternintheTEST 0 registeris set to 00h (525 line,30 frame,27MHz, NTSC 4x3 referenceblack). Attemptingtoapplya VCLK frequencyhigherthanthedeviceexpects,accordingtothe settinginthe TEST 0 register,may resultinthe PLL lockingup whileattemptingto slewtoitsmaximum possiblefrequency.Thissituationisnotrecoverableby theuse of thedeviceRESET input.To recoverfromthiscondition,power must be removed and re-appliedtothedevice.ProperconditioningoftheVCLK input,whichdoes nothave an internalpulldown device,ismandatory to preventadmissionof noiseor unwanted signalsat any time,especiallyduringpower-up or resetsequences.Itis strongly recommended thatVCLK not be applieduntildeviceinitializationand configurationis completed. Example: Enable theTPG Mode touse theNTSC 270 Mbps colorbarsas theBIST and TPG pattern.Enable TPG operationusingtheI/Oport. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-low. 3. Present00Dh toAD[9:0]as theTEST 0 registeraddress. 4. ToggleACLK . 5. Present303h toAD[9:0]as theregisterdata(525 line,30 frame,27MHz, NTSC 4x3,colorbars(SMPTE 125M)). 6. ToggleACLK . 7. SetTPG ENABLE (I/OPort,bit7)toa logic-high. 8. ToggleACLK . 9. The PASS/ FAIL indicator(I/OPort,bit6) ismonitoredforthe resultof the test.Alternatively,the TEST 0 registermay be read.Bit7 isthePass/Failindicatorbit. CONFIGURATION AND CONTROL REGISTERS The configurationand controlregistersstoredata which configuresthe operationalmodes of the LMH0030 or which resultfrom itsoperation.Many of theseregisterscan be mapped to the multi-functionI/Obus to make them availableas externalI/O functions.These functionsand initialvaluesare summarized in Table 1 and detailedinTable 2. The power-on defaultconditionforthe multi-functionI/OportisindicatedinTable 1 and detailedinTable6. Table1.Configurationand ControlData RegisterSummary AssignabletoRegisterFunction Bits Read or Write InitialCondition(1) NotesI/OBus as EDH Error(SD) 1 R Output See (1) Full-FieldFlags 5 R Reset No ActivePictureFlags 5 R Reset No ANC Flags 5 R Reset No EDH Force 1 R/W OFF Input EDH Enable 1 R/W ON Input F/FFlagError 1 R Reset Output (1) ON = logic-1,OFF = logic-0(positivelogic). Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Table1.Configurationand ControlData RegisterSummary (continued) AssignabletoRegisterFunction Bits Read or Write InitialCondition(1) NotesI/OBus as A/P FlagError 1 R Reset Output ANC FlagError 1 R Reset Output ANC Checksum 1 R/W OFF Input Force ANC Checksum Error 1 R Reset Output FIFO Empty 1 R Set Output FIFO Full 1 R Reset Output FIFO Overrun 1 R Reset Output VideoFIFO Depth 3 R/W 000b No ANC ID 16 R/W 0000h No ANC Mask 16 R/W FFFFh No FIFO FlushStatic 1 R/W OFF No Chksum AttachIn 1 R/W OFF Input FIFO InsertEnable 1 R/W OFF Input ANC ParityMask 1 R/W OFF No Disable VANC 1 R/W OFF No SwitchPoint0 8 R/W 00h No SwitchPoint1 8 R/W 00h No SwitchPoint2 8 R/W 00h No SwitchPoint3 8 R/W 00h No FormatSet 5 R/W OFF No SD Only 1 R/W OFF No HD Only 1 R/W OFF No Format 5 R Output Format4 H 1 R Output See (2) V 1 R Output See (2) F 1 R Output See (2) TestPatternSelect 6 R/W 00000b Input 525/27MHz/Black TPG Enable 1 R/W OFF Input See (2) Pass/Fail 1 R Output See (2) New Sync Position 1 R Output (NSP) SAV 1 R Output EAV 1 R Output Lock Detect 1 R Output See (2) VPG FilterEnable 1 R/W OFF Input Dither_Enable 1 R/W OFF Input Vert.DitherEnable 1 R/W OFF No Scrambler_Enable 1 R/W ON No NRZI_Enable 1 R/W ON No LSB_Clipping 1 R/W ON No SYNC_Detect_Enabl 1 R/W ON No e I/OBus PinConfig. 48 R/W See Table6 No (2) ConnectedtomultifunctionI/Oportatpower-on.

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 Table2.ControlRegisterBitAssignments Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EDH 0 (registeraddress 01h) EDH ERROR EDH FORCE EDH ENABLE F/FFLAGS(4) F/FFLAGS(3) F/FFLAGS(2) F/FFLAGS(1) F/FFLAGS(0)(SD) EDH 1 (registeraddress 02h) reserved reserved reserved A/P FLAGS(4) A/P FLAGS(3) A/P FLAGS(2) A/P FLAGS(1) A/P FLAGS(0) EDH 2 (registeraddress 03h) F/FFLAG A/P FLAG ANC FLAG ANC ANC ANCANC FLAGS(3) ANC FLAGS(1)ERROR ERROR ERROR FLAGS(4) FLAGS(2) FLAGS(0) ANC 0 (registeraddress 04h) VIDEO FIFO VIDEO FIFO VIDEO FIFO FIFO FIFO FIFO ANC CHECK- ANC CHECK- DEPTH(2) DEPTH(1) DEPTH(0) OVERRUN EMPTY FULL SUM ERROR SUM FORCE ANC 1 (registeraddress 05h)DID ANC ID(7) ANC ID(6) ANC ID(5) ANC ID(4) ANC ID(3) ANC ID(2) ANC ID(1) ANC ID(0) ANC 2 (registeraddress 06h)SDID/DBN ANC ID(15) ANC ID(14) ANC ID(13) ANC ID(12) ANC ID(11) ANC ID(10) ANC ID(9) ANC ID(8) ANC 3 (registeraddress 07h)DID ANC MASK(7) ANC MASK(6) ANC MASK(5) ANC MASK(4) ANC MASK(3) ANC MASK(2) ANC MASK(1) ANC MASK(0) ANC 4 (registeraddress 08h)SDID/DBN ANC ANC ANCANC MASK(15) ANC MASK(13) ANC MASK(11) ANC MASK(9) ANC MASK(8)MASK(14) MASK(12) MASK(10) ANC 5 (registeraddress 17h) FIFO INSERT CHSUM FIFO FLUSHreserved reserved reserved reserved reservedENABLE ATTACH IN STATIC ANC 6 (registeraddress 18h) ANC PARITYreserved reserved reserved reserved reserved reserved VANCMASK SWITCH POINT 0 (registeraddress 09h) LINE(7) LINE(6) LINE(5) LINE(4) LINE(3) LINE(2) LINE(1) LINE(0) SWITCH POINT 1 (registeraddress 0Ah) PROTECT(4) PROTECT(3) PROTECT(2) PROTECT(1) PROTECT(0) LINE(10) LINE(9) LINE(8) SWITCH POINT 2 (registeraddress 19h) LINE(7) LINE(6) LINE(5) LINE(4) LINE(3) LINE(2) LINE(1) LINE(0) SWITCH POINT 3 (registeraddress 1Ah) PROTECT(4) PROTECT(3) PROTECT(2) PROTECT(1) PROTECT(0) LINE(10) LINE(9) LINE(8) FORMAT 0 (registeraddress 0Bh) FORMAT FORMAT FORMAT FORMAT FORMATreserved SD ONLY HD ONLY SET(4) SET(3) SET(2) SET(1) SET(0) FORMAT 1 (registeraddress 0Ch) F V H FORMAT(4) FORMAT(3) FORMAT(2) FORMAT(1) FORMAT(0) TEST 0 (registeraddress 0Dh) TEST TEST TEST TEST TEST TEST PASS/FAIL TPG ENABLE PATTERN PATTERN PATTERN PATTERN PATTERN PATTERN SELECT(5) SELECT(4) SELECT(3) SELECT(2) SELECT(1) SELECT(0) VIDEO INFO 0 (registeraddress 0Eh) VERT.DITHER VPG FILTER LOCKDITHER EAV SAV NSP reservedENABLE ENABLE DETECTENABLE MULTI-FUNCTION I/OBUS PIN CONFIGURATION I/OPIN 0 CONFIG (registeraddress 0Fh) reserved reserved PIN 0 SEL[5] PIN 0 SEL[4] PIN 0 SEL[3] PIN 0 SEL[2] PIN 0 SEL[1] PIN 0 SEL[0] I/OPIN 1 CONFIG (registeraddress 10h) Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Table2.ControlRegisterBitAssignments (continued) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 reserved reserved PIN 1 SEL[5] PIN 1 SEL[4] PIN 1 SEL[3] PIN 1 SEL[2] PIN 1 SEL[1] PIN 1 SEL[0] I/OPIN 2 CONFIG (registeraddress 11h) reserved reserved PIN 2 SEL[5] PIN 2 SEL[4] PIN 2 SEL[3] PIN 2 SEL[2] PIN 2 SEL[1] PIN 2 SEL[0] I/OPIN 3 CONFIG (registeraddress 12h) reserved reserved PIN 3 SEL[5] PIN 3 SEL[4] PIN 3 SEL[3] PIN 3 SEL[2] PIN 3 SEL[1] PIN 3 SEL[0] I/OPIN 4 CONFIG (registeraddress 13h) reserved reserved PIN 4 SEL[5] PIN 4 SEL[4] PIN 4 SEL[3] PIN 4 SEL[2] PIN 4 SEL[1] PIN 4 SEL[0] I/PPIN 5 CONFIG (registeraddress 14h) reserved reserved PIN 5 SEL[5] PIN 5 SEL[4] PIN 5 SEL[3] PIN 5 SEL[2] PIN 5 SEL[1] PIN 5 SEL[0] I/OPIN 6 CONFIG (registeraddress 15h) reserved reserved PIN 6 SEL[5] PIN 6 SEL[4] PIN 6 SEL[3] PIN 6 SEL[2] PIN 6 SEL[1] PIN 6 SEL[0] I/OPIN 7 CONFIG (registeraddress 16h) reserved reserved PIN 7 SEL[5] PIN 7 SEL[4] PIN 7 SEL[3] PIN 7 SEL[2] PIN 7 SEL[1] PIN 7 SEL[0] TEST MODE 0 (registeraddress 55h) SYNC DETECT LSB SCRAMBLERreserved reserved reserved NRZI ENABLE reservedENABLE CLIPPING ENABLE Table3.ControlRegisterAddresses Address AddressRegisterName Decimal Hexadecimal EDH 0 1 01 EDH 1 2 02 EDH 2 3 03 ANC 0 4 04 ANC 1 5 05 ANC 2 6 06 ANC 3 7 07 ANC 4 8 08 ANC 5 23 17 ANC 6 24 18 SWITCH POINT 0 9 09 SWITCH POINT 1 10 0A SWITCH POINT 2 25 19 SWITCH POINT 3 26 1A FORMAT 0 11 0B FORMAT 1 12 0C TEST 0 13 0D VIDEO INFO 0 14 0E I/OPIN 0 CONFIG 15 0F I/OPIN 1 CONFIG 16 10 I/OPIN 2 CONFIG 17 11 I/OPIN 3 CONFIG 18 12 I/OPIN 4 CONFIG 19 13 I/OPIN 5 CONFIG 20 14 I/OPIN 6 CONFIG 21 15 I/OPIN 7 CONFIG 22 16 TEST MODE 0 85 55

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 EDH REGISTERS 0,1 AND 2 (Addresses 01h through 03h) Updated EDH packetsmay be insertedintotheserialoutputdataby settingtheEDH Force bitinthecontrol registers.The EDH Force controlbitcauses the insertionof new EDH checkwords and flagsintothe serial outputregardlessofthepreviousconditionofEDH checkwordsand flagsintheinputparalleldata.Thisfunction may be used insituationswhere videocontenthas been edittedthusmaking the previousEDH information invalid.Inthecase ofSMPTE 292M data,theCRC check charactersarerecalculatedand insertedautomatically regardlessofthepresenceofCRC charactersintheparalleldata.AftertheLMH0030 isreset,theinitialstateof theCRC checkcharactersis00h. The EDH Enable bitenablesoperationoftheEDH generatorfunction. The EDH ERROR (SD)bitwhen setindicatesthatEDH errorconditionsarebeingreportedinEDH ancillarydata packetspresentintheparallelinputdata.DetailsofthespecificerrorconditionscontainedintheEDH packets arereportedviathefullfield,activepictureand ancillaryflagerrorbitsand thespecificflagbitsintheseregisters. The EDH flagsF/F FLAGS[4:0] (fullfield),A/P FLAGS[4:0] (activepicture)and ANC FLAGS[4:0] (ancillary data)are definedinSMPTE RP 165.The EDH flagsare storedinthecontrolregisters.The flagsare updated automaticallywhen theEDH functionisenabledand dataisbeingreceived. The statusof EDH flagerrorsinincomingSD paralleldata are reportedinthe ffFlagError,apFlagErrorand ancFlagErrorbits.The ffFlagError,apFlagErrorand ancFlagErrorbitsarethelogical-ORofthecorresponding EDH and EDA flagsoftheEDH checkwords. ANC REGISTER 0 (Address 04h) The V FIFO Depth[2:0]bitscontrolthedepthofthevideoFIFO whichfollowstheinputdatalatches.The depth can be setfrom0 to4 stagesdeep by writingthecorrespondingbinarycode intothesebits.For example:toset theVideoFIFO depthattwo registers,load11010XXXXXb intotheANC 0 controlregister(whereX represents theotherfunctionalbitsofthisregister).To retainotherdatapreviouslystoredina register,read theregister’s contentsand logically-ORthiswiththenew data.Then writethecompositedataback intotheregister. FlagsforFIFO EMPTY ,FIFO FULL and FIFO OVERRUN areavailableintheconfigurationand controlregister set.These flagscan alsobe assignedas inputsand outputson themulti-functionI/Oport.The FIFO OVERRUN flagindicatesthatan attempttowritedataintoa fullFIFO has occurred. The ANC Checksum Force bit,under certainconditions,enablesthe overwritingof ancillarydata checksums receivedintheparallelancillarydata.Calculationand insertionofnew ancillarydatachecksums iscontrolledby the ANC Checksum Force bit.Ifa checksum errorisdetected(calculatedand receivedchecksums do not match)and theANC Checksum Force bitisset,a new checksum willbe insertedintheancillarydatareplacing thepreviousone.Ifa checksum errorisdetectedand theANC Checksum Force bitisnotset,thechecksum mismatchisreportedviatheANC Checksum Errorbit. Ancillarydata checksums may be receivedintheincomingparallelancillarydata.Alternativelytheymay be calculatedand insertedautomaticallyby the LMH0030. The CHKSUM ATTACH IN bitinthe controlregisters when settoa logic-1indicatesthatthechecksum istobe suppliedintheincomingdata.When theCHKSUM ATTACH IN bitisset,checksums forincomingdataare calculatedand checked againstreceivedchecksums. Calculationand insertionofnew ancillarydatachecksum iscontrolledby theANC Checksum Force bitinthe configurationand controlregisters.Ifa checksum errorisdetected(calculatedand receivedchecksums do not match)and theANC Checksum Force bitisset,a new checksum willbe insertedintheancillarydatareplacing thepreviousone.Ifa checksum errorisdetectedand theANC Checksum Force bitisnotset,thechecksum mismatchisreportedviatheANC CHECKSUM ERROR bitinthecontrolregisters. The ANC Checksum Error bitindicatesthatthe receivedancillarydata checksum did not agree withthe LMH0030's internallygeneratedchecksum.Thisbitisavailableas an outputon themultifunctionI/Oport. ANC REGISTERS 1 THROUGH 4 (Address 05h through 08h) AdmissionofancillarydatapacketsintotheFIFO can be controlledby theANC MASK[15:0] and ANC ID[15:0] bitsinthecontrolregisters.The ANC ID[7:0]registercan be settoa valid8-bitData Identification(DID)code used forcomponent ancillarydatapacketidentificationas specifiedinSMPTE 291M. Similarly,theANC ID[15:8] registercan be settoa valid8-bitSecondaryData Identification(SDID)orData BlockNumber (DBN) code.The ANC MASK[7:0] isan 8-bitword thatcan be used toselectivelycontrolloadingofpacketswithspecificDIDs (or DID ranges)intothe FIFO. Similarly,the ANC MASK[15:8] isan 8-bitword thatcan be used to selectively controlloadingofpacketswithspecificSDID orDBNs (orSDID orDBN ranges). Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com When ANC MASK[7:0] orANC MASK[15:8] issettoFFh, packetswithany DID,SDID orDBN can be loaded intothe FIFO. When any bitor bitsof ANC MASK[7:0] or ANC MASK[15:8] are set to a logic-1,the correspondingbitor bitsofANC ID[7:0]or ANC ID[15:8],respectivelyare a don't-carewhen matchingIDs of incomingpackets.When ANC MASK[7:0] orANC MASK[15:8] issetto00h,theDID,SDID orDBN ofincoming packetsmust match exactly,bit-for-bit,thesettingofANC ID[7:0]orANC ID[15:8]inthecontrolregisterforthe packetstobe loadedintotheFIFO.The initialvalueofANC MASK[7:0] and ANC MASK[15:8] isFFh.The initial valueofANC ID[7:0]and ANC ID[15:8]is00h. Bits7 through0 ofRegisterANC 1,ANC ID[7:0],and RegisterANC3, ANC MASK[7:0],affectDID[7:0].BIts7 through0 of RegisterANC2, ANC ID[15:8], and RegisterANC 4, ANC MASK[15:8], affectSDID[7:0]or DBN[7:0]. ANC REGISTER 5 (Address 17h) The FIFO INSERT ENABLE bitenablesinsertionofancillarydatastoredintheFIFO intotheserialdatastream. Data insertionisenabledwhen thisbitissettoa logic-1.Thisbitcan be used todelayautomaticinsertionofdata intotheserialdatastream. SettingtheFIFO FLUSH STAT bittoa logic-1flushestheFIFO. Data may notbe loadedintotheFIFO during FIFO FLUSH STAT execution.Similarly,FIFO FLUSH STAT may not be setwhen data isbeinginputto the FIFO. FIFO FLUSH STAT is automaticallyresetafterthisoperationis complete.Executionof these FIFO operationsrequirestogglingofACLK . ANC REGISTER 6 (Addresses 18h) The ANC PARITY MASK bitwhen setdisablesparitycheckingfortheDATA ID (DID)and SECONDARY DATA ID (SDID)orData BlockNumber (DBN) intheANC datapacket.When reset,paritycheckingisenabled,and,ifa parityerroroccurs,thepacketwillnotbe loaded. The VANC bitinthecontrolregisters,when settoa logic-1,enablesinsertionofancillarydataduringthevertical blankinginterval. SWITCH POINT REGISTERS 0 THROUGH 3 (Addresses 09h,0Ah, 19h and 1Ah) The Line[10:0]and Protect[4:0]bitsdefinethe verticalswitchingpointlineand number of protectedlines followingtheswitchingpointlineforfields0 and 1 (orfields1 and 2 as thesearesometimes referredto)ofhigh- definationformats.The verticalswitchingpointforcomponent digitalstandarddefinitionformatsisdefinedin SMPTE RP 168-1993.The verticalswitchingpointforhigh-definitionformatshas the same basicdefinition. However, sincethe verticalswitchingpointlinesare not necessarilystandardizedamong the varioushigh- definitionrasters,these registersprovidea convenientmeans whereby the verticalswitchingpointlineand subsequentprotectedlinesmay be specifiedby theuser.The SwitchPointregistersdo notoperateforstandard definitionformats. The Line[10:0]bitsofregistersSwitch Point0 and 1 may be loadedwitha linenumber rangingfrom0 to1023 which then specifiesthe switchingpointlineforField0. The Protect[4:0]bitsof registerSwitch Point 1 determinethenumber oflinesfrom0 to15 aftertheverticalswitchingpointlineinwhichancillarydatamay not be inserted.LINE(0)istheLSB and LINE(10)istheMSB fortheLine[10:0]bits.Similarorderingholdsforthe Protect[4:0]bits. The Line[10:0]and Protect[4:0]bitsofregistersSwitch Point2 and 3 performthesame functionas explained above fortheverticalswitchingpointlineforField1. FORMAT REGISTERS 0 (Addresses 0Bh) The LMH0030 may be settoprocessa singlevideoformatby writingtheappropriatedataintotheFORMAT 0 register.The Format Set[4:0]bitsconfinethe LMH0030 to recognizeand processonlyone of the fourteen specifiedtypesofstandardorhighdefinitionformats.When theLMH0030 issettoprocessa singleformat,itwill notrecognizeand thereforewillnotprocessotherformatsthatitiscapableofrecognizing.The Format Set[4:0] bitsmay notbe used toconfinedeviceoperationtoa range ofstandards.For normaloperatingsituations,itis recommended thattheLMH0030 be operatedinautomaticformatdetectionmode, i.e.thattheFormat 0 register be setto00h.

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 The availableformatsand codes aredetailedinTable4.Generallyspeaking,theFormat Set[4:0]codes indicate or group theformatsas follows:Format Set[4]issetfortheHD formatsand resetfortheSD formats.Format Set[3]when setindicatesthatPAL dataisbeingprocessed.When resetNTSC dataisbeingprocessed.Format Set[2:0]correspondtoone ofthesub-standardsgiveninthetable.Note thattheLMH0030 makes no distinction informatsresultingfromtheprocessingofdataat74.25MHz or74.176MHz. The HD Only bitwhen settoa logic-1lockstheLMH0030 intothehighdefinitiondatarangeand frequency.In systems designedto handleonlyhighdefinitionsignals,enablingHD Only reducesthe timerequiredforthe LMH0030 toestablishfrequencylockand determinetheHD formatbeingprocessed. The SD Only bitwhen set to a logic-1locksthe LMH0030 intothe standarddefinitiondata ranges and frequencies.Insystemsdesignedtohandleonlystandarddefinitionsignals,enablingSD Only reducesthetime requiredfortheLMH0030 toestablishfrequencylockand determinetheformatbeingprocessed.When SD Only and HD Only aresettologic-0,thedeviceoperatesinSD/HD mode. Table4.Video RasterFormat Parameters Format Frame ActiveCode Format Specification Lines ActiveLines SamplesRate Samples[4,3,2,1,0]

00001 SDTV, 54 SMPTE 344M 60I 525 507/487 3432 2880

00010 SDTV, 36 SMPTE 267M 60I 525 507/487 2288 1920

00011 SDTV, 27 SMPTE 125M 60I 525 507/487 1716 1440

01001 SDTV, 54 ITU-R BT 601.5 50I 625 577 3456 2880 01010 SDTV, 36 ITU-R BT 601.5 50I 625 577 2304 1920 01011 SDTV, 27 ITU-R BT 601.5 50I 625 577 1728 1440 10001 HDTV, 74.25 SMPTE 260M 30I 1125 1035 2200 1920 10010 HDTV, 74.25 SMPTE 274M 30I 1125 1080 2200 1920 10011 HDTV, 74.25 SMPTE 274M 30P 1125 1080 2200 1920 11001 HDTV, 74.25 SMPTE 274M 25I 1125 1080 2640 1920 11010 HDTV, 74.25 SMPTE 274M 25P 1125 1080 2640 1920 11100 HDTV, 74.25 SMPTE 295M 25I 1250 1080 2376 1920 11101 HDTV, 74.25 SMPTE 274M 24P 1125 1080 2750 1920 10100 HDTV, 74.25 SMPTE 296M 60P 750 720 1650 1280 FORMAT REGISTER 1 (Address 0Ch) The LMH0030 can automaticallydeterminetheformatoftheincomingparalleldata.The resultofthisoperationis storedintheFORMAT 1 register.The Format[4:0]bitsidentifywhichofthemany possiblevideodatastandards thattheLMH0030 can processisbeingreceived.These formatcodes followthesame arrangementas forthe Format Set[4:0]bits.These formatsand codes aregiveninTable4.BitFormat[4]when setindicatesthatHD dataisbeingprocessed.When reset,SD dataisindicated.Format[3]when setindicatesthatPAL dataisbeing processed.When resetNTSC dataisbeingprocessed.Format[2:0]correspondwithone ofthesub-standards giveninthetable. The H, V, and F bitsregistercorrespondto inputTRS data bits6, 7 and 8, respectively.The meaning and functionofthisdataisthesame forbothstandarddefinition(SMPTE 125M) and highdefinition(SMPTE 292M luminanceand colordifference)videodata.Polarityislogic-1equalsHIGH-true.These bitsareregisteredforthe durationoftheapplicablefield. TEST 0 REGISTER (Address 0Dh) The Test PatternSelectbitsdeterminewhich testpatternisoutputwhen the Test PatternGenerator(TPG) mode ortheBuilt-inSelf-Test(BIST)mode isenabled.Table5 givesthecodes correspondingtothevarioustest patterns.AllHD colorbars testpatternsare BIST data.StandardDefinitionBIST testpatternsare:NTSC, 27MHz, 4x3 colorBarsand PAL, 27MHz, 4x3 PLL Pathological. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com The TPG Enable bitwhen setto a logic-1enablesthe Test PatternGeneratorfunctionand built-inself-test (BIST).Thisbitismapped toI/Oportbit7 inthedefaultcondition.Note thattheinputpulldownon theI/Oportbit has the effectof overridingthe logiclevelof data beingwrittenintothe registerviathe ancillary/ControlData Port.Incases where itisdesiredtocontrolthestateofTPG Enable throughthecontrolregisterinsteadofthe multi-functionI/Oport,bit7,theI/Oportbitmust be remapped toanotherbitinthecontrolregisters.Remapping to a read-onlyfunctionis recommended to avoid possibleconflictingdata being writtenintothe remapped location. The Pass/Failbitindicatestheresultofrunningthebuilt-inself-test.Thisbitisa logic-1fora pass condition.The bitismapped toI/Oportbit6 inthedefaultcondition. VIDEO INFO 0 REGISTER (Address 0Eh) The NSP (New Sync Position)bitindicatesthata new or out-of-placeTRS characterhas been detectedinthe inputdata.Thisbitissettoa logic-1and remainssetforatleastone horizontallineperiodorunlessre-activated by a subsequentnew orout-of-placeTRS. Itisresetby an EAV TRS character. The EAV (end of activevideo)and SAV (startof activevideo)bitstrackthe occurrenceof the corresponding TRS characters. Lock Detectisregisteredas a controlsignaland isa logic-1when thePLL islockedand a validformathas been detected.Thisbitmay be programmed as an outputon themulti-functionI/Oport.Thisbitismapped toI/Oport bit4 inthedefaultcondition.Thisfunctionalsoincludeslogictocheck thestabilityofthedeviceafterthedigital logicresetisreleasedfollowingPLL lock.Ifthesystem isnotfullystable,thelogicisautomaticallyreset.LOCK DETECT also combines the functionof indicatingthatthe LMH0030 has detectedthe video formatbeing received.Thisformatdetectfunctioninvolvesdeterminationofthemajorrasterparameterssuch as linelength, number of videolinesina frame,and so forth.Thisisdone so thatinformationlikelinenumbering can be correctlyinserted.The PLL itselfwillhave lockedinabout50 microseconds(HD rates,150 microsecondsforSD) orless;however,resolutionofallrasterparametersmay takethemajorityofa frame. The VPG FilterEnable bitwhen setenablesoperationoftheVideo PatternGeneratorfilter.Operationofthis filtercauses theinsertionoftransitioncodes inthechroma and luma dataofcolorbartestpatternswhere these patternschange from one bar tothenext.Thisfilterreducesthemagnitudeofout-of-bandfrequencyproducts which can be producedby abrupttransitionsinthechroma and luma datawhen fedtoD-to-Aconvertersand picturemonitors.The defaultconditionofthisbitisreset(off). A method by which theoccurrenceofpathologicaldatapatternscan be preventedhas been proposedforSD formats.The LMH0030 implementsthisprocessforSD formats.The DitherEnable and VerticalDitherEnable bitscontroloperationofpseudo-randomditheringappliedtothetwo LSBs ofthevideodata.Ditheringisapplied toactivevideodatawhen theDitherEnable bitisset.When theVerticalDitherEnable bitisset,ditheringis appliedtothatportionofthevideolinecorrespondingtoactivevideoforlinesintheverticalblankinginterval. I/OPIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h) The Multi-functionI/OBus Pin Configurationregistersareused tomap thebitsofthemulti-functionI/Oportto selectedbitsoftheConfigurationand ControlRegisters.Table6 detailstheavailableConfigurationand Control registerbitfunctionsthatmay be mapped totheportand theircorrespondingmapping addresses.Pin # SEL[5] ineach registerindicateswhethertheportpinisinputoroutput.The portpinwillbe an inputwhen thisbitisset and an outputwhen reset.Input-onlyfunctionsmay notbe configuredas outputsand viceversa.The remaining lower-orderfiveaddressbitsdistinguishtheparticularfunction. Example: Program,viatheAD port,I/Oportbit0 as outputfortheSAV bitinthecontrolregisters. 1. SetANC/ CTRL toa logic-low. 2. SetRD/WR toa logic-low. 3. Present00Fh toAD[9:0]as theI/OPIN 0 CONFIG registeraddress(seeTable3). 4. ToggleACLK . 5. Present30Dh toAD[9:0]as the registerdata,the bitaddressof the SAV bitinthe controlregisters(see Table6). 6. ToggleACLK .

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 TEST MODE 0 REGISTER (Address 55h) The fourbitsofthisregisterareintendedforuse as testmode functions.They arenotnormaloperatingmodes. The bitsmay be set(enabled)or reset(disabled)by writingtotheregister.Reading thisregistersets(enables) allbitstotheirdefaultON condition. The Scrambler_EnablebitenablesoperationoftheSMPTE scramblerfunction.ThisbitisnormallyON. The NRZI_Enable bitenablesoperationoftheNRZ-to-NRZIconversionfunction.ThisbitisnormallyON. The LSB_Clipping bitenablesoperationoftheLSB clippingfunction.ThisbitisnormallyON. The Sync_Detect_EnablebitenablesoperationoftheTRS detectorfunction.ThisbitisnormallyON. Table5.TestPatternSelectionCodes (1) TestPattern Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SelectWord Bits> 1=HD 1=Progressive 00=Black 0=Interlaced 01=PLL Path.Video Raster Standard 0=SD 1=PAL 10=EQ Path. 0=NTSC 11=colorBars 1125 Line,74.25MHz, 30 Frame InterlacedComponent (SMPTE 260M) Ref.Black 1 0 0 0 0 0 PLL Path. 1 0 0 0 0 1 EQ Path. 1 0 0 0 1 0 colorBars 1 0 0 0 1 1 1125 Line,74.25MHz, 30 Frame InterlacedComponent (SMPTE 274M) Ref.Black 1 0 0 1 0 0 PLL Path. 1 0 0 1 0 1 EQ Path. 1 0 0 1 1 0 colorBars 1 0 0 1 1 1 1125 Line,74.25MHz, 25 Frame InterlacedComponent (SMPTE 274M) Ref.Black 1 0 1 0 0 0 PLL Path. 1 0 1 0 0 1 EQ Path. 1 0 1 0 1 0 colorBars 1 0 1 0 1 1 1125 Line,74.25MHz, 25 Frame InterlacedComponent (SMPTE 295M) Ref.Black 1 0 1 1 0 0 PLL Path. 1 0 1 1 0 1 EQ Path. 1 0 1 1 1 0 colorBars 1 0 1 1 1 1 1125 Line,74.25MHz, 30 Frame ProgressiveComponent (SMPTE 274M) Ref.Black 1 1 0 0 0 0 PLL Path. 1 1 0 0 0 1 EQ Path. 1 1 0 0 1 0 colorBars 1 1 0 0 1 1 1125 Line,74.25MHz, 25 Frame ProgressiveComponent (SMPTE 274M) Ref.Black 1 1 0 1 0 0 PLL Path. 1 1 0 1 0 1 EQ Path. 1 1 0 1 1 0 colorBars 1 1 0 1 1 1 (1) Note:SD BIST patternsareNTSC 4x3 colorBarsand PAL 4x3 PLL Pathological.HD BIST patternsarecolorbarsforeach format. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Table5.TestPatternSelectionCodes (1)(continued) TestPattern Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SelectWord Bits> 1125 Line,74.25MHz, 24 Frame ProgressiveComponent (SMPTE 274M) Ref.Black 1 1 1 0 0 0 PLL Path. 1 1 1 0 0 1 EQ Path. 1 1 1 0 1 0 colorBars 1 1 1 0 1 1 750 Line,74.25MHz, 60 Frame ProgressiveComponent (SMPTE 296M) Ref.Black 1 1 1 1 0 0 PLL Path. 1 1 1 1 0 1 EQ Path. 1 1 1 1 1 0 colorBars 1 1 1 1 1 1

525 Line,30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M)

Ref.Black 0 0 0 0 0 0 PLL Path. 0 0 0 0 0 1 EQ Path. 0 0 0 0 1 0 colorBars(SD 0 0 0 0 1 1 BIST) 625 Line,25 Frame, 27 MHz, PAL 4x3 (ITU-TBT.601) Ref.Black 0 1 0 0 0 0 PLL Path.(SD 0 1 0 0 0 1 BIST) EQ Path. 0 1 0 0 1 0 colorBars 0 1 0 0 1 1

525 Line,30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M)

Ref.Black 0 0 0 1 0 0 PLL Path. 0 0 0 1 0 1 EQ Path. 0 0 0 1 1 0 colorBars 0 0 0 1 1 1 625 Line,25 Frame, 36 MHz, PAL 16x9 (ITU-TBT.601) Ref.Black 0 1 0 1 0 0 PLL Path. 0 1 0 1 0 1 EQ Path. 0 1 0 1 1 0 colorBars 0 1 0 1 1 1

525 Line,30 Frame, 54 MHz (NTSC)

Ref.Black 0 0 1 0 0 0 PLL Path. 0 0 1 0 0 1 EQ Path. 0 0 1 0 1 0 colorBars 0 0 1 0 1 1

625 Line,25 Frame, 54 MHz (PAL)

Ref.Black 0 1 1 0 0 0 PLL Path. 0 1 1 0 0 1 EQ Path. 0 1 1 0 1 0 colorBars 0 1 1 0 1 1

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 Table6.I/OConfigurationRegisterAddresses forControlRegisterFunctions BitAddress Pin # SEL [n] Power-OnRegisterBit I/Por O/P Status[5] [4] [3] [2] [1] [0] reserved 0 0 0 0 0 0 FF FlagError 0 0 0 0 0 1 Output AP FlagError 0 0 0 0 1 0 Output ANC Flag 0 0 0 0 1 1 Output Error CRC Error 0 0 0 1 0 0 Output I/OPortBit5 (SD/HD) Addressesx05h throughx0Ch arereserved. SAV 0 0 1 1 0 1 Output EAV 0 0 1 1 1 0 Output NSP 0 0 1 1 1 1 Output F 0 1 0 0 1 0 Output I/OPortBit0 V 0 1 0 0 1 1 Output I/OPortBit1 H 0 1 0 1 0 0 Output I/OPortBit2 Format[0] 0 1 0 1 0 1 Output Format[1] 0 1 0 1 1 0 Output Format[2] 0 1 0 1 1 1 Output Format[3] 0 1 1 0 0 0 Output Format[4] 0 1 1 0 0 1 Output I/OPortBit3 (SD/HD) FIFO Full 0 1 1 0 1 0 Output FIFO Empty 0 1 1 0 1 1 Output Lock Detect 0 1 1 1 0 0 Output I/OPortBit4 Pass/Fail 0 1 1 1 0 1 Output I/OPortBit6 FIFO Overrun 0 1 1 1 1 0 Output ANC Chksum 0 1 1 1 1 1 Output Error EDH Force 1 0 0 0 0 0 Input TestPattern 1 0 0 0 0 1 Input Select[0] TestPattern 1 0 0 0 1 0 Input Select[1] TestPattern 1 0 0 0 1 1 Input Select[2] TestPattern 1 0 0 1 0 0 Input Select[3] TestPattern 1 0 0 1 0 1 Input Select[4] TestPattern 1 0 0 1 1 0 Input Select[5] EDH Enable 1 0 0 1 1 1 Input TPG Enable 1 0 1 0 0 0 Input I/OPortBit7 reserved 1 0 1 0 0 1 Chksum 1 0 1 0 1 0 Input AttachIn reserved 1 0 1 0 1 1 VPG Filter 1 0 1 1 0 0 Input Enable DitherEnable 1 0 1 1 0 1 Input Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Table6.I/OConfigurationRegisterAddresses forControlRegisterFunctions(continued) BitAddress Pin # SEL [n] Power-OnRegisterBit I/Por O/P Status[5] [4] [3] [2] [1] [0] FIFO Insert 1 0 1 1 1 1 Input Enable

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013 PIN DESCRIPTIONS (1) Pin Name Description 1 VDDPLLD PositivePower SupplyInput(2.5Vsupply,PLL Logic) 2 VSSPLLD NegativePower SupplyInput(2.5Vsupply,PLL Logic)

3 IO0 Multi-FunctionI/OPort

4 IO1 Multi-FunctionI/OPort

5 DV0 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

6 DV1 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

7 DV2 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

8 DV3 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

9 DV4 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

10 VSSD NegativePower SupplyInput(2.5Vsupply,DigitalLogic)

11 DV5 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

12 DV6 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

13 DV7 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

14 DV8 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

15 DV9 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

16 VDDD PositivePower SupplyInput(2.5Vsupply,DigitalLogic) 17 VSSD NegativePower SupplyInput(2.5Vsupply,DigitalLogic)

18 DV10 ParallelVideoInput(HD=Luma)

19 DV11 ParallelVideoInput(HD=Luma)

20 DV12 ParallelVideoInput(HD=Luma)

21 DV13 ParallelVideoInput(HD=Luma)

22 DV14 ParallelVideoInput(HD=Luma)

23 VDDIO PositivePower SupplyInput(3.3Vsupply,I/O)

24 DV15 ParallelVideoInput(HD=Luma)

25 DV16 ParallelVideoInput(HD=Luma)

26 DV17 ParallelVideoInput(HD=Luma)

27 DV18 ParallelVideoInput(HD=Luma)

28 DV19 ParallelVideoInput(HD=Luma)

29 VSSIO NegativePower SupplyInput(3.3Vsupply,I/O)

30 IO2 Multi-FunctionI/OPort

31 IO3 Multi-FunctionI/OPort

32 IO4 Multi-FunctionI/OPort

33 IO5 Multi-FunctionI/OPort

34 IO6 Multi-FunctionI/OPort

35 IO7 Multi-FunctionI/OPort

36 ACLK Ancillary/ControlClockInput

37 VDDD PositivePower SupplyInput(2.5Vsupply,DigitalLogic)

38 AD0 Ancillary/ControlData I/OPort

39 AD1 Ancillary/ControlData I/OPort

40 AD2 Ancillary/ControlData I/OPort

41 AD3 Ancillary/ControlData I/OPort

42 AD4 Ancillary/ControlData I/OPort

43 VSSD NegativePower SupplyInput(2.5Vsupply,DigitalLogic)

44 AD5 Ancillary/ControlData I/OPort

45 AD6 Ancillary/ControlData I/OPort

46 AD7 Ancillary/ControlData I/OPort

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (1)(continued) Pin Name Description

47 AD8 Ancillary/ControlData I/OPort

48 AD9 Ancillary/ControlData I/OPort

49 RD/WR Ancillary/ControlData PortRead/WriteControlInput

50 ANC/ CTRL Ancillary/ControlData PortFunctionControlInput

51 VDDSD PositivePower SupplyInput(3.3Vsupply,OutputDriver) 52 R REF PRE OutputPreemphasisReferenceResistor(4.75KΩ,1% Nom.) 53 R REF LVL OutputLevelReferenceResistor(4.75KΩ,1% Nom.) 54 VSSSD NegativePower SupplyInput(3.3Vsupply,OutputDriver) 55 VSSSD NegativePower SupplyInput(3.3Vsupply,OutputDriver)

56 SDO SerialData TrueOutput

57 VDDLS PositivePower SupplyInput(3.3Vsupply,LevelShift)

58 SDO SerialData Complement Output

59 VSSLS NegativePower SupplyInput(3.3Vsupply,LevelShift) 60 VDDZ PositivePower SupplyInput(2.5Vsupply,Serializer) 61 VSSPLLA NegativePower SupplyInput(2.5Vsupply,PLL Analog) 62 VDDPLLA PositivePower SupplyInput(2.5Vsupply,PLL Analog)

63 VCLK VideoData ClockInput

64 Reset Manual ResetInput(HighTrue)

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www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013

APPLICATION INFORMATION

Complete detailsfortheSD130ASM evaluationPCB are availableon TI’s WEB site.Thiscircuitdemonstrates thecapabilitiesoftheLMH0030 and allowsitsevaluationina nativeconfiguration.An assembled demonstration boardkit,partnumber SD130EVK, completewithoperatinginstructions,drawingpackage and listofmaterialsis available.ContacttheInterfaceProductsGroup or theSerialDigitalVideo and InterfaceApplicationsGroup for orderinginformation.Complete circuitboard layouts,schematicsand otherinformationforthe SD130EVK are alsoavailableon TI'sWEB sitein the applicationinformationforthisdevice.For latestproductdetailsand availabilityinformation,pleasesee:www.ti.com/appinfo/interface. PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuitboardlayoutand stack-upfortheLMH0030 shouldbe designedtoprovidenoise-freepower tothedevice. Good layoutpracticealsowillseparatehighfrequencyor highlevelinputsand outputsto minimizeunwanted straynoisepickup,feedbackand interference.Power systemperformancemay be greatlyimprovedby usingthin dielectrics(4to10 mils)forpower/groundsandwiches.ThisincreasestheintrinsiccapacitanceofthePCB power system which improves power supply filtering,especiallyat high frequencies,and makes the value and placementofexternalbypass capacitorslesscritical.Externalbypass capacitorsshouldincludebothRF ceramic and tantalumelectrolytictypes.RF capacitorsmay use valuesin the range 0.01 µF to 0.1 µF. Tantalum capacitorsmay be intherange2.2µF to10 µF.Voltageratingfortantalumcapacitorsshouldbe atleast5X the power supplyvoltagebeingused.Itisrecommended practicetouse two viasateach power pinoftheLMH0030 as wellas allRF bypass capacitorterminals.Dual viasreducetheinterconnectinductanceby up tohalf,thereby reducinginterconnectinductanceand extendingtheeffectivefrequencyrangeofthebypasscomponents. The outerlayersof the PCB may be floodedwithadditionalVSS (ground)plane.These planeswillimprove shieldingand isolationas wellas increasetheintrinsiccapacitanceofthepower supplyplanesystem.Naturally, tobe effective,theseplanesmust be tiedtotheVSS power supplyplaneatfrequentintervalswithvias.Frequent viaplacementalsoimprovessignalintegrityon signaltransmissionlinesby providingshortpaths forimage currentswhich reduces signaldistortion.The planesshouldbe pulledback from alltransmissionlinesand component mountingpads a distanceequaltothewidthofthewidesttransmissionlineor thethicknessofthe dielectricseparatingthetransmissionlinefromtheinternalpower orgroundplane(s)whicheverisgreater.Doing so minimizeseffectson transmissionlineimpedances and reduces unwanted parasiticcapacitancesat component mountingpads. The LMH0030 uses two power supplyvoltages,2.5and 3.3volts.These suppliesconnecttothedevicethrough seven setsofindependentpower inputpins.The functionand system suppliedthroughtheseisgiveninthePin DescriptionTable.The power supplyvoltagesnormallysharea common 0 voltorgroundreturnsystem.Eithera splitplaneorseparatepower planescan be used tosupplythepositivevoltagestothedevice. Inespeciallynoisypower supplyenvironments,such as isoftenthecase when usingswitchingpower supplies, separatefilteringmay be used attheLMH0030's PLL analog,PLL digitaland serialoutputdriverpower pins.The LMH0030 was designedforthissituation.The digitalsection,PLL and outputdriverpower supplyfeedsare independent.See thePinDescriptionTableand theConnectionDiagram fordetails.Supplyfilteringmay takethe form ofL-sectionor pi-section,L-C filtersinserieswiththeseVDD inputs.Such filtersare availableina single package from severalmanufacturers.Despitebeing independentfeeds,alldevicepower suppliesshouldbe appliedsimultaneouslyas froma common source. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LMH0030

SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com PROCESSING NON-SUPPORTED AND pSf RASTER FORMATS The number and typeofHD rasterformatshas proliferatedgreatlysincetheLMH0030 was designed.Though notspecificallycapableoffullyorautomaticallyprocessingthesenew formats,theLMH0030 may stillbe capable ofserializingthem.The userisencouragedtoexperimentwithprocessingoftheseformatskeepinginmind that theLMH0030 has notbeen testedtohandlerasterformatsotherthanthosedetailedinTable4.Therefore,the resultsfrom attemptsto processnon-supportedformatsisnot ensured.The followingguidelinesconcerning devicesetupareprovidedtoaidtheuserinconfiguringtheLMH0030 toattemptlimitedprocessingoftheseother rasterformats.Ingeneral,thedeviceisconfiguredtodefeatitsformatand TRS detectionfunctionand tolimit operationto a genericHD formattype.(The user shouldconsultTable 4 forguidanceon the formatgroups similartothenon-supportedone tobe processed).Sincethesenewer formatsareintheHD realm,theLMH0030 shouldbe configuredtooperateinHD-ONLY mode by settingbit-5oftheFORMAT 0 register(address0Bh). Also,thedeviceshouldbe furtherconfiguredby loadingtheFORMAT SET[4:0]bitsofthisregisterwitha non- specificHD sub-formatcode.The completedataword forthisHD sub-formatcode withHD-ONLY bitsetis33Fh (all10 bitsofAD[9:0]).Sincethisformatdiffersfrom thoseinthetable,theEAV/SAV indicatorsare disabled. Withouttheseindicators,linenumbering and CRC insertionare disabledand ancillarydata insertionwillnot function.Pre-processingoftheparalleldataahead oftheLMH0030 willbe requiredtoinsertCRC dataand line numbering. Among the specializedformatsare so-calledprogressive-segmentedframe formats(pSf).Refer to SMPTE 274M-2003,Annex A. These formatsarecomposed ofthevideolinesofprogressivescan rastersrearrangedin themanner ofan interlacedraster.The even numbered linesarearrangedtoformField1 and theodd numbered linesform Field2.Inotherrespects,theformatisidenticaltothenormalinterlacedformat.The LMH0030 can serializethesepSf formatsprovidedthatthelinesoftheoriginalprogressiverasterarefirstrearrangedexternally totheLMH0030 beforebeingpresentedtoitforprocessing.

ProductFolderLinks:LMH0030

www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013

REVISION HISTORY

www.ti.com 3-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMH0030VS NRND TQFP PAG 64 160 TBD Call TI Call TI 0 to 70 L030 LMH0030VS/NOPB ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 L030 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 3-Nov-2013 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 4040282/C 11/96 Gage Plane 0,17 0,27 7,50 TYP SQ 9,80 1,05 0,95 11,80 12,20 1,20 MAX 10,20 SQ 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: SD130EVK

Summary

SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver

Description

SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver

Source title LMH0030VS/NOPB Datasheet(PDF) - Texas Instruments

Read LMH0030VS/NOPB online.

LMH0030_14 TI1 | Alldatasheet

Document overview

Technical content

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0 Vdc

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00001 SDTV, 54 SMPTE 344M 60I 525 507/487 3432 2880

00010 SDTV, 36 SMPTE 267M 60I 525 507/487 2288 1920

00011 SDTV, 27 SMPTE 125M 60I 525 507/487 1716 1440

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525 Line,30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M)

525 Line,30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M)

525 Line,30 Frame, 54 MHz (NTSC)

625 Line,25 Frame, 54 MHz (PAL)

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3 IO0 Multi-FunctionI/OPort

4 IO1 Multi-FunctionI/OPort

5 DV0 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

6 DV1 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

7 DV2 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

8 DV3 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

9 DV4 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

11 DV5 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

12 DV6 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

13 DV7 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

14 DV8 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

15 DV9 ParallelVideoInput(HD=Chroma, SD=Luma & Chroma)

18 DV10 ParallelVideoInput(HD=Luma)

19 DV11 ParallelVideoInput(HD=Luma)

20 DV12 ParallelVideoInput(HD=Luma)

21 DV13 ParallelVideoInput(HD=Luma)

22 DV14 ParallelVideoInput(HD=Luma)

24 DV15 ParallelVideoInput(HD=Luma)

25 DV16 ParallelVideoInput(HD=Luma)

26 DV17 ParallelVideoInput(HD=Luma)

27 DV18 ParallelVideoInput(HD=Luma)

28 DV19 ParallelVideoInput(HD=Luma)

30 IO2 Multi-FunctionI/OPort

31 IO3 Multi-FunctionI/OPort

32 IO4 Multi-FunctionI/OPort

33 IO5 Multi-FunctionI/OPort

34 IO6 Multi-FunctionI/OPort

35 IO7 Multi-FunctionI/OPort

36 ACLK Ancillary/ControlClockInput

38 AD0 Ancillary/ControlData I/OPort

39 AD1 Ancillary/ControlData I/OPort

40 AD2 Ancillary/ControlData I/OPort

41 AD3 Ancillary/ControlData I/OPort

42 AD4 Ancillary/ControlData I/OPort

44 AD5 Ancillary/ControlData I/OPort

45 AD6 Ancillary/ControlData I/OPort

46 AD7 Ancillary/ControlData I/OPort

47 AD8 Ancillary/ControlData I/OPort

48 AD9 Ancillary/ControlData I/OPort

49 RD/WR Ancillary/ControlData PortRead/WriteControlInput

50 ANC/ CTRL Ancillary/ControlData PortFunctionControlInput

56 SDO SerialData TrueOutput

58 SDO SerialData Complement Output

63 VCLK VideoData ClockInput

64 Reset Manual ResetInput(HighTrue)

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APPLICATION INFORMATION

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REVISION HISTORY

LMH0030VS/NOPB specifications and overview.

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