LMH0030

LMH0030 NSC | Alldatasheet

Document overview

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Technical content

Features

n SDTV/HDTV serial digital video standard compliant n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps and 1.485 Gbps SDV data rates with auto-detection n Low output jitter: 125ps max, 85ps typical n Low power: typically 430mW n No external serial data rate setting or VCO filtering components required* n Fast PLL lock time: < 150µs typical at 1.485 Gbps n Adjustable depth video FIFO for timing alignment n Built-in self-test (BIST) and video test pattern generator (TPG)* n Automatic EDH/CRC word and flag generation and insertion n On-chip ancillary data FIFO and insertion control circuitry n Flexible control and configuration I/O port n LVCMOS compatible data and control inputs and outputs n 75Ω ECL-compatible, differential, serial cable-driver outputs n 3.3V I/O power supply and 2.5V logic power supply operation n 64-pin TQFP package * Patent applications made or pending.

Applications

n SDTV/HDTV parallel-to-serial digital video interfaces for: — Video cameras — VTRs — Telecines — Digital video routers and switchers — Digital video processing and editing equipment — Video test pattern generators and digital video test equipment — Video signal generators Order Number LMH0030VS 64-Pin TQFP NS Package Number VEC-64A PRELIMINARY April 2006 LMH0030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver © 2006 National Semiconductor Corporation DS201803 www.national.com

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See NS Package Number VEC-64A LMH0030 www.national.com 4

Absolute Maximum Ratings(Note 1) It is anticipated that this device will not be offered in a military qualified version.If Military/Aerospace specified devices are required, please contact the National Semicon- ductor Sales Office / Distributors for availability and specifi- cations. CMOS I/O Supply Voltage DDIO–VSSIO): 4.0V SDO Supply Voltage (VDDSD–VSSSD): 4.0V Digital Logic Supply Voltage (VDDD–VSSD): 3.0V PLL Digital Supply Voltage (VDDPLL–VSSPLL): 3.0V PLL Analog Supply Voltage (VDDPLLA–VSSPLLA), (VDDZ −VSSD ) : 3.0V CMOS Input Voltage (Vi): VSSIO −0.15V to VDDIO +0.15V CMOS Output Voltage (Vo): VSSIO −0.15V to VDDIO +0.15V CMOS Input Current (single input): V i=V SSIO −0.15V: −5 mA V i=V DDIO +0.15V: +5 mA CMOS Output Source/Sink Current: ±10 mA SDO Output Sink Current: 40 mA Package Thermal Resistance θ JA @ 0 LFM Airflow 47˚C/W θJA @ 500 LFM Airflow 27˚C/W θJC 6.5˚C/W Storage Temp. Range: −65˚C to +150˚C Junction Temperature: +150˚C Lead Temperature (Soldering 4 Sec): +260˚C ESD Rating (HBM): 2 kV ESD Rating (MM): 250V Recommended Operating Conditions Symbol Parameter Conditions Reference Min Typ Max Units VDDIO CMOS I/O Supply Voltage V DDIO−VSSIO 3.150 3.300 3.450 V VDDSD SDO Supply Voltage V DDSD−VSSSD 3.150 3.300 3.450 V VDDD Digital Logic Supply Voltage VDDD–VSSD 2.375 2.500 2.625 V VDDPLL PLL Supply Voltage V DDPLL–VSSPLL 2.375 2.500 2.625 V VDDZ Analog Supply Voltage V DDZ–VSSD 2.375 2.500 2.625 V VIL CMOS Input Voltage, Low Level VSSIO V VIH CMOS Input Voltage High Level VDDIO V TA Operating Free Air Temperature 0 +70 ˚C tJIT Video Clock Jitter V CLK 30 ps P-P Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units VIH Input Voltage High Level All LVCMOS Inputs

2.0 V DDIO V

VIL Input Voltage Low Level V SSIO 0.8 V IIH Input Current High Level V IH =V DDIO +90 +150 µA IIL Input Current Low Level V IL =V SSIO −1 −20 µA VOH CMOS Output Voltage High Level IOH = −6.6 mA All LVCMOS Outputs 2.4 2.7 V DDIO V VOL CMOS Output Voltage Low Level IOL = +6.6 mA VSSIO VSSIO +0.3 VSSIO +0.5V V VSDO Serial Driver Output Voltage Test Circuit, Test Loads Shall Apply SDO, SDO 720 800 880 mV P-P IDD (3.3V) Power Supply Current, 3.3V Supply, Total VCLK = 27 MHz, NTSC color Bar Pattern, Test Circuit, Test Loads Shall Apply V DDIO,V DDSD 48 65 mA LMH0030 www.national.com5

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units IDD (3.3V) Power Supply Current, 3.3V Supply, Total VCLK = 74.25 MHz, NTSC color Bar Pattern, Test Circuit, Test Loads Shall Apply V DDIO,V DDSD 66 90 mA IDD (2.5V) Power Supply Current, 2.5V Supply, Total VCLK = 27 MHz, NTSC color Bar Pattern, Test Circuit, Test Loads Shall Apply V DDD,V DDZ, VDDPLL 66 85 mA IDD (2.5V) Power Supply Current, 2.5V Supply, Total VCLK = 74.25 MHz, NTSC color Bar Pattern, Test Circuit, Test Loads Shall Apply V DDD,V DDZ, VDDPLL 85 110 mA Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Conditions Reference Min Typ Max Units fVCLK Parallel Video Clock Frequency VCLK 27 74.25 MHz DCV Video Clock Duty Cycle VCLK 45 50 55 % fACLK Ancillary Clock Frequency ACLK VCLK MHz DCA Ancillary Clock Duty Cycle ACLK 45 50 55 % tr,t f Input Clock and Data Rise Time, Fall Time 10%–90% V CLK,A CLK,D VN, ADN 1.0 1.5 3.0 ns BRSDO Serial Data Rate (Notes 5, 6) SDO, SDO 270 1,485 M bps tr,t f Rise Time, Fall Time 20%–80%, (Note 6) SDO, SDO 270 ps tr,t f Rise Time, Fall Time 20%–80%, (Note 5) SDO, SDO 500 ps Output Overshoot (Note 4) SDO, SDO 5% tj Serial Output Jitter, Intrinsic

270 Mbps, (Notes 5, 9, 10) SDO, SDO 270 350 ps P-P

tj Serial Output Jitter, Intrinsic 1,485 Mbps, (Notes 6, 9, 10) SDO, SDO 85 125 ps P-P tLOCK Lock Time (Notes 5, 7) (SD Rates) 15 ms tLOCK Lock Time (Notes 6, 7) (HD Rates) 15 ms tS Setup Time, Video Data Timing Diagram, (Note 4) DV N to VCLK 1.5 2.0 ns tH Hold Time, Video Data Timing Diagram, (Note 4) V CLK to DVN 1.5 2.0 ns tS Setup Time, Anc. Data Port Timing Diagram, (Note 4) AD N to ACLK 1.5 2.0 ns tH Hold Time, Anc. Data Port Timing Diagram, (Note 4) A CLK to ADN 1.5 2.0 ns Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteris tics” specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to V SS =0 V . Note 3: Typical values are stated for V DDIO =V DDSD = +3.3V, VDDD =V DDPLL = +2.5V and T A = +25˚C. Note 4: Spec. is guaranteed by design. Note 5: RL =7 5Ω, AC-coupled @ 270 Mbps,R REFLVL = RREFPRE = 4.75 k Ω 1%, See Test Loadsand Test Circuit. Note 6: RL =7 5Ω, AC-coupled @ 1,485 Mbps,R REFLVL = RREFPRE = 4.75 k Ω 1%, See Test Loadsand Test Circuit. Note 7: Measured from rising-edge of first DV CLK cycle until Lock Detect output goes high (true). Lock time includes format detection time plus PLL lock time. LMH0030 www.national.com 6

Note 8: Average value measured between rising edges computed over at least one video field. Note 9: Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission standard, SMPTE 259M-1997 or SMPTE 292M (proposed). A color bar test pattern is used. The value of fSCLK is 270 MHz or 360 MHz for SMPTE 259M, 540MHz for SMPTE 344M or 1,485 MHz for SMPTE 292M serial data rates. See Timing Jitter Bandpasssection. Note 10: Intrinsic jitter is defined in accordance with SMPTE RP 184-1996 as: jitter at an equipment output in the absence of input jitter. As applied to this dev ice, the input port is V CLK and the output port is SDO or SDO. Test Loads 20180304 Timing Jitter Bandpass 20180306 LMH0030 www.national.com7

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The LMH0030 SDTV/HDTV Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts parallel SDTV or HDTV component digital video signals into serial format. Logic levels within this equipment are normally produced by LVCMOS logic devices. The encoder produces serial digital video (SDV) signals conforming to SMPTE 259M, SMPTE 344M (proposed) or SMPTE 292M. The LMH0030 operates at parallel data rates of 27.0 MHz, 36.0 MHz, 54.0 MHz, 74.176MHz and 74.25 MHz. Corresponding serial data rates are 270 Mbps, 360 Mbps, 540 Mbps, 1.4835 Gbps and 1.485 Gbps. VIDEO DATA PATH The input data registeraccepts 10-bit standard definition or 20-bit high definition parallel data and associated parallel clock signals having LVCMOS-compatible levels. All parallel video data inputs, DV[19:0], have internal pull-down de- vices. VCLK does not have an internal pull-down device. Parallel video data may conform to any of several SMPTE standards: 125M, 267M, 260M, 274M, 295M or 296M. Some segmented frame formats are not supported. For HDTV data, the upper 10 bits of the DV input are luminance (luma) information and the lower 10 bits are color difference (chrominance or chroma) information. For SDTV data, the lower order 10 bits contain both luma and chroma informa- tion. Output from this register feeds the video FIFO, video format detection circuit, TRS character detector, SMPTE scrambler, EDH/CRC generators, serializer/NRZI converter and the device control system. Data from the input data register passes into a 4-register deep video FIFO prior to encoding and other processing. The depth of this FIFO is set by theVIDEO FIFO Depth[2:0] bits of the ANC 0control register. The video format detector automatically determines the raster characteristics (video data format) of the parallel input data and configures the LMH0030 to properly handle the data. This assures that the data will be properly formatted, that the correct data rate is selected and that ancillary data, line numbers (HD) and CRC/EDH data are correctly in- serted. Indication of the standard being processed is stored in the FORMAT[4:0] bits in the FORMAT 1 control data register. This format data can be programmed for output on the multi-function I/O port. The LMH0030 normally operates in an auto-format-detection mode. It may optionally be configured to process only a single video format by writing the appropriate FORMAT SET[4:0] control data into the FORMAT 0 control register. The default state of FORMAT SET[4:0]is 0000b. Also, the LMH0030 may be configured to handle only the standard- definition data formats by setting theSD ONLYbit or only the high-definition data formats by setting theHD ONLYbit in the FORMAT 0 control register. When both of these bits are reset the part automatically selects the data rate. The TRS character detector processes the timing refer- ence signals which control raster framing. The TRS detector supplies control signals to the system controller to identify the presence of the valid video data. The system controller supplies necessary control signals to the EDH/CRC control block. TRS character LSB-clipping as prescribed in ITU-R BT.601 is used. LSB-clipping causes all TRS characters with a value between 000h and 003h to be forced to 000h and all TRS characters with a value between 3FCh and 3FFh to be forced to 3FFh. Clipping is done prior to scrambling and EDH/CRC character generation. The LMH0030 incorporates circuitry for LSB dithering. The Dither Enable bit in the VIDEO INFO 0register when set enables dithering. The V Dither Enable bit in the VIDEO INFO 0 control register when set enables dithering during the vertical blanking interval. The initial condition of Dither Enable and V Dither Enableis OFF. The SMPTE scrambleraccepts 10-bit standard definition or 20-bit high definition parallel video data and encodes it using the polynomial X 9 +X 4 + 1 as specified in the respective standard: SMPTE 259M, SMPTE 344M or SMPTE 292M. The data is then serialized and sent to the NRZ-to-NRZI converter before being output. The transmission bit order is LSB-first. The NRZ-to-NRZI converter accepts NRZ serial data from the SMPTE scrambler. The data is converted to NRZI format using the polynomial (X + 1). The converter’s output goes to the output cable driver amplifier. ANCILLARY/CONTROL DATA PATH The 10-bit, bi-directional Ancillary and Control Data Port performs two distinct functions in the LMH0030. First, it is used to selectively load ancillary data into the Ancillary Data FIFO for insertion into the video data stream. The utilization and flow of ancillary data within the device is managed by a system of control bits, masks and IDs in the control data registers. Second, this port provides read/write access to contents of the configuration and control registers. Ancillary and control data are input via the 10-bit Ancillary/ Control Data Port, AD[9:0]. The state of the RD/WR control input determines whether data is read or written to the registers or written to the Ancillary Data FIFO. The state of the ANC/CTRL control input selects which of the ancillary data or control data sub-systems is accessed through the port. LMH0030 www.national.com9

Device Operation (Continued) supplied power via external low-pass filters, if desired. PLL acquisition time is less than 200µs @ 1485 Mbps. The VCO halts when the V CLK signal is not present or is inactive. A LOCK DETECT indicator function is available as a bit in the VIDEO INFO 0 control registers. LOCK DETECT is a logic-1 when the PLL is locked and a valid format has been detected. It can be assigned as an output on the multifunc- tion I/O port. By default LOCK DETECT is assigned as I/O Port bit 4 after power-on or reset . This function also includes logic to check the stability of the device after the digital logic reset is released following PLL lock. If the system is not fully stable, the logic is automatically reset. LOCK DETECTalso combines the function of indicating that the LMH0030 has detected the video format being received. This format detect function involves determination of the major raster param- eters such as line length, number of video lines in a frame, and so forth. This is done so that information like line num- bering can be correctly inserted. The PLL itself will have locked in 200 microseconds (HD rates) or less. However, resolution of all raster parameters may take the majority of a frame. SERIAL DATA OUTPUT DRIVER The serial data outputsprovide low-skew complimentary or differential signals. The output buffer is a current-mode de- sign and is intended to drive AC-coupled and terminated, 75Ω coaxial cables. The driver automatically adjusts its out- put slew rate depending upon the data rate being processed. Output levels are 800 mV P-P ±10% into 75 Ω AC-coupled loads. The 75 Ω resistors connected to the SDO outputs function both as drain-load and back-matching resistors. Series back-matching resistors are not used with this output type. The serial output level is controlled by the value of R REFLVL and RREFPRE connected to pin 53 and pin 52, respectively. The R REFLVL resistor sets the peak-to-peak level of the output signal to the required SMPTE nominal level. The R REFPRE resistor sets the value of a pre-emphasis current which is active during the transition times of the HD-rate output signal. The value of R REFLVL is normally 4.75 K Ω, ±1%. The value of RREFPRE is normally 4.75 KΩ, ±1%. The voltage present at these pins is approximately +1.3Vdc. The transition times of this output buffer design automatically adjust and are different for the HD and SD data rate condi- tions. The output buffer is quiescent when the device is in an out-of-lock condition. The output will become active after the PLL is locked and a valid format has been detected. Sepa- rate power feeds are provided for the serial output driver: V SSSD, pins 54, 55, and 59; V DDSD, pin 51; and V DDLS, pin 57. CAUTION: This output buffer is not designed or specified for driving 50Ω or other impedance loads. POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT The LMH0030 requires two power supplies, 2.5V for the core logic functions and 3.3V for the I/O functions. The supplies must be applied to the device in proper sequence. The 3.3V supply must be applied prior to or coincident with the 2.5V supply. Application of the 2.5V supply must not precede the 3.3V supply. It is recommended that the 3.3V supply be configured or designed so as to control application of the 2.5V supply in order to satisfy this sequencing requirement. The LMH0030 has an automatic, power-on-reset circuit. Reset initializes the device and clears TRS detection cir- cuitry, all latches, registers, counters and polynomial genera- tors, sets the EDH/CRC characters to 00h and disables the serial output. Table 1 lists the initial conditions of the con- figuration and control registers. An active-HIGH-true, manual reset input is available at pin 64. The reset input has an internal pull-down device and may be considered inactive when unconnected. Important: When power is first applied to the device or following a reset, the Ancillary and Control Data Portmust be initialized to receive data. This is done by toggling ACLK three times. TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST) The LMH0030 includes a built-in test pattern generator (TPG). Four test pattern types are available for all data rates, all HD and SD formats, NTSC and PAL standards, and 4x3 and 16x9 raster sizes. The test patterns are: flat-field black, PLL pathological, equalizer (EQ) pathological and a 75%, 8-color vertical bar pattern. The pathologicals follow the recommendations of SMPTE RP 178-1996 regarding the test data used. The color bar pattern has optional bandwidth limiting coding in the chroma and luma data transitions be- tween bars. The VPG FILTER ENABLEbit in the VIDEO INFO 0control register enables the color bar filter function. The default condition of VPG FILTER ENABLEis OFF. The TPG also functions as a built-in self-test (BIST)which can verify device functionality. The BIST function performs a comprehensive go/no-go test of the device. The test may be run using any of the HD color bar test patterns or one of two SD test patterns, either a 270 Mbps NTSC full-field color bar or a PAL PLL pathological, as the test data pattern. Data is supplied internally in the input data register, processed through the device and tested for errors using either the EDH system for SD or the CRC system for HD. A go/no-go indi- cation is logged in the Pass/Fail bit of the TEST 0 control register set. This bit may be assigned as an output on the multifunction I/O port. TPG and BIST operation is initiated by loading the code for the desired test pattern into the Test Pattern Select [5:0] bits of the TEST 0 register. Table 5gives the available test patterns and codes. (Recall also the requirement to initialize the ancillary data port control logic by clockingACLK at least three (3) complete cycles before attempting to load the first register address). In the default power-on state,TPG Enable appears as bit 7 on the multi-function I/O port. The TPG is run by applying the appropriate frequency at the VCLK input for the format and rate selected and then setting the TPG Enable input on the multi-function I/O port, or by setting the TPG Enablebit in the TEST 0register. Important: If the TPG Enable input of the I/O port is in its default mapping and is not being used to enable the TPG mode, attempting to enable TPG operation by setting bit 6 of the TEST 0register will not cause the TPG to operate. This is because the low logic level at the I/O port input pulldown overrides the high level being written to the register. The result is the TPG does not run. The Pass/Fail bit in the TEST 0control register indicates the test status. If no errors have been detected, this bit will be set to logic-1 approximately 2 field intervals after TPG En- able is set. If errors have been detected in the internal circuitry of the LMH0030, Pass/Fail will remain reset to a LMH0030 www.national.com13

Device Operation (Continued) logic-0. The TPG or BIST is halted by resettingTPG Enable. The serial output data is present at the SDO outputs during TPG or BIST operation. Caution !When attempting to use the TPG or BIST imme- diately after applying power or resetting the device, the TPG defaults to the 270 Mbps SD rate and expects a V CLK clock frequency of 27MHz as input. This is because the code for the test pattern in the TEST 0register is set to 00h (525 line, 30 frame, 27MHz, NTSC 4x3 reference black). Attempting to apply a V CLK frequency higher than the device expects, according to the setting in the TEST 0register, may result in the PLL locking up while attempting to slew to its maximum possible frequency. This situation is not recoverable by the use of the device RESET input. To recover from this condi- tion, power must be removed and re-applied to the device. Proper conditioning of the V CLK input, which does not have an internal pull down device, is mandatory to prevent admis- sion of noise or unwanted signals at any time, especially during power-up or reset sequences. It is strongly recom- mended that V CLK not be applied until device initialization and configuration is completed. Example: Enable the TPG Mode to use the NTSC 270 Mbps color bars as the BIST and TPG pattern. Enable TPG opera- tion using the I/O port. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. 3. Present 00Dh to AD[9:0] as the TEST 0 register ad- dress. 4. Toggle ACLK. 5. Present 303h to AD[9:0] as the register data (525 line, 30 frame, 27MHz, NTSC 4x3, color bars (SMPTE 125M)). 6. Toggle ACLK. 7. Set TPG ENABLE(I/O Port, bit 7) to a logic-high. 8. Toggle ACLK. 9. The PASS/FAIL indicator (I/O Port, bit 6) is monitored for the result of the test. Alternatively, the TEST 0regis- ter may be read. Bit 7 is the Pass/Fail indicator bit. CONFIGURATION AND CONTROL REGISTERS The configuration and control registers store data which configures the operational modes of the LMH0030 or which result from its operation. Many of these registers can be mapped to the multi-function I/O bus to make them available as external I/O functions. These functions and initial values are summarized in Table 1 and detailed in Table 2. The power-on default condition for the multi-function I/O port is indicated in Table 1and detailed in Table 6. LMH0030 www.national.com 14

TABLE 1. Configuration and Control Data Register Summary

1 R/W OFF Input

1 R Reset Output

1 R/W OFF No

1 R Output

TABLE 1. Configuration and Control Data Register Summary(Continued) Note 11: Connected to multifunction I/O port at power-on. Note 12: ON = logic-1, OFF = logic-0 (positive logic). TABLE 2. Control Register Bit Assignments

TABLE 2. Control Register Bit Assignments(Continued)

TABLE 3. Control Register Addresses data by setting the EDH Force bit in the control registers. state of the CRC check characters is 00h. specific flag bits in these registers. the EDH function is enabled and data is being received. and EDA flags of the EDH checkwords. ite data back into the register. are available in the configuration and control register set.

Device Operation (Continued) The ANC Checksum Errorbit indicates that the received ancillary data checksum did not agree with the LMH0030’s internally generated checksum. This bit is available as an output on the multifunction I/O port. ANC REGISTERS 1 THROUGH 4 (Address 05h through 08h) Admission of ancillary data packets into the FIFO can be controlled by the ANC MASK[15:0]and ANC ID[15:0]bits in the control registers. The ANC ID[7:0]register can be set to a valid 8-bit Data Identification (DID) code used for compo- nent ancillary data packet identification as specified in SMPTE 291M. Similarly, the ANC ID[15:8] register can be set to a valid 8-bit Secondary Data Identification (SDID) or Data Block Number (DBN) code. The ANC MASK[7:0]is an 8-bit word that can be used to selectively control loading of packets with specific DIDs (or DID ranges) into the FIFO. Similarly, the ANC MASK[15:8]is an 8-bit word that can be used to selectively control loading of packets with specific SDID or DBNs (or SDID or DBN ranges). When ANC MASK[7:0]or ANC MASK[15:8]is set to FFh, packets with any DID, SDID or DBN can be loaded into the FIFO. When any bit or bits of ANC MASK[7:0] or ANC MASK[15:8] are set to a logic-1, the corresponding bit or bits of ANC ID[7:0] or ANC ID[15:8], respectively are a don’t- care when matching IDs of incoming packets. When ANC MASK[7:0] or ANC MASK[15:8] is set to 00h, the DID, SDID or DBN of incoming packets must match exactly, bit- for-bit, the setting of ANC ID[7:0] or ANC ID[15:8] in the control register for the packets to be loaded into the FIFO. The initial value of ANC MASK[7:0]and ANC MASK[15:8] is FFh. The initial value of ANC ID[7:0]and ANC ID[15:8]is 00h. Bits 7 through 0 of Register ANC 1, ANC ID[7:0], and Register ANC3, ANC MASK[7:0], affect DID[7:0]. BIts 7 through 0 of Register ANC2, ANC ID[15:8], and Register ANC 4, ANC MASK[15:8], affect SDID[7:0] or DBN[7:0]. ANC REGISTER 5 (Address 17h) The FIFO INSERT ENABLEbit enables insertion of ancillary data stored in the FIFO into the serial data stream. Data insertion is enabled when this bit is set to a logic-1. This bit can be used to delay automatic insertion of data into the serial data stream. Setting the FIFO FLUSH STATbit to a logic-1 flushes the FIFO. Data may not be loaded into the FIFO during FIFO FLUSH STATexecution. Similarly, FIFO FLUSH STATmay not be set when data is being input to the FIFO. FIFO FLUSH STAT is automatically reset after this operation is complete. Execution of these FIFO operations requires tog- gling of ACLK. ANC REGISTER 6 (Addresses 18h) The ANC PARITY MASKbit when set disables parity check- ing for the DATA ID (DID) and SECONDARY DATA ID (SDID) or Data Block Number (DBN) in the ANC data packet. When reset, parity checking is enabled, and, if a parity error occurs, the packet will not be loaded. The VANC bit in the control registers, when set to a logic-1, enables insertion of ancillary data during the vertical blank- ing interval. SWITCH POINT REGISTERS 0 THROUGH 3 (Addresses 09h, 0Ah, 19h and 1Ah) The Line[10:0] and Protect[4:0] bits define the vertical switching point line and number of protected lines following the switching point line for fields 0 and 1 (or fields 1 and 2 as these are sometimes referred to) of high-defination formats. The vertical switching point for component digital standard definition formats is defined in SMPTE RP 168-1993. The vertical switching point for high-definition formats has the same basic definition. However, since the vertical switching point lines are not necessarily standardized among the vari- ous high-definition rasters, these registers provide a conve- nient means whereby the vertical switching point line and subsequent protected lines may be specified by the user. The Switch Point registers do not operate for standard defi- nition formats. The Line[10:0] bits of registers Switch Point 0 and 1may be loaded with a line number ranging from 0 to 1023 which then specifies the switching point line for Field 0. The Pro- tect[4:0] bits of register Switch Point 1determine the num- ber of lines from 0 to 15 after the vertical switching point line in which ancillary data may not be inserted. LINE(0) is the LSB and LINE(10) is the MSB for theLine[10:0] bits. Similar ordering holds for the Protect[4:0] bits. The Line[10:0] and Protect[4:0] bits of registers Switch Point 2 and 3perform the same function as explained above for the vertical switching point line for Field 1. FORMAT REGISTERS 0 (Addresses 0Bh) The LMH0030 may be set to process a single video format by writing the appropriate data into the FORMAT 0register. The Format Set[4:0]bits confine the LMH0030 to recognize and process only one of the fourteen specified types of standard or high definition formats. When the LMH0030 is set to process a single format, it will not recognize and therefore will not process other formats that it is capable of recognizing. The Format Set[4:0] bits may not be used to confine device operation to a range of standards. For normal operating situations, it is recommended that the LMH0030 be operated in automatic format detection mode, i.e. that the Format 0 register be set to 00h. The available formats and codes are detailed in Table 4. Generally speaking, the Format Set[4:0] codes indicate or group the formats as follows:Format Set[4]is set for the HD formats and reset for the SD formats. Format Set[3] when set indicates that PAL data is being processed. When reset NTSC data is being processed. Format Set[2:0]correspond to one of the sub-standards given in the table. Note that the LMH0030 makes no distinction in formats resulting from the processing of data at 74.25MHz or 74.176MHz. The HD Only bit when set to a logic-1 locks the LMH0030 into the high definition data range and frequency. In systems designed to handle only high definition signals, enabling HD Only reduces the time required for the LMH0030 to establish frequency lock and determine the HD format being pro- cessed. The SD Only bit when set to a logic-1 locks the LMH0030 into the standard definition data ranges and frequencies. In systems designed to handle only standard definition signals, enabling SD Only reduces the time required for the LMH0030 to establish frequency lock and determine the format being processed. When SD Only and HD Only are set to logic-0, the device operates in SD/HD mode. LMH0030 www.national.com19

TABLE 4. Video Raster Format Parameters

00001 SDTV, 54 SMPTE 344M 60I 525 507/487 3432 2880

00010 SDTV, 36 SMPTE 267M 60I 525 507/487 2288 1920

00011 SDTV, 27 SMPTE 125M 60I 525 507/487 1716 1440

01001 SDTV, 54 ITU-R BT

01010 SDTV, 36 ITU-R BT

01011 SDTV, 27 ITU-R BT

Set[4:0] bits. These formats and codes are given in Table 4. spond with one of the sub-standards given in the table. PAL, 27MHz, 4x3 PLL Pathological. mapped to I/O port bit 6 in the default condition. eters may take the majority of a frame.

Device Operation (Continued) the insertion of transition codes in the chroma and luma data of color bar test patterns where these patterns change from one bar to the next. This filter reduces the magnitude of out-of-band frequency products which can be produced by abrupt transitions in the chroma and luma data when fed to D-to-A converters and picture monitors. The default condi- tion of this bit is reset (off). A method by which the occurrence of pathological data patterns can be prevented has been proposed for SD for- mats. The LMH0030 implements this process for SD for- mats. The Dither Enable and Vertical Dither Enablebits control operation of pseudo-random dithering applied to the two LSBs of the video data. Dithering is applied to active video data when the Dither Enable bit is set. When the Vertical Dither Enable bit is set, dithering is applied to that portion of the video line corresponding to active video for lines in the vertical blanking interval. I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h) The Multi-function I/O Bus Pin Configurationregisters are used to map the bits of the multi-function I/O port to selected bits of the Configuration and Control Registers. Table 6 details the available Configuration and Control register bit functions that may be mapped to the port and their corre- sponding mapping addresses. Pin # SEL[5]in each register indicates whether the port pin is input or output. The port pin will be an input when this bit is set and an output when reset. Input-only functions may not be configured as outputs and vice versa. The remaining lower-order five address bits dis- tinguish the particular function. Example: Program, via the AD port, I/O port bit 0 as output for the CRC Luma Error bit in the control registers. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. 3. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register address. 4. Toggle ACLK. 5. Present 310h to AD[9:0] as the register data, the bit address of the CRC Luma Error bit in the control regis- ters. 6. Toggle ACLK. TEST MODE 0 REGISTER (Address 55h) The four bits of this register are intended for use as test mode functions. They are not normal operating modes. The bits may be set (enabled) or reset (disabled) by writing to the register. Reading this register sets (enables) all bits to their default ON condition. The Scrambler_Enable bit enables operation of the SMPTE scrambler function. This bit is normally ON. The NRZI_Enable bit enables operation of the NRZ-to-NRZI conversion function. This bit is normally ON. The LSB_Clipping bit enables operation of the LSB clipping function. This bit is normally ON. The Sync_Detect_Enable bit enables operation of the TRS detector function. This bit is normally ON. LMH0030 www.national.com21

TABLE 5. Test Pattern Selection Codes

TABLE 5. Test Pattern Selection Codes(Continued)

525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M)

525 Line, 30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M)

525 Line, 30 Frame, 54 MHz (NTSC)

625 Line, 25 Frame, 54 MHz (PAL)

Note:SD BIST patterns are NTSC 4x3 color Bars and PAL 4x3 PLL Pathological. HD BIST patterns are color bars for each format.

TABLE 6. I/O Configuration Register Addresses for Control Register Functions

000001 Output

000010 Output

000011 Output

000100 Output I/O Port Bit 5

Addresses x05h through x0Ch are reserved.

011110 Output

011111 Output

100001 Input

100010 Input

100011 Input

100100 Input

100101 Input

100110 Input

TABLE 6. I/O Configuration Register Addresses for Control Register Functions(Continued)

101010 Input

101100 Input

101101 Input

101111 Input

1V DDPLLD Positive Power Supply Input (2.5V supply, PLL Logic) 2V SSPLLD Negative Power Supply Input (2.5V supply, PLL Logic)

3 IO0 Multi-Function I/O Port

4 IO1 Multi-Function I/O Port

5 DV0 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

6 DV1 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

7 DV2 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

8 DV3 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

9 DV4 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

SSD Negative Power Supply Input (2.5V supply, Digital Logic)

11 DV5 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

12 DV6 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

13 DV7 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

14 DV8 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

15 DV9 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

DDD Positive Power Supply Input (2.5V supply, Digital Logic) 17 V SSD Negative Power Supply Input (2.5V supply, Digital Logic)

18 DV10 Parallel Video Input (HD=Luma)

19 DV11 Parallel Video Input (HD=Luma)

20 DV12 Parallel Video Input (HD=Luma)

21 DV13 Parallel Video Input (HD=Luma)

22 DV14 Parallel Video Input (HD=Luma)

DDIO Positive Power Supply Input (3.3V supply, I/O)

24 DV15 Parallel Video Input (HD=Luma)

25 DV16 Parallel Video Input (HD=Luma)

26 DV17 Parallel Video Input (HD=Luma)

27 DV18 Parallel Video Input (HD=Luma)

28 DV19 Parallel Video Input (HD=Luma)

SSIO Negative Power Supply Input (3.3V supply, I/O)

30 IO2 Multi-Function I/O Port

31 IO3 Multi-Function I/O Port

32 IO4 Multi-Function I/O Port

33 IO5 Multi-Function I/O Port

34 IO6 Multi-Function I/O Port

35 IO7 Multi-Function I/O Port

36 ACLK Ancillary/Control Clock Input

DDD Positive Power Supply Input (2.5V supply, Digital Logic)

38 AD0 Ancillary/Control Data I/O Port

39 AD1 Ancillary/Control Data I/O Port

40 AD2 Ancillary/Control Data I/O Port

41 AD3 Ancillary/Control Data I/O Port

42 AD4 Ancillary/Control Data I/O Port

SSD Negative Power Supply Input (2.5V supply, Digital Logic)

44 AD5 Ancillary/Control Data I/O Port

45 AD6 Ancillary/Control Data I/O Port

46 AD7 Ancillary/Control Data I/O Port

47 AD8 Ancillary/Control Data I/O Port

48 AD9 Ancillary/Control Data I/O Port

49 RD/WR

Ancillary/Control Data Port Read/Write Control Input LMH0030 www.national.com 26

Pin Descriptions (Continued) Pin Name Description

50 ANC/CTRL Ancillary/Control Data Port Function Control Input

51 V DDSD Positive Power Supply Input (3.3V supply, Output Driver) 52 R REFPRE Output Preemphasis Reference Resistor (4.75 K Ω, 1% Nom.) 53 R REFLVL Output Level Reference Resistor (4.75 K Ω, 1% Nom.) 54 V SSSD Negative Power Supply Input (3.3V supply, Output Driver) 55 V SSSD Negative Power Supply Input (3.3V supply, Output Driver)

56 SDO Serial Data True Output

DDLS Positive Power Supply Input (3.3V supply, Level Shift)

58 SDO Serial Data Complement Output

59 V SSLS Negative Power Supply Input (3.3V supply, Level Shift) 60 V DDZ Positive Power Supply Input (2.5V supply, Serializer) 61 V SSPLLA Negative Power Supply Input (2.5V supply, PLL Analog) 62 V DDPLLA Positive Power Supply Input (2.5V supply, PLL Analog)

63 VCLK Video Data Clock Input

64 Reset Manual Reset Input (High True)

Note: All LVCMOS inputs except VCLK and ACLK have internal pull-down devices. LMH0030 www.national.com27

Application Information

Complete details for the SD130ASM evaluation PCB are available on National’s WEB site. This circuit demonstrates the capabilities of the LMH0030 and allows its evaluation in a native configuration. An assembled demonstration board kit, part number SD130EVK, complete with operating in- structions, drawing package and list of materials is available. Contact the Interface Products Group or the Serial Digital Video and Interface Applications Group for ordering informa- tion. Complete circuit board layouts, schematics and other information for the SD130EVK are also available on Nation- al’s WEB site in the application information for this device. For latest product details and availability information, please see: www.national.com/appinfo/interface. PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuit board layout and stack-up for the LMH0030 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic ca- pacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum capaci- tors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the LMH0030 as well as all RF bypass capacitor terminals. Dual vias reduce the intercon- nect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional V SS (ground) plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the V SS power supply plane at fre- quent intervals with vias. Frequent via placement also im- proves signal integrity on signal transmission lines by pro- viding short paths for image currents which reduces signal distortion. The planes should be pulled back from all trans- mission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. The LMH0030 uses two power supply voltages, 2.5 and 3.3 volts. These supplies connect to the device through seven sets of independent power input pins. The function and system supplied through these is given in the Pin Description Table. The power supply voltages normally share a common 0 volt or ground return system. Either a split plane or sepa- rate power planes can be used to supply the positive volt- ages to the device. In especially noisy power supply environments, such as is often the case when using switching power supplies, sepa- rate filtering may be used at the LMH0030’s PLL analog, PLL digital and serial output driver power pins. The LMH0030 was designed for this situation. The digital section, PLL and output driver power supply feeds are independent. See the Pin Description Table and the Connection Diagram for de- tails. Supply filtering may take the form of L-section or pi- section, L-C filters in series with these V DD inputs. Such filters are available in a single package from several manu- facturers. Despite being independent feeds, all device power supplies should be applied simultaneously as from a com- mon source. PROCESSING NON-SUPPORTED AND pSf RASTER FORMATS The number and type of HD raster formats has proliferated greatly since the LMH0030 was designed. Though not spe- cifically capable of fully or automatically processing these new formats, the LMH0030 may still be capable of serializing them. The user is encouraged to experiment with processing of these formats keeping in mind that the LMH0030 has not been tested to handle raster formats other than those de- tailed in Table 4. Therefore, the results from attempts to process non-supported formats is not guaranteed. The fol- lowing guidelines concerning device setup are provided to aid the user in configuring the LMH0030 to attempt limited processing of these other raster formats. In general, the device is configured to defeat its format and TRS detection function and to limit operation to a generic HD format type. (The user should consult Table 4for guidance on the format groups similar to the non-supported one to be processed). Since these newer formats are in the HD realm, the LMH0030 should be configured to operate in HD-ONLY mode by setting bit-5 of the FORMAT 0 register (address 0Bh). Also, the device should be further configured by load- ing the FORMAT SET[4:0] bits of this register with a non- specific HD sub-format code. The complete data word for this HD sub-format code with HD-ONLY bit set is 33Fh (all 10 bits of AD[9:0]). Since this format differs from those in the table, the EAV/SAV indicators are disabled. Without these indicators, line numbering and CRC insertion are disabled and ancillary data insertion will not function. Pre-processing of the parallel data ahead of the LMH0030 will be required to insert CRC data and line numbering. Among the specialized formats are so-called progressive- segmented frame formats (pSf). Refer to SMPTE 274M- 2003, Annex A. These formats are composed of the video lines of progressive scan rasters rearranged in the manner of an interlaced raster. The even numbered lines are ar- ranged to form Field 1 and the odd numbered lines form Field 2. In other respects, the format is identical to the normal interlaced format. The LMH0030 can serialize these pSf formats provided that the lines of the original progressive raster are first rearranged externally to the LMH0030 before being presented to it for processing. LMH0030 www.national.com 28

Physical Dimensions inches (millimeters) unless otherwise noted 64-Pin TQPF Order Number LMH0030VS National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LMH0030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver