LMH0026MH/NOPB

LMH0026 TI1 | Alldatasheet

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www.ti.com SNLS253B –MARCH 2008–REVISED APRIL 2013 LMH0026SDSDIReclockerwithDualDifferentialOutputs Check forSamples: LMH0026 1FEATURES DESCRIPTION The LMH0026 SD SDI Reclockerretimesserialdigital 2• Supports SMPTE 259M (C)SerialDigitalVideo video data conformingto the SMPTE 259M (C)Standard standard.The LMH0026 operatesat the serialdata• Supports 270 Mbps SerialData Rate Operation rate of 270 Mbps and also supports DVB-ASI

• Supports DVB-ASI at270 Mbps operationat270 Mbps.
• Single3.3VSupply Operation The LMH0026 retimestheincomingdatatosuppress accumulatedjitter.The LMH0026 recoverstheserial• 330 mW TypicalPower Consumption data-rateclock and optionallyprovidesit as an• Two Differential,Reclocked Outputs output.The LMH0026 has two differentialserialdata• Choice ofSecond Reclocked Output or Low- outputs;thesecond outputmay be selectedas a low- Jitter,Differential,Data-RateClock Output jitter,data-rateclockoutput.Controlsand indicators are:serialclockor second serialdata outputselect,• Single27 MHz ExternalCrystalor Reference SD indicatoroutput,lockdetectoutput,auto/manualClock Input databypass,and outputmute.The serialdatainputs,• Lock DetectIndicatorOutput outputs,and serialdata-rateclock outputs are
• Output Mute FunctionforData and Clock differentialLVPECL compatible.The CML serialdata and serialdata-rateclockoutputsare suitablefor• Auto/Manual ReclockerBypass driving100Ω differentiallyterminatednetworks.The• DifferentialLVPECL Compatible SerialData controllogic inputs and outputs are LVCMOSInputsand Outputs compatible.
• LVCMOS ControlInputsand IndicatorOutputs The LMH0026 ispowered from a single3.3V supply.• 20-PinHTSSOP Package Power dissipationistypically330 mW. The deviceis
• IndustrialTemperature Range: -40°C to+85°C housed ina 20-pinHTSSOP package.
• FootprintCompatible withtheLMH0046 and LMH0346

APPLICATIONS

• SDTV SerialDigitalVideo Interfacesfor: – DigitalVideo Routers and Switchers – DigitalVideo Processingand Editing Equipment – DVB-ASI Equipment – Video Standards and Format Converters Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2008–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

CONTROL LOGICAUTO BYPASSBYPASS/ O/P MUTE 50 XTAL IN/EXT CLK XTAL OUT LOOP FILTER 1 LOOP FILTER 2 SCO_EN SCO/SDO2 BYPASS SDI SDO VCCO SD VCCO SCO/SDO2 HD/SD CROSSPOINT SWITCH CLC018 8 x 8 CABLE EQUALIZER LMH0074 HD/SD DESERIALIZER LMH0031 CABLE DRIVER LMH0001 SERIAL DATA PARALLEL DATA SD RECLOCKER LMH0026 HD/SD SERIALIZER LMH0030 SD SERIALIZER CLC021A CABLE EQUALIZER LMH0024 SD RECLOCKER LMH0026 SD RECLOCKER LMH0026 SD RECLOCKER LMH0026 SERIAL DATA PARALLEL DATA CABLE DRIVER LMH0001 CABLE DRIVER LMH0001 LMH0026 SNLS253B –MARCH 2008–REVISED APRIL 2013 www.ti.com TYPICAL APPLICATION Block Diagram

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SCO_EN XTAL OUT LOCK DET SCO/SDO2 SCO/SDO2 VCCO VCCO SDO SDO SD LMH0026 www.ti.com SNLS253B –MARCH 2008–REVISED APRIL 2013 CONNECTION DIAGRAM The exposed dieattachpad isthenegativeelectricalterminalforthisdevice.Itmust be connectedtothenegative power supplyvoltage. Figure1. 20-PinHTSSOP PIN DESCRIPTIONS Pin Name Description 1 LF1 Loop Filter. 2 LF2 Loop Filter. 3 NC No Connect.Not bonded internally. 4 RSVD Reserved.Do notconnectorconnecttoground. 5 SDI Data Inputtrue. 6 SDI Data Inputcomplement. 7 VCC Positivepower supplyinput. Bypass/AutoBypass mode select.Bypasses reclockingwhen high.Thispinhas an internal 8 BYPASS/ AUTO BYPASS pulldown. Data and ClockOutputMute input.Mutes theoutputwhen low.Thispinhas an internal 9 OUTPUT MUTE pullup. 10 XTAL IN/EXT CLK CrystalorExternalOscillatorinput. 11 XTAL OUT CrystalOscillatoroutput. 12 LOCK DETECT PLL Lock Detectoutput(activehigh). 13 SCO/SDO2 SerialClockorSerialData Output2 complement. 14 SCO/SDO2 SerialClockorSerialData Output2 true. 15 VCCO Positivepower supplyinput(OutputDriver). 16 SDO Data Outputcomplement. 17 SDO Data Outputtrue. 18 VCCO Positivepower supplyinput(outputdriver). 19 SD SD indicatoroutput.Outputishighwhen lockedto270 Mbps. SerialClockorSerialData 2 Outputselect.Setssecond outputtooutputtheclockwhen 20 SCO_EN highand thedatawhen low.Thispinhas an internalpulldown. DAP VEE Connectexposed DAP tonegativepower supply(ground). Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMH0026

SNLS253B –MARCH 2008–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VCC –VEE ) 4.0V LogicSupplyVoltage(Vi) VEE −0.15Vto VCC +0.15V LogicInputCurrent(singleinput): Vi= VEE −0.15V −5 mA Vi= VCC +0.15V +5 mA LogicOutputVoltage(Vo) VEE −0.15Vto VCC +0.15V LogicOutputSource/SinkCurrent ±8 mA SerialData InputVoltage(VSDI) VCC toVCC −2.0V SerialData OutputSinkCurrent(ISDO ) 24 mA Package ThermalResistance,HTSSOP θJA 26.6°C/W θJC 2.4°C/W StorageTemp. Range −65°C to+150°C JunctionTemperature +150°C Lead Temperature(Soldering4 Sec) +260°C (Pb-free) ESD Rating(HBM) 7 kV ESD Rating(MM) 350V ESD Rating(CDM) 1250V (1) “AbsoluteMaximum Ratings”arethoseparametervaluesbeyond whichthelifeand operationofthedevicecannotbe ensured.The statinghereinofthesemaximums shallnotbe construedtoimplythatthedevicecan orshouldbe operatedatorbeyond thesevalues. DC ELECTRICAL CHARACTERISTICS and AC ELECTRICAL CHARACTERISTICS specifyacceptabledeviceoperatingconditions. (2) Itisanticipatedthatthisdevicewillnot be offeredina militaryqualifiedversion.IfMilitary/Aerospacespecifieddevicesare required,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. RECOMMENDED OPERATING CONDITIONS SupplyVoltage(VCC –VEE ) 3.3V±5% LogicInputVoltage VEE toVCC DifferentialSerialInputVoltage 800 mV ±10% SerialData orClockOutputSink Current(ISO ) 16 mA max. OperatingFreeAirTemperature(TA) −40°C to+85°C DC ELECTRICAL CHARACTERISTICS Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified.(1)(2) Symbol Parameter Conditions Reference Min Typ Max Units VIH InputVoltageHighLevel Logiclevelinputs 2 VCC V VIL InputVoltageLow Level VEE 0.8 V IIH InputCurrentHighLevel VIH = VCC 47 65 µA IIL InputCurrentLow Level VIL= VEE −18 −25 µA VOH OutputVoltageHighLevel IOH = −2 mA Alllogiclevel 2 V outputsVOL OutputVoltageLow Level IOL = +2 mA VEE + 0.6 V VSDID SerialInputVoltage, SDI 200 1600 mV P-PDifferential VCMI InputCommon Mode VSDID = 200 mV VEE +1.2 VCC −0.2 VVoltage (1) Currentflowintodevicepinsisdefinedas positive.Currentflowoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedto VEE (equaltozerovolts). (2) Typicalvaluesarestatedfor:VCC = +3.3V,TA = +25°C.

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www.ti.com SNLS253B –MARCH 2008–REVISED APRIL 2013 DC ELECTRICAL CHARACTERISTICS (continued) Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified.(1)(2) Symbol Parameter Conditions Reference Min Typ Max Units VSDOD SerialOutputVoltage, 100Ω differentialload SDO, SCO 720 800 880 mV P-PDifferential VCMO OutputCommon Mode 100Ω differentialload VCC − VVoltage VSDOD ICC Power SupplyCurrent, 270 Mbps 100 mA3.3Vsupply,Total AC ELECTRICAL CHARACTERISTICS Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified.(1) Symbol Parameter Conditions Reference Min Typ Max Units BR SD SerialData Rate SMPTE 259M-C SDI,SDO 270 Mbps TOL JIT SerialInputJitter 270 Mbps, SDI >6 UIP-PTolerance (2)(3)(4) TOL JIT SerialInputJitter 270 Mbps, (2)(3)(5) >0.6 UIP-PTolerance tJIT SerialData OutputJitter 270 Mbps, (3)(6) SDO 0.02 0.08 UIP-P BW LOOP Loop Bandwidth 270 Mbps, 300 kHz<0.1dBPeaking FCO SerialClockOutput 270 Mbps datarate SCO 270 MHzFrequency tJIT SerialClockOutputJitter 2 3 psRMS SerialClockOutput SDO, SCO Alignmentwithrespectto 40 60 % Data Interval SerialClockOutputDuty SCO 45 55 %Cycle TACQ AcquisitionTime (7)(8)15 ms tr,tf Inputrise/falltime 10% –90% Logicinputs 1.5 3 ns tr,tf Inputrise/falltime 20% –80% SDI 1500 ps tr,tf Outputrise/falltime 10% –90% Logicoutputs 1.5 3 ns tr,tf Outputrise/falltime 20% –80%, (9) SDO, SCO 90 130 ps FREF ReferenceClock 27 MHzFrequency FTOL ReferenceClock ±50 ppmFrequencyTolerance (1) Typicalvaluesarestatedfor:VCC = +3.3V,TA = +25°C. (2) Peak-to-peakamplitudewithsinusoidalmodulationperSMPTE RP 184-1996paragraph4.1.The testdatasignalshallbe colorbars. (3) Thisparameterisensuredby characterizationovervoltageand temperaturelimits. (4) Referto“A1”inFigure1 ofSMPTE RP 184-1996. (5) Referto“A2”inFigure1 ofSMPTE RP 184-1996. (6) SerialData OutputJitteristotaloutputjitterwith0.2UIP-P inputjitter. (7) Specificationisensuredby design. (8) Measured fromfirstSDI transitionuntilLock Detect(LD)outputgoes high(true). (9) R L = 100Ω differential. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMH0026

2 k: 80 k: 1 pF 20 k: VCC 2 k: LMH0026 SNLS253B –MARCH 2008–REVISED APRIL 2013 www.ti.com DEVICE DESCRIPTION The LMH0026 SD SDI Reclockerisused in many typesof digitalvideosignalprocessingequipment.The LMH0026 supportstheSMPTE 259M (C)serialdigitalvideostandard,witha correspondingserialdatarateof 270 Mbps. DVB-ASI data at 270 Mbps may alsobe retimed.The LMH0026 retimesthe serialdata stream to suppressaccumulatedjitter.Itprovidestwo low-jitter,differential,serialdataoutputs.The second outputmay be selectedtooutputeitherserialdataora low-jitterserialdata-rateclock.Controlsand indicatorsare:serialdata- rateclockorsecond serialdataoutputselect,SD indicatoroutput,lockdetectoutput,auto/manualdatabypass, and outputmute. SerialdatainputsareCML and LVPECL compatible.Serialdataand data-rateclockoutputsaredifferentialCML and produceLVPECL compatiblelevels.The outputbufferdesigncan driveAC orDC-coupled,terminated100Ω differentialloads.The differentialoutputlevelis800 mV P-P ±10% into100Ω AC orDC-coupleddifferentialloads. Logicinputsand outputsareLVCMOS compatible. The devicepackage is an HTSSOP-20 withan exposed die attachpad. The exposed die attachpad is electricallyconnectedtodeviceground(VEE )and isthenegativeelectricalterminalforthedevice.Thisterminal must be connectedtothenegativepower supplyorcircuitground. SerialData Inputs,SerialData and Clock Outputs SERIAL DATA INPUT AND OUTPUTS The differentialserialdata input,SDI, accepts270 Mbps serialdigitalvideo data.The serialdata inputis differentialLVPECL compatible.The inputisintendedto be DC interfacedto devicessuch as the LMH0074 adaptivecableequalizer.The inputisnot internallyterminatedor biased.The inputmay be AC-coupledifa suitableinputbiasvoltageisprovided.Figure2 shows theequivalentinputcircuitforSDI and SDI. The LMH0026 has two,retimed,differential,serialdata outputs,SDO and SCO/SDO2. These outputsprovide lowjitter,differential,retimeddatatodevicessuch as theLMH0001 orLMH0002 cabledriver.OutputSCO/SDO2 ismultiplexedand can provideeithera second serialdata outputor a serialdata-rateclockoutput.Figure3 shows theequivalentoutputcircuitforSDO, SDO, SCO/SDO2, and SCO/SDO2. The SCO_EN inputcontrolstheoperatingmode fortheSCO/SDO2 output.When theSCO_EN inputishighthe SCO/SDO2 outputprovidesa serialdata-rateclock.When SCO_EN islow,the SCO/SDO2 outputprovides retimedserialdata. Both differentialserialdataoutputs,SDO and SCO/SDO2, aremuted when theOUTPUT MUTE inputisa logic low level.SCO/SDO2 alsomutes when theBypass mode isactivatedwhen thisoutputisoperatingas theserial clockoutput.When muted,SDO and SDO (orSDO2 and SDO2) willassume oppositedifferentialoutputlevels. The CML serialdataoutputsaredifferentialLVPECL compatible.These outputshave internal50Ω pull-upsand are suitablefordrivingAC or DC-coupled,100Ω center-tapped,AC grounded or 100Ω un-center-tapped, differentiallyterminatednetworks. Figure2. EquivalentSDI inputCircuit(SDI,SDI)

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50: SDO, SCO/SDO2 VCC VCC 50: VCC SDO, SCO/SDO2 LMH0026 www.ti.com SNLS253B –MARCH 2008–REVISED APRIL 2013 Figure3. EquivalentSDO Output Circuit(SDO, SDO, SCO/SDO2, SCO/SDO2) SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT The SerialData Clock/SerialData 2 Outputiscontrolledby the SCO_EN inputand provideseithera second retimedserialdata outputor a low jitterdifferentialclockoutputappropriateto the serialdata ratebeing processed.When operatingas a serialclockoutput,the risingedge of the clockwillbe positionedwithinthe correspondingserialdatabitintervalwithin10% ofthecenterofthedatainterval. DifferentialoutputSCO/SDO2 functionsas thesecond serialdataoutputwhen theSCO_EN inputisa logic-low level.Thisoutputfunctionsas theserialdata-rateclockoutputwhen theSCO_EN inputisa logic-highlevel.The SCO_EN inputhas an internalpull-downdeviceand thedefaultstateofSCO_EN islow (serialdataoutput2 enabled).SCO/SDO2 ismuted when theOUTPUT MUTE inputisa logiclow level.When theBypass mode is activatedand thisoutputisfunctioningas a serialclockoutput,theoutputwillalsobe muted.Ifan unsupported datarateisused whileinAuto Bypass mode withthisoutputfunctioningas a serialclockoutput,theoutputis invalid. ControlInputsand IndicatorOutputs LOCK DETECT The Lock Detect(LD)output,when high,indicatesthatdataisbeingreceivedand thePLL islocked.LD may be connected to the OUTPUT MUTE inputto mute the data and clockoutputswhen no data signalis being received.Note thatwhen theBypass/AutoBypass inputissethigh,Lock Detectwillremainlow.See Table1. OUTPUT MUTE The OUTPUT MUTE input,when low,mutes the serialdata and clockoutputs.Itmay be connectedto Lock Detectorexternallydriventomute orun-mutetheoutputs.IfOUTPUT MUTE isconnectedtoLD, thenthedata and clockoutputsare muted when the PLL isnot locked.This functionoverridesthe Bypass function:see Table1.OUTPUT MUTE has an internalpull-updevicetoenabletheoutputby default. BYPASS/ AUTO BYPASS The Bypass/Auto Bypass input,when high,forcesthedevicetooutputthedatawithoutreclockingit.When this inputis low,the deviceautomaticallybypasses the reclockingfunctionwhen the deviceis in an unlocked conditionorthedetecteddatarateisa ratewhichthedevicedoes notsupport.Note thatwhen theBypass/Auto Bypass inputissethigh,Lock Detectwillremainlow.See Table1.BYPASS/ AUTO BYPASS has an internalpull- down device. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMH0026

NO DATA 270 MBPS DATA NO DATA TACQ = Acquisition Time, defined in the AC Electrical Characteristics Table T1 = Time from Lock Detect assertion or deassertion until SD output is valid, typically 37 ns (one 27 MHz clock period) T2 = Time from SDI input change until Lock Detect de-assertion, 1 ms maximum. SD output is not valid during this time. TACQ T1 T1 TACQ T1T1 LMH0026 SNLS253B –MARCH 2008–REVISED APRIL 2013 www.ti.com Table1.ControlFunctionality LOCK DETECT OUTPUT MUTE BYPASS/ AUTO BYPASS DEVICE STATUS 0 1 X PLL unlocked,reclockerbypassed 1 1 0 PLL lockedtosupporteddatarate,reclockernotbypassed X 0 X Outputsmuted

0 LOCK DETECT X Outputsmuted

1 LOCK DETECT 0 PLL lockedtosupporteddatarate,reclockernotbypassed

The SD outputindicatesthattheLMH0026 islockedand processingSD datarates.Itmay be used tocontrol anotherdevicesuch as theLMH0002 cabledriver.When thisoutputishighitindicatesthatthedatarateis270 Mbps. The SD outputisa registeredfunctionand isonlyvalidwhen the PLL islockedand the Lock Detect outputishigh.When thePLL isnotlocked(theLock Detectoutputislow),theSD outputdefaultstolow.The SD outputisundefinedfora shorttimeafterlockdetectassertionorde-assertiondue toa datachange on SDI.See Figure4 fora timingdiagramshowingtherelationshipbetween SDI,Lock Detect,and SD. Figure4. SDI,Lock Detect,and SD Timing SCO_EN InputSCO_EN enablestheSCO/SDO2 differentialoutputtofunctioneitheras a serialdata-rateclockorsecond serialdata output.SCO/SDO2 functionsas a serialdata-rateclockwhen SCO_EN ishigh.This pin has an internalpull-downdevice.The defaultstate(low)enablestheSCO/SDO2 outputas a second serialdataoutput. CRYSTAL OR EXTERNAL CLOCK REFERENCE The LMH0026 uses a 27 MHz crystalor externalclocksignalas a timingreferenceinput.A 27 MHz parallel resonantcrystaland load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins. Alternatively,a 27 MHz LVCMOS compatibleclocksignalmay be inputtoXTAL IN/EXT CLK. Parametersfora suitablecrystalaregiveninTable2.

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SCO_EN XTAL OUT LOCK DET SCO/SDO2 SCO/SDO2 VCCO VCCO SDO SDOCoaxial Cable 75: 37.4: 75: 6.8 nH LMH0074 Adaptive Cable Equalizer SDI SDO SDI AEC+ AEC- SDO 100: 56 nF

27 MHz

75: LMH0001 Cable Driver SDO SDI R REF SDO SDI 100: 75: 75: 75: 75: 750: A B Additional Outputs A B 75: LOCK DET OP MUTE BP/AUTO-BP VCC VCC +3.3V +3.3V SCO_EN Coaxial Cable Coaxial Cable 1.0 PF 1.0 PF 1.0 PF 4.7 PF 4.7 PF 5.6 nH 5.6 nH SD SD LMH0026 www.ti.com SNLS253B –MARCH 2008–REVISED APRIL 2013 Table2.CrystalParameters Parameter Value Frequency 27 MHz FrequencyStability ±50 ppm @ recommended drivelevel OperatingMode Fundamentalmode, ParallelResonant Load Capacitance 20 pF ShuntCapacitance 7 pF SeriesResistance 40Ω max. Recommended DriveLevel 100 µW Maximum DriveLevel 500 µW OperatingTemperatureRange −10°C to+60°C

APPLICATION INFORMATION

Figure5 shows an applicationcircuitfortheLMH0026 alongwiththeLMH0074 SMPTE 259M /344M Adaptive CableEqualizerand LMH0001 SMPTE 259M /344M CableDriver. Figure5. ApplicationCircuit Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMH0026

SNLS253B –MARCH 2008–REVISED APRIL 2013 www.ti.com The LMH0026 inputsareLVPECL compatible.The LMH0026 has a wide inputcommon mode rangeand inmost cases theinputshouldbe DC coupled.For DC coupling,theinputsmust be keptwithinthecommon mode range specifiedin DC ELECTRICAL CHARACTERISTICS . Figure5 shows an example of a DC coupledinterface between the LMH0074 cableequalizerand the LMH0026. The LMH0074 outputcommon mode voltageand voltageswing are withintherange oftheinputcommon mode voltageand voltageswing oftheLMH0026. All thatisrequiredisa 100Ω differentialterminationas shown. The resistorshouldbe placedas closeto the LMH0026 inputas possible.Ifdesired,thisnetworkmay be terminatedwithtwo 50Ω resistersand a centertap capacitortogroundinplaceofthesingle100Ω resistor. The LMH0026 outputsare LVPECL compatible.SDO isthe primarydata outputand SCO/SDO2 isa second outputthatmay be setas theserialclockora second dataoutput.Bothoutputsarealwaysactive.The LMH0026 outputshouldbe DC coupledtotheinputofthereceivingdeviceas longas thecommon mode rangesofboth devicesare compatible.Figure5 shows an example of a DC coupledinterfacebetween the LMH0026 and LMH0001 cabledriver.Allthatisrequiredisa 100Ω differentialterminationas shown. The resistorshouldbe placedas closeto the LMH0001 inputas possible.Ifdesired,thisnetworkmay be terminatedwithtwo 50Ω resistersand a centertapcapacitortogroundinplaceofthesingle100Ω resistor. The externalloopfiltercapacitor(betweenLF1 and LF2) shouldbe 56 nF.Thisistheonlysupportedvalue;the loopfiltercapacitorshouldnotbe changed. BYPASS/ AUTO BYPASS has an internalpulldownto enableAuto Bypass mode by default.Thispinmay be pulledhightoforcetheLMH0026 tobypassalldata. OUTPUT MUTE has an internalpulluptoenabletheoutputsby default.Thispinmay be pulledlow tomute the outputs. The XTAL IN/EXT CLK and XTAL OUT pinsareshown witha 27 MHz crystaland theproperloading.The crystal shouldmatch theparametersdescribedinTable2.Alternately,a 27MHz LVCMOS compatibleclocksignalmay be inputtoXTAL IN/EXT CLK. The activehighLOCK DETECT outputprovidesan indicationthatproperdataisbeingreceivedand thePLL is locked. The SD outputmay be used todrivetheSD/HD pinofan SDI cabledriver(suchas theLMH0002) inorderto properlysetthe cabledriver’s edge rateforSMPTE compliance.Itdefaultsto low when the LMH0026 isnot locked. SCO_EN has an internalpulldowntosetthesecond output(SCO/SDO2) tooutputdata.Thispinmay be pulled hightosetthesecond outputas a serialclock. The ground connectionforthe LMH0026 isthroughthe largeexposed DAP. The DAP must be connectedto groundforproperoperationoftheLMH0026.

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www.ti.com SNLS253B –MARCH 2008–REVISED APRIL 2013

REVISION HISTORY

Changes from RevisionA (April2013)toRevisionB Page Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMH0026

www.ti.com 8-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMH0026MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L026 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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