Driver IC

LMG2652RFBR

Texas Instruments

LMG2652 650V 140mΩ GaN Half Bridge With Integrated Driver and Current Sense Emulation JANUARY 2025

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LMG2652 650V 140mΩ GaN Half Bridge With Integrated Driver and Current Sense Emulation

1 Features

650V GaN power-FET half bridge
140mΩ low-side and high-side GaN FETs
Integrated gate drivers with <100ns low propagation delays
Current-sense emulation with high-bandwidth and high accuracy
Low-side referenced (INH) and high-side referenced (GDH) high-side gate drive pins
Low-side (INL) / high-side (INH) gate-drive interlock
High-side (INH) gate-drive signal level shifter
Smart-switched bootstrap diode function
High-side start up: <8µs
Low-side / high-side cycle-by-cycle overcurrent protection
Overtemperature protection
AUX idle quiescent current: 250μA
AUX standby quiescent current: 50μA
BST idle quiescent current: 70μA
8mm × 6mm QFN package with dual thermal pads

2 Applications

AC/DC adapters and chargers
AC/DC USB wall outlet power supplies
AC/DC auxiliary power supplies
Mobile wall charger design
USB wall power outlet Level Shifter Tx Level Shifter Rx Driver Driver Control Current Emulation INL CS INH AGND SL RDRVL EN AUX SW DH RDRVH BST GDH LS GaN FET HS GaN FET Simplified Block Diagram

3 Description

The LMG2652 is a 650V 140mΩ GaN power-FET half bridge. The LMG2652 simplifies design, reduces component count, and reduces board space by integrating half-bridge power FETs, gate drivers, bootstrap diode, and high-side gate-drive level shifter in a 6mm by 8mm QFN package. The low-side current-sense emulation reduces power dissipation compared to the traditional current-sense resistor and allows the low-side thermal pad to be connected to the cooling PCB power ground. The high-side GaN power FET can be controlled with either the low-side referenced gate-drive pin (INH) or the high-side referenced gate-drive pin (GDH). The high-side gate-drive signal level shifter reliably transmits the INH pin signal to the high-side gate driver in challenging power switching environments. The smart-switched GaN bootstrap FET has no diode forward-voltage drop, avoids overcharging the high- side supply, and has zero reverse-recovery charge. The LMG2652 supports converter light-load efficiency requirements and burst-mode operation with low quiescent currents and fast start-up times. Protection features include FET turn-on interlock, under-voltage lockout (UVLO), cycle-by-cycle current limit, and over- temperature shut down.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LMG2652 RFB (VQFN, 19) 8.00mm × 6.00mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Package View LMG2652 SNOSDL5 – JANUARY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

Figure 4-1. RFB Package, 19-Pin VQFN (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. NC 1, 6, 9, 11 NC Used to anchor QFN package to PCB. Pin must be soldered to a PCB landing pad. The PCB landing pad is non-solder mask defined pad and must not be physically connected to any other metal on the PCB. Pin not connected internally. INH 2 I High-side gate-drive control input. Referenced to AGND. Signal is level shifted internally to the high-side GaN FET driver. There is a forward biased ESD diode from INH to AUX so avoid driving INH higher than AUX. Short this pin to AGND if GDH pin function is used. INL 3 I Low-side gate-drive control input. Referenced to AGND. There is a forward biased ESD diode from INL to AUX so avoid driving INL higher than AUX. CS 4 O Current-sense emulation output. Outputs scaled replica of the GaN FET current. Feed output current into a resistor to create a current sense voltage signal. Reference the resistor to the power supply controller IC local ground. This function replaces the external current sense resistor that is used in series with the low-side FET source. SL 5, 7 P Low-side GaN FET source. Low-side thermal pad. Internally connected to AGND. DH 8 P High-side GaN FET drain. SW 10, 15 P GaN FET half-bridge switch node between the high-side GaN FET source and low-side GaN FET drain. High-side thermal pad. GDH 12 I High-side gate-drive control input. Referenced to SW. Signal is connected directly to the high-side GaN FET driver. There is a forward biased ESD diode from GDH to BST so avoid driving GDH higher than BST. Short this pin to SW if INH pin function is used. RDRVH 13 I Short to SW. www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMG2652

Table 4-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. BST 14 P Bootstrap voltage rail. High-side supply voltage. The bootstrap diode function between AUX and BST is internally provided. Connect an appropriately sized bootstrap capacitor between BST and SW. RDRVL 16 I Short to AGND. AGND 17 G Low-side analog ground. Internally connected to SL. AUX 18 P Auxiliary voltage rail. Low-side supply voltage. Connect a local bypass capacitor between AUX and AGND. EN 19 I Enable. Used to toggle between active and standby modes. The standby mode has reduced quiescent current to support converter light load efficiency targets. There is a forward biased ESD diode from EN to AUX so avoid driving EN higher than AUX. (1) I = input, O = output, I/O = input or output, G = ground, P = power, NC = no connect LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

Unless otherwise noted: voltages are respect to AGND(1) MIN MAX UNIT VDS(ls) Low-side drain-source (SW to SL) voltage, FET off 650 V VDS(surge)(ls) Low-side drain-source (SW to SL) voltage, surge condition, FET off (2) 720 V VDS(tr)(surge) (ls) Low-side drain-source (SW to SL) transient ringing peak voltage, surge condition, FET off (2) 800 V VDS(hs) High-side drain source (DH to SW) voltage, FET off 650 V VDS(surge)(hs) High-side drain-source (DH to SW) voltage, surge condition, FET off (2) 720 V VDS(tr)(surge) (hs) High-side drain-source (DH to SW) transient ringing peak voltage, surge condition, FET off (2) 800 V Pin voltage to AGND AUX –0.3 30 V EN, INL, INH –0.3 VAUX + 0.3 V CS –0.3 5.5 V RDRVL –0.3 4 V Pin voltage to SW BST –0.3 30 V RDRVH –0.3 4 V GDH –0.3 VBST_SW + 0.3 V ID(cnts)(ls) Low-side drain (SW to SL) continuous current, FET on –7.4 Internally limited A ID(pulse)(oc)(ls) Low-side drain (SW to SL) pulsed current during overcurrent response time(3) 18 A IS(cnts)(ls) Low-side source (SL to SW) continuous current, FET off 7.4 A ID(cnts)(hs) High-side drain (DH to SW) continuous current, FET on –7.4 Internally limited A ID(pulse)(oc) (hs) High-side drain (DH to SW) pulsed current during overcurrent response time(3) 18 A IS(cnts)(hs) High-side source (SW to DH) continuous current, FET off 7.4 A Positive sink current CS 10 mA TJ Operating junction temperature –40 150 °C Tstg Storage temperature –40 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) See GaN Power FET Switching Capability for more information on the GaN power FET switching capability. (3) GaN power FET may self-limit below this value if it enters saturation.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Pins 8 through 15 ±1000 V Pins 1 through 7, Pins 16 through 19 ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 V (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMG2652

5.3 Recommended Operating Conditions

Unless otherwise noted: voltages are respect to AGND MIN NOM MAX UNIT Supply voltage AUX 10 26 V Supply voltage to SW BST 7.5 26 V Input voltage EN, INL, INH 0 VAUX V Input voltage to SW GDH 0 VBST_SW V VIH High-level input voltage EN, INL, INH, GDH to SW 2.5 V VIL Low-level input voltage 0.6 V ID(cnts)(ls) Low-side drain (SW to SL) continuous current, FET on –6.1 6.1 A ID(cnts)(hs) High-side drain (DH to SW) continuous current, FET on –6.1 6.1 A CAUX AUX to AGND capacitance from external bypass capacitor 3 x CBST µF CBST_SW BST to SW capacitance from external bypass capacitor 0.010 µF

5.4 Thermal Information

THERMAL METRIC(1) LMG2652 UNITRFB (VQFN)

19 PINS

RθJA Junction-to-ambient thermal resistance 22.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.20 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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5.5 Electrical Characteristics

1) Symbol definitions: VDS(ls) = SW to SL voltage; IDS(ls) = SW to SL current; VDS(hs) = DH to SW voltage; ID(hs) = DH to SW current; ISW = SW point current into device; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; VDS(ls) = 520V; VDS(hs) = 520V; 10V ≤ VAUX ≤ 26V; 7.5V ≤ VBST_SW ≤ 26V; VEN = 5V; VINL = 0V; VINH = 0V; VGDH_SW = 0V; RCS = 100Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW-SIDE GAN POWER FET RDS(on)(ls) Drain-source (SW to SL) on resistance VINL = 5V, ID(ls) = 3.5A, TJ = 25°C 140 mΩ VINL = 5V, ID(ls) = 3.5A, TJ = 125°C 255 VSD(ls) Source-drain (SL to SW) third-quadrant voltage SL to SW current = 0.35A 1.9 V SL to SW current = 3.5A 2.6 IDSS(ls) Drain (SW to SL) leakage current VDS(hs) = 0V, VDS(ls) = 650V, TJ = 25°C 2.3 µA VDS(hs) = 0V, VDS(ls) = 650V, TJ = 125°C 11.5 QOSS(ls) Output (SW to SL) charge VDS(hs) = 0V, VDS(ls) = 400V 21.8 nC COSS(ls) Output (SW to SL) capacitance 34.2 pF EOSS(ls) Output (SW to SL) capacitance stored energy 3.0 µJ COSS,er(ls) Energy related effective output (SW to SL) capacitance 36.7 pF COSS,tr(ls) Time related effective output (SW to SL) capacitance VDS(hs) = 0V, VDS(ls) = 0V to 400V 54.5 pF QRR(ls) Reverse recovery charge 0 nC HIGH-SIDE GAN POWER FET RDS(on) (hs) Drain-source (DH to SW) on resistance VINH = 5V, ID(hs) = 3.5A, TJ = 25°C 140 mΩ VINH = 5V, ID(hs) = 3.5A, TJ = 125°C 255 VSD(hs) Source-drain (SW to DH) third-quadrant voltage SW to DH current = 0.35A 1.9 V SW to DH current = 3.5A 2.6 IDSS(hs) Drain (DH to SW) leakage current VDS(ls) = 0V, VDS(hs) = 650V, TJ = 25°C 2.3 µA VDS(ls) = 0V, VDS(hs) = 650V, TJ = 125°C 11.5 QOSS(hs) Output (DH to SW) charge VDS(ls) = 0V, VDS(hs) = 400V 21.8 nC COSS(hs) Output (DH to SW) capacitance 34.2 pF EOSS(hs) Output (DH to SW) capacitance stored energy 3.0 µJ COSS,er(hs Energy related effective output (DH to SW) capacitance 36.7 pF COSS,tr(hs Time related effective output (DH to SW) capacitance VDS(ls) = 0V, VDS(hs) = 0V to 400V 54.5 pF QRR(hs) Reverse recovery charge 0 nC LOW-SIDE OVERCURRENT PROTECTION IT(OC)(ls) Overcurrent fault – threshold current 5.6 6.5 7.4 A HIGH-SIDE OVERCURRENT PROTECTION IT(OC)(hs) Overcurrent fault – threshold current 5.6 6.5 7.4 A BOOTSTRAP RECTIFIER RDS(on) AUX to BST on resistance VINL = 5V, VAUX_BST = 1V, TJ = 25°C 7 Ω VINL = 5V, VAUX_BST = 1V, TJ = 125°C 12 AUX to BST current limit VINL = 5V, VAUX_BST = 7V 210 240 270 mA BST to AUX reverse current blocking threshold VINL = 5V 15 mA CS www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMG2652

5.5 Electrical Characteristics (continued)

1) Symbol definitions: VDS(ls) = SW to SL voltage; IDS(ls) = SW to SL current; VDS(hs) = DH to SW voltage; ID(hs) = DH to SW current; ISW = SW point current into device; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; VDS(ls) = 520V; VDS(hs) = 520V; 10V ≤ VAUX ≤ 26V; 7.5V ≤ VBST_SW ≤ 26V; VEN = 5V; VINL = 0V; VINH = 0V; VGDH_SW = 0V; RCS = 100Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Current sense gain (ICS(src) / ID(LS)) VINL = 5V, 0V ≤ VCS ≤ 2V, 0A ≤ ID(ls)< IT(OC)(ls) 0.901 mA/A Current sense input offset current VINL = 5V, 0V ≤ VCS ≤ 2V, 0A ≤ ID(ls)< IT(OC)(ls) –56 56 mA Initial held output after overcurrent fault occurs while INL remains high VINL = 5V, 0V ≤ VCS ≤ 2V 7 mA ICS(src) (OC)(final) Final held output after overcurrent fault occurs while INL remains high VINL = 5V, 0V ≤ VCS ≤ 2V 10 12 15.5 mA Output clamp voltage VINL = 5V, ID(ls) = 5.8A, CS sinking 5mA from external source 2.6 V EN, INL, INH to AGND; GDH to SW VIT+ Positive-going input threshold voltage 1.7 2.45 V VIT– Negative-going input threshold voltage 0.7 1.3 V Input threshold voltage hysteresis 1 V Pull-down input resistance 0V ≤ VPIN ≤ 3V 200 400 600 kΩ Pull-down input current 10V ≤ VPIN ≤ 26V; VAUX = 26V 10 µA OVERTEMPERATURE PROTECTION Temperature fault – postive-going threshold temperature 165 °C Temperature fault – negative-going threshold temperature 150 °C Temperature fault – threshold temperature hysteresis 15 °C AUX VAUX,T+ (UVLO) UVLO – positive-going threshold voltage 8.9 9.3 9.7 V UVLO – negative-going threshold voltage 8.6 9.0 9.5 V UVLO – threshold voltage hysteresis 250 mV Standby quiescent current VEN = 0V 50 110 µA Quiescent current 250 400 µA VINL = 5V, ID(ls) = 0A 1000 Operating current VINL = 0V or 5V, VDS(ls) = 0V, ID(ls) = 0A, fINL = 500kHz 3.3 mA BST VBST_SW, T+(UVLO) VBST_SW UVLO for FET to turn on – positive-going threshold voltage 6.7 7 7.3 V VBST_SW UVLO for FET to stay on– negative-going threshold voltage 4.8 5.1 5.4 V Quiescent current 70 120 µAVINH = 5V, ID(hs) = 0A 660 VGDH_SW = 5V, ID(hs) = 0A 660 Operating current VINH = 0V or 5V, VDS(hs) = 0V, IDS(hs) = 0A; fINH = 500kHz 2.2 mA VGDH_SW = 0V or 5V, VDS(hs) = 0V, IDS(hs) = 0A; fGDH_SW = 500kHz 2.2 LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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5.6 Switching Characteristics

80 V/ns

td(on) (Idrain) (hs,INH) Drain current turn-on delay time From VINH > VINH,IT+ to ID(hs) > 50mA, VBUS = 400V, ISW = –1.8A, see GaN Power FET Switching Parameters 45 ns td(on) (Idrain) (hs,GDH) Drain current turn-on delay time From VGDH > VGDH,IT+ to ID(hs) > 50mA, VBUS = 400V, ISW = –1.8A, see GaN Power FET Switching Parameters 40 ns td(off) (hs,INH) Turn-off delay time From VINH < VINH,IT– to VDS(hs) > 80V, VBUS = 400V, ISW = –1.8A, see GaN Power FET Switching Parameters 55 ns td(off) (hs,GDH) Turn-off delay time From VGDH < VGDH,IT– to VDS(hs) > 80V, VBUS = 400V, ISW = –1.8A, see GaN Power FET Switching Parameters 45 ns tf(off)(hs) Turn-off fall time From VDS(hs) > 80V to VDS(hs) > 320V, VBUS = 400V, ISW = –1.8A, see GaN Power FET Switching Parameters 23 ns Turn-on slew rate From VDS(hs) < 320V to VDS(hs) < 80V, TJ = 25℃, VBUS = 400V, ISW = –1.8A, see GaN Power FET Switching Parameters From ICS(src) > 0.1 × ICS(src)(final) to ICS(src) > 0.9 × ICS(src)(final), 0V ≤ VCS ≤ 2V, Low- side enabled into a 1.8A load 30 ns EN EN wake-up time From VEN > VIT+ to ID(ls) > 10mA, VINL = 5V 1.5 µs BST Start-up time from deep BST to SW discharge From VBST_SW > VBST_SW,T+(UVLO) to high- side reacts to INH or GDH high level with VBST_SW rising from 0V to 10V in 1µs 5 µs Start-up time from shallow BST to SW discharge From VBST_SW > VBST_SW,T+(UVLO) to high- side reacts to INH or GDH high level with VBST_SW rising from 5V to 10V in 0.5µs 2.6 µs www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMG2652

5.7 Typical Characteristics

J u n c t i o n T e m p e r a t u r e ( ° C ) Low-Side Normalized On Resistance () - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 6 0 . 8 1 . 2 1 . 4 1 . 6 1 . 8 Figure 5-1. Low-Side Normalized Drain-Source On-Resistance vs Junction Temperature J u n c t i o n T e m p e r a t u r e ( ° C ) High-Side Normalized On Resistance () - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 6 0 . 8 1 . 2 1 . 4 1 . 6 1 . 8 Figure 5-2. High-Side Normalized Drain-Source On-Resistance vs Junction Temperature J u n c t i o n T e m p e r a t u r e ( ° C ) Low-Side Drain Current Turn-On Delay Time (ns) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 0 2 0 3 0 4 0 5 0 Figure 5-3. Low-Side Drain Current Turn-On Delay Time vs Junction Temperature J u n c t i o n T e m p e r a t u r e ( ° C ) Low-Side Turn-Off Delay Time (ns) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 0 2 0 3 0 4 0 5 0 6 0 Figure 5-4. Low-Side Turn-Off Delay Time vs Junction Temperature J u n c t i o n T e m p e r a t u r e ( ° C ) High-Side Drain Current Turn-On Delay Time (ns) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 0 2 0 3 0 4 0 5 0 Figure 5-5. High-Side Drain Current Turn-On Delay Time vs Junction Temperature J u n c t i o n T e m p e r a t u r e ( ° C ) High-Side Turn-Off Delay Time (ns) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 0 2 0 3 0 4 0 5 0 6 0 Figure 5-6. High-Side Turn-Off Delay Time vs Junction Temperature LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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5.7 Typical Characteristics (continued)

J u n c t i o n T e m p e r a t u r e ( ° C ) AUX Standby Current (µA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 3 5 4 0 4 5 5 0 5 5 6 0 Figure 5-7. AUX Standby Current vs Junction Temperature J u n c t i o n T e m p e r a t u r e ( ° C ) AUX Quiescent Current (µA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 INL = 0V Figure 5-8. AUX Quiescent Current vs Junction Temperature J u n c t i o n T e m p e r a t u r e ( ° C ) AUX Quiescent Current (µA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 1 0 0 1 2 0 0 1 3 0 0 1 4 0 0 1 5 0 0 1 6 0 0 INL = 5V Figure 5-9. AUX Quiescent Current vs Junction Temperature F r e q u e n c y ( k H z ) AUX Operating Current (mA) 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 1 . 2 1 . 5 1 . 8 2 . 1 2 . 4 2 . 7 3 . 3 3 . 6 3 . 9 Figure 5-10. AUX Operating Current vs Frequency J u n c t i o n T e m p e r a t u r e ( ° C ) BST Quiescent Current (µA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 6 0 6 5 7 0 7 5 8 0 8 5 INH = 0V Figure 5-11. BST Quiescent Current vs Junction Temperature J u n c t i o n T e m p e r a t u r e ( ° C ) BST Quiescent Current (µA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 3 0 0 3 3 0 3 6 0 3 9 0 4 2 0 4 5 0 4 8 0 5 1 0 5 4 0 5 7 0 INH = 5V Figure 5-12. BST Quiescent Current vs Junction Temperature www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMG2652

F r e q u e n c y ( k H z ) BST Operating Current (mA) 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 0 . 6 1 . 4 1 . 8 2 . 2 2 . 6 Figure 5-13. BST Operating Current vs Frequency LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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6 Parameter Measurement Information

6.1 GaN Power FET Switching Parameters

Figure 6-1 shows the circuit used to measure the GaN power FET switching parameters. The circuit is operated as a double-pulse tester. Consult external references for double-pulse tester details. The circuit is placed in the boost configuration to measure the low-side GaN switching parameters. The circuit is placed in the buck configuration to measure the high-side GaN switching parameters. The GaN FET not being measured in each configuration (high-side in the boost and low-side in the buck) acts as the double-pulse tester diode and circulates the inductor current in the off-state, third-quadrant conduction mode. Table 6-1 shows the details for each configuration. DH SL BST RDRVH AUX SW EN INH INL CS RDRVL AGND LMG265x SW CBST CAUX RCS AGND PGND CBULK LHB VBUS SBOOSTSBUCK VINL VINH VDS(hs) VDS(ls) ISW VGDH GDH Figure 6-1. GaN Power FET Switching Parameters Test Circuit Table 6-1. GaN Power FET Switching Parameters Test Circuit Configuration Details CONFIGURATION GaN FET UNDER TEST GaN FET ACTING AS DIODE SBOOST SBUCK VINL VINH VGDH Boost Low-side High-side Closed Open Double-pulse waveform 0V 0V Buck High-side Low-side Open Closed 0V Double-pulse waveform 0V Buck High-side Low-side Open Closed 0V 0V Double-pulse waveform Figure 6-2 shows the GaN power FET switching parameters. The GaN power FET turn-on transition has three timing components: drain-current turn-on delay time t d(on)(Idrain), turn-on delay time td(on), and turn-on rise time tr(on). Note that the turn-on rise time is the same as the VDS 80% to 20% fall time. The GaN power FET turn-off transition has two timing components: turn-off delay time t d(off), and turn-off fall time tf(off). Note that the turn-off fall time is the same as the VDS 20% to 80% rise time. The turn-off timing components are heavily dependent on the LHB current. The turn-on slew rate is measured over a turn-on rise time voltage delta (240V) to obtain a slew rate which is useful for EMI design. www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMG2652

td(on)(Idrain) ID VDS 400V 390V td(on) 320V 80V 0Vtr(on) Slew rate calculation region 80V td(off) 320V tf(off) 1.8A Figure 6-2. GaN Power FET Switching Parameters LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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7 Detailed Description

7.1 Overview

The LMG2652 is a highly-integrated 650V 140mΩ GaN power-FET half bridge intended for use in switch-mode power-supply applications. The LMG2652 combines the half-bridge power FETs, gate drivers, low-side current- sense emulation function, high-side gate-drive level shifter, and bootstrap diode function in a 6mm by 8mm QFN package. The 650V rated GaN FETs support the high voltages encountered in off-line power switching applications. The GaN FETs low output-capacitive charge reduces both the time and energy needed for power converter switching and is the key characteristic needed to create small, efficient power converters. The LMG2652 internal gate drivers regulate the GaN FET gate voltage for optimum on-resistance. Internal drivers also reduce total gate inductance and GaN FET common-source inductance for improved switching performance. Current-sense emulation places a scaled replica of the low-side drain current on the output of the CS pin. The CS pin is terminated with a resistor to AGND to create the current-sense input signal to the external power supply controller. This CS pin resistor replaces the traditional current-sense resistor, placed in series with the low-side GaN FET source, at significant power and space savings. Furthermore, with no current-sense resistor in series with the GaN source, the low-side GaN FET thermal pad (SL pin) can be connected directly to the PCB power ground, improving system thermal performance. The high-side GaN FET is controlled by both the low-side referenced INH pin and high-side referenced GDH pin allowing the LMG2652 to interface with controllers that employ either high-side gate drive reference scheme. The internal high-side gate-drive level-shifter reliably transmits the INH signal to the high-side with minimal impact to device quiescent current and no impact to device start-up time. The bootstrap diode function between AUX and BST is implemented with a smart-switched GaN bootstrap FET. The switched GaN bootstrap FET allows more complete charging of the BST-to-SW capacitor since the on-state GaN bootstrap FET does not have the forward voltage drop of a traditional bootstrap diode. The smart-switched GaN bootstrap FET also avoids the traditional bootstrap diode problem of BST-to-SW capacitor overcharging due to off-state third-quadrant current flow in the low-side half-bridge GaN power FET. Finally, the bootstrap function has more efficient switching due to low capacitance and no reverse-recovery charge compared to the traditional bootstrap diode. The AUX input supply wide voltage range is compatible with the corresponding wide range supply rail created by power supply controllers. The BST input supply range is even wider on the low end to account for capacitive droop in between bootstrap recharge cycles. Low AUX/BST idle quiescent currents and fast BST start-up time support converter burst-mode operation critical for meeting government light-load efficiency mandates. Further AUX quiescent current reduction is obtained by placing the device in standby mode with the EN pin. The EN, INL, INH, and GDH control pins have high input impedance, low input threshold voltage and maximum input voltage equal to the local supply pin voltage (AUX or BST to SW). This allows the pins to support both low voltage and high voltage input signals and be driven with low-power outputs. The LMG2652 protection features are low-side / high-side under-voltage lockout (UVLO), INL/INH input gate- drive interlock, low-side/high-side cycle-by-cycle current limit, and low-side/high-side overtemperature shut down. The UVLO features also help achieve well-behaved converter operation. www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMG2652

7.2 Functional Block Diagram

INH_pass INL_pass AUX AUX_uvlo Over_temp LS_over_current LS FET Driver LS_fet_enable INH Level-Shifter Transmitter LS_inh_transmit HS FET Driver SW DH HS FET Control HS_fet_enable Bootstrap Control LS_fet_on Bootstrap GaN FET HS Fault Monitor LS_current_sense HS_current_sense HS_over_current BST_uvlo INH Level-Shifter Receiver INH_receive BST GDH LS GaN FET HS GaN FET LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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7.3 Feature Description

7.3.1 GaN Power FET Switching Capability

Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware that the nameplate drain-source voltage cannot be used as an equivalent point to compare devices across technologies. The nameplate drain-source voltage of a silicon FET is set by the avalanche breakdown voltage. The nameplate drain-source voltage of a GaN FET is set by the long term compliance to data sheet specifications. Exceeding the nameplate drain-source voltage of a silicon FET can lead to immediate and permanent damage. Meanwhile, the breakdown voltage of a GaN FET is much higher than the nameplate drain-source voltage. For example, the breakdown drain-source voltage of the LMG2652 GaN power FET is more than 800V which allows the LMG2652 to operate at conditions beyond an identically nameplate rated silicon FET. The LMG2652 GaN power FET switching capability is explained with the assistance of Figure 7-1 . The figure shows the drain-source voltage versus time for the LMG2652 GaN power FET for four distinct switch cycles in a switching application. No claim is made about the switching frequency or duty cycle. The first two cycles show normal operation and the second two cycles show operation during a rare input voltage surge. The LMG2652 GaN power FETs are intended to be turned on in either zero-voltage switching (ZVS) or discontinuous-conduction mode (DCM) switching conditions. VDS(tr) = 650V VDS = 520V t2 t0 t2 Normal DCM Cycle Normal ZVS Cycle t0 t2 t0 t2 Surge DCM Cycle Surge ZVS Cycle VDS(surge) = 720V VDS(tr)(surge) = 800V t1 t1 t1 Figure 7-1. GaN Power FET Switching Capability Each cycle starts before t0 with the FET in the on state. At t0 the GaN FET turns off and parasitic elements cause the drain-source voltage to ring at a high frequency. The high frequency ringing has damped out by t 1. Between t1 and t 2 the FET drain-source voltage is set by the characteristic response of the switching application. The characteristic is shown as a flat line (plateau), but other responses are possible. At t 2 the GaN FET is turned on. For normal operation, the transient ring voltage is limited to 650V and the plateau voltage is limited to 520V. For rare surge events, the transient ring voltage is limited to 800V and the plateau voltage is limited to 720V. www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMG2652

7.3.2 Current-Sense Emulation

The current-sense emulation function creates a scaled replica of the GaN power FET positive drain current at the output of the CS pin. The current-sense emulation gain, G CSE, is 0.901mA output from the CS pin, I CS, for every 1A passing into the drain of the low-side GaN power FET, ID. GCSE = ICS / ID = 0.901mA / 1A = 0.000901 (1) The CS pin is terminated with a resistor to AGND, R CS, to create the current-sense voltage input signal to the external power supply controller. RCS is determined by solving for the traditional current-sense design resistance, R CS(trad), and multiplying by the inverse of G CSE. The traditional current-sense design creates the current-sense voltage, V CS(trad), by passing the GaN power FET drain current, I D, through R CS(trad). The LMG2652 creates the current-sense voltage, V CS, by passing the CS pin output current, I CS, through R CS. The current-sense voltage must be the same for both designs. VCS = ICS × RCS = VCS(trad) = ID × RCS(trad) (2) RCS = ID / ICS × RCS(trad) = 1 / GCSE × RCS(trad) (3) RCS = 1,110 × RCS(trad) (4) The CS pin is clamped internally to a typical 2.5V. The clamp protects vulnerable power-supply controller current-sense input pins from over voltage if, for example, the current sense resistor on the CS pin were to become disconnected. Figure 7-2 shows the current-sense emulation operation. In both cycles, the CS pin current emulates the GaN power FET drain current while the GaN FET is enabled. The first cycle shows normal operation where the controller turns off the GaN power FET when the controller current-sense input threshold is tripped. The second cycle shows a fault situation where the LMG2652 overcurrent protection turns off the GaN power FET before the controller current-sense input threshold is tripped. In this second cycle, the LMG2652 avoids a hung controller IN pulse by generating a fast-ramping artificial current-sense emulation signal to trip the controller current-sense input threshold. The artificial signal persists until the IN pin goes to logic-low which indicates the controller is back in control of switch operation. INL = PWM Signal from Controller Low-Side FET Drain Current Low-Side FET Enable CS Pin Current FET On FET Off INL Logic High INL Logic Low 0 A IT(OC) 0 A Effective Controller Current-Sense Input Threshold Artificial Current-Sense Emulation Signal Cycle without Overcurrent Protection Cycle with Overcurrent Protection Figure 7-2. Current-Sense Emulation Operation LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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7.3.3 Bootstrap Diode Function

The internal bootstrap diode function is implemented with a smart-switched GaN bootstrap FET. The GaN bootstrap FET blocks current in both directions between AUX and BST when the GaN bootstrap FET is turned off. The bootstrap diode function is active when the low-side GaN power FET is turned on and inactive when the low-side GaN power FET is turned off. The GaN bootstrap FET is held off in the bootstrap diode inactive phase. The GaN bootstrap FET is turned on a single time at the beginning of the bootstrap active phase and is controlled as an ideal diode with diode current flowing from AUX to BST to charge the BST-to-SW capacitor. If a small reverse current from BST to AUX is detected after the GaN bootstrap FET is turned on, the GaN bootstrap FET is turned off for the remainder of the bootstrap active phase. The bootstrap diode function implements a current limit to protect the GaN bootstrap FET when the BST-to-SW capacitor is significantly discharged at the beginning of the bootstrap active phase. If there is no current limit situation during the GaN bootstrap FET turn on, or if the bootstrap function drops out of current limit as the BST-to-SW capacitor charges, the current limit function is disabled for the remainder of the GaN bootstrap FET turn-on time. The current limit function is disabled to save quiescent current.

7.3.4 Input Control Pins (EN, INL, INH, GDH)

The EN pin is referenced to AGND and is used to toggle the device between the active and standby modes described in the Device Functional Modes section. The INL pin is referenced to AGND and is used to turn the low-side GaN power FET on and off. The INH pin is referenced to AGND and is used to turn the high-side GaN power FET on and off. The INH pin is compatible with controllers that use a low-side referenced gate drive signal to control the high-side GaN power FET. The GDH pin is referenced to SW and is used to turn the high-side GaN power FET on and off. The GDH pin is compatible with controllers that use a high-side referenced signal to control the high-side GaN power FET. The LMG2652 is intended to be used with either the INH pin or the GDH pin controlling the high-side GaN power FET. Short the unused pin to its reference (INH to AGND or GDH to SW). The input control pins have a typical 1V input-voltage-threshold hysteresis for noise immunity. The pins also have a typical 400k Ω pull-down resistance to protect against floating inputs. The 400k Ω saturates for typical input voltages above 4V to limit the maximum input pull-down current to a typical 10uA. There are individual forward based ESD diodes from the EN, INL, and INH pins to the AUX pin. Avoid driving the EN, INL, and INH voltages higher than the AUX voltage. There is also a forward based ESD diode from the GDH pin to the BST pin. Avoid driving the GDH-to-SW voltage higher than the BST-to-SW voltage. The INL turn-on action is blocked by the following conditions:

Standby mode (as set by the EN pin above)
INH in control of the INL/INH interlock
AUX under-voltage lockout (UVLO)
Low-side overtemperature protection
Low-side GaN Power FET overcurrent protection The INH turn-on action is blocked by the following conditions
Standby mode (as set by the EN pin above)
INL in control of the INL/INH interlock
AUX UVLO
Low-side overtemperature protection
BST UVLO
High-side overcurrent protection The GDH turn-on action is blocked by the following conditions
BST UVLO www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMG2652

High-side overtemperature protection
High-side overcurrent protection Note that the INH pin is blocked by the low-side temperature protection while the GDH pin is blocked by the high-side temperature protection. All the blocking conditions except the INL/INH interlock and the overcurrent protection act independently of the INL, INH, or GDH logic state. Figure 7-3 shows the operation of these control-input independent blocking conditions. INL or INH or GDH Logic High Logic Low Blocking Condition Asserted Blocking Condition De-Asserted GaN FET Enable GaN Power FET On GaN Power FET Off Control-Input Independent Blocking Condition 1 2 Figure 7-3. Control-Input-Independent Blocking Condition Operation The INL/INH Interlock blocking action is described in the INL - INH Interlock section. Meanwhile, the overcurrent protection blocking action only asserts after the control input has turned on its respective GaN power FET. See the Overcurrent Protection section for the details.

7.3.5 INL - INH Interlock

The interlock function keeps the low-side and high-side GaN power FETs from being simultaneously turned on when the INL and INH pins are both logic-high. Either the INL or the INH pin gains control of the interlock if either pin is logic high when the other pin is logic low. Once the INL or INH pin gains control of the interlock, it retains control as long as it remains logic high. Only the INL or INH pin in control of the interlock passes a logic-high signal through the interlock. Note that there is no interlock feature regarding the GDH pin. This means it is possible to simultaneously turn on the low-side and high-side GaN power FETs if the INL and GDH pins are both logic-high.

7.3.6 AUX Supply Pin

The AUX pin is the input supply for the low-side internal circuits and is the power source to charge the BST-to- SW capacitor through the internal bootstrap diode function. The AUX external capacitance is recommended to be a ceramic capacitor that is at least three times larger than the BST-to-SW external capacitance over operating conditions.

7.3.6.1 AUX Power-On Reset

The AUX Power-On Reset disables all low-side functionality, including the INH pin function, if the AUX voltage is below the AUX Power-On Reset voltage. The AUX Power-On Reset voltage is not specified but is around 5V. The AUX Power-On Reset enables the low-side overtemperature protection function if the AUX voltage is above the AUX Power-On Reset voltage.

7.3.6.2 AUX Under-Voltage Lockout (UVLO)

The AUX UVLO blocks the INL pin from turning on the low-side GaN power FET and blocks the INH pin from turning on the high-side GaN power FET if the AUX voltage is below the AUX UVLO voltage. Figure 7-3 shows the AUX UVLO blocking operation. The AUX UVLO voltage is set higher than the BST UVLO voltage so the high-side GaN power FET can be operated when the low-side GaN power FET is operating. The voltage separation between the AUX UVLO voltage and BST UVLO voltage accounts for operating conditions where LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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the bootstrap charging of the BST-to-SW capacitor from the AUX supply is incomplete. The AUX UVLO voltage hysteresis prevents on-off chatter near the UVLO voltage trip point.

7.3.7 BST Supply Pin

The BST pin is the input supply for the high-side internal circuits. The BST pin and corresponding high-side circuits are referenced to the SW pin. The BST pin is powered by the low-side AUX Supply pin through the internal bootstrap diode function. The bootstrap function is inactive when the low-side GaN FET is off and the BST pin must rely on an external BST-to-SW capacitor for the BST power source. Designing the BST-to-SW capacitance is a trade-off between high-side charge-up time and hold-up time. The BST-to-SW external capacitance is recommended to be a ceramic capacitor that is at least 10nF over operating conditions.

7.3.7.1 BST Power-On Reset

The BST Power-On Reset voltage is with respect to the SW pin. The BST Power-On Reset disables all high-side functionality if the BST-to-SW voltage is below the BST Power-On Reset voltage. The BST Power-On Reset voltage is not specified but is around 5V.

7.3.7.2 BST Under-Voltage Lockout (UVLO)

The BST UVLO voltage is with respect to the SW pin. The BST UVLO blocks both the INH and GDH pins from turning on the high-side GaN power FET if the BST-to-SW voltage is below the applicable BST UVLO voltage as described as follows. Figure 7-3 shows the BST UVLO blocking operation. The BST UVLO consists of two separate UVLO functions to create a two-level BST UVLO. The upper BST UVLO is called the BST Turn-On UVLO and only controls if the high-side GaN power FET is allowed to turn on. The lower BST UVLO is called the BST Turn-Off UVLO and only controls if the high-side GaN power FET is turned off after the high-side GaN power FET is already turned on. The operation of the two-level UVLO is not the same as a single UVLO with hysteresis. Figure 7-4 shows the two-level BST UVLO operation. The BST Turn-On UVLO prevents the high-side GaN power FET from turning on, for INH or GDH logic-high, if the BST-to-SW voltage is below the BST Turn-On UVLO voltage (INH/GDH pulse #1, first portion of pulse #2, and pulse #5). After the high-side GaN power FET is successfully turned-on, the BST Turn-On UVLO is ignored and the BST Turn-Off UVLO output is watched for the remainder of the INH or GDH logic-high pulse (INH/GDH second portion of pulse #2, pulses #3, #4, and #6. The BST Turn-Off UVLO turns off the high-side GaN power FET for the remainder of the INH/GDH logic-high pulse if the BST-to-SW voltage falls below the BST Turn-Off UVLO voltage (INH/GDH pulse #6). INH or GDH Logic High Logic Low FET On FET Off High-Side FET Enable BST-to-SW Voltage BST Turn-On UVLO BST Turn-Off UVLO 1 2 3 5 4 6 Figure 7-4. BST UVLO Operation The effective voltage hysteresis of the two-level BST UVLO is the difference between the upper and lower BST UVLO voltages. A single-level BST UVLO can be implemented with the same hysteresis but allows subsequent high-side GaN power FET turn on anywhere in the hysteresis range. A single-level BST UVLO allows INH/GDH pulse #5 to turn on the high-side GaN power. The two-level UVLO design prevents any turn on in the hysteresis range. The two-level BST UVLO allows a wide hysteresis while making sure the BST-to-SW capacitor is adequately charged at the beginning of every INH or GDH pulse. The wide hysteresis allows a smaller BST-to-SW capacitor www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMG2652

to be used which is useful for faster high-side start-up time. The adequate capacitor charge at the beginning of the INH or GDH pulse helps make sure the high-side GaN power FET is not turned-off early in the INH or GDH pulse which can create erratic converter operation.

7.3.8 Overcurrent Protection

The LMG2652 implements cycle-by-cycle overcurrent protection for both half-bridge GaN power FETs. Figure 7-5 shows the cycle-by-cycle overcurrent operation. Every INL or INH or GDH logic-high cycle turns on the controlled GaN power FET. If the GaN power FET drain current exceeds the overcurrent threshold current, the overcurrent protection turns off the GaN power FET for the remainder of the INL or INH or GDH logic-high duration. INL or INH or GDH GaN FET Drain Current FET On FET Off IT(OC) Logic High Logic Low 0 A GaN FET Enable Figure 7-5. Cycle-by-Cycle Overcurrent Protection Operation Cycle-by-cycle overcurrent protection minimizes system disruption because the event is not reported and because the protection allows the GaN power FET to turn on every INL or INH or GDH cycle. As described in the Current-Sense Emulation section, an artificial CS pin current is produced after the low-side GaN power FET is turned off by the low-side overcurrent protection in order to prevent the controller from entering a hung state.

7.3.9 Overtemperature Protection

The LMG2652 implements separate overtemperature protection for both the low-side and high-side device circuits. The low-side overtemperature protection blocks the INL pin from turning on the low-side GaN power FET and blocks the INH pin from turning on the high-side GaN power FET if the low-side temperature is above the overtemperature protection temperature. The high-side overtemperature protection blocks the GDH pin from turning on the high-side GaN power FET if the high-side temperature is above the overtemperature protection temperature. Figure 7-3 shows the overtemperature blocking operation. The overtemperature protection hysteresis avoids erratic thermal cycling. The low-side overtemperature protection is enabled when the AUX voltage is above the AUX Power-On Reset voltage. The low AUX Power-On Reset voltage helps the overtemperature protection remain operational when the AUX rail droops during a power converter cool-down phase. The high-side overtemperature protection is enabled when the BST-to-SW voltage is above the BST Power-On Reset voltage.

7.4 Device Functional Modes

The LMG2652 has two modes of operation controlled by the EN pin. The device is in Active mode when the EN is logic high and in Standby mode when the EN pin is logic low. In active mode, the half-bridge GaN power FETs are controlled by the INL, INH, and GDH pins. In Standby mode, the INL and INH pins are ignored, the low-side GaN power FET and bootstrap diode are held off, the INH pin is blocked from turning on the high-side FET, and the AUX quiescent current is reduced to the AUX standby quiescent current. Note that in Standby mode the high-side GaN power FET can still be controlled by the GDH pin if the BST pin is powered by an external source. LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The LMG2652 is a GaN power-FET half bridge with plug-and-play simplicity since it integrates the half-bridge FETs, FET gate drivers, high-side gate-drive level shifter, bootstrap diode function, and current-sense emulation in a single package. The integrated gate driver, low IN input threshold voltage, and wide AUX input-supply voltage allows the LMG2652 to seamlessly pair with common industry power-supply controllers. www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMG2652

8.2 Typical Application

8.2.1 LLC Application

Figure 8-1. 200W LLC Converter Application

8.2.1.1 Design Requirements

Table 8-1. Design Specification SPECIFICATION VALUE Input DC voltage range 365 VDC to 410 VDC Output DC voltage 19.5V Ouput rated current 10.3A Output voltage ripple at 390 VDC 120mVpp Peak efficiency at 390 VDC 93%

8.2.1.2 Detailed Design Procedure

The typical application shows the LMG2652 pairing a LLC controller to create a high-power-density, high- efficiency, 200W, LLC converter. The 200W LLC converter application is adapted from the typical application. This detailed design procedure focuses on the specifics of using the LMG2652 in the application. LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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8.2.1.3 Application Curves

The following waveform shows typical switching waveforms. The red trace is the switch-node voltage of LMG2652, the green trace is the current-sense voltage across RISNS, and the blue trace is VOUT. Figure 8-2. VIN = 400VDC www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMG2652

8.2.2 AHB Application

Figure 8-3. 140W AHB Converter Application

8.3 Power Supply Recommendations

The LMG2652 operates from a single input supply connected to the AUX pin. The BST pin is powered internally by the AUX pin. The LMG2652 is intended to be operated from the same supply managed and used by the power supply controller. The wide recommended AUX voltage range of 10V to 26V overlaps common-controller supply-pin turn-on and UVLO voltage limits. The BST-to-SW external capacitance is recommended to be a ceramic capacitor that is at least 10nF over operating conditions. The AUX external capacitance is recommended to be a ceramic capacitor that is at least three-times larger than the BST-to-SW capacitance over operating conditions. LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

Product Folder Links: LMG2652

8.4 Layout

8.4.1 Layout Guidelines

8.4.1.1 Solder-Joint Stress Relief

Large QFN packages can experience high solder-joint stress. Several best practices are recommended to provide solder-joint stress relief. First, the instructions for the NC anchor pins found in Pin Configuration and Functions section must be followed. Second, all the board solder pads must be non-solder-mask defined (NSMD) as shown in the land pattern example within the Mechanical, Packaging, and Orderable Information section. Finally, any board trace connected to an NSMD pad must be less than 2/3 the width of the pad on the pad side where it is connected. The trace must maintain this 2/3 width limit for as long as it is not covered by solder mask. After the trace is under solder mask, there are no limits on the trace dimensions. All these recommendations are followed in the Layout Example section.

8.4.1.2 Signal-Ground Connection

Design the power supply with separate signal and power grounds that only connect in one location. Connect the LMG2652 AGND pin to signal ground. Connect the LMG2652 SL pin and low-side thermal pad to power ground. The LMG2652 serves as the single connection point between the signal and power grounds since the AGND pin, SL pin, and low-side thermal pad are connected internally. Do not connect the signal and power grounds anywhere else on the board except as recommended in the next sentence.

8.4.1.3 CS Pin Signal

As seen with Equation 4 , the current-sense signal impedance is three orders of magnitude higher than a traditional current-sense signal. This higher impedance has implications for current-sense signal noise susceptibility. Minimize routing the current-sense signal near any noisy traces. Place the current-sense resistor and any filtering capacitors at the far end of the trace next to the controller current-sense input pin.

8.4.2 Layout Example

Figure 8-5. PCB Inner Layer (Second Layer) LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com LMG2652 SNOSDL5 – JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMG2652

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES January 2025 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LMG2652 SNOSDL5 – JANUARY 2025 www.ti.com

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www.ti.com 20-Feb-2025 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMG2652RFBR ACTIVE VQFN RFB 19 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 LMG2652 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com VQFN - 1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RFB0019A A 0.08 C 6.1 5.9 0.8 SEATING PLANE PIN 1 INDEX AREA C (0.10) TYP PIN 1 ID B 8.1 7.9 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

0.1 C A B

0.05 C 13X (0.25) 2X 7.05 2X 5.95 4X 0.552X 5.95 22X 0.65 2X 5.05 2X 3.9 3X 0.575 36X 0.3 0.2 20X 0.7 0.5 0.65

0.000 PKG ℄

2.075±0.1 1.025 1.025 0.7±0.1 8 9 1119 16 0.05

www.ti.com VQFN - 1 mm max heightRFB0019A PLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 12X SOLDER MASK DETAILS

0.05 MAX

(PREFERRED) SOLDER MASK DEFINED NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. (R0.05) TYP 2X (7.05) 2X (5.95) 22X (0.65) 4X (0.55) 2X (5.05) 2X (3.9) 3X (0.575) (Ø0.2) TYP (2.8) (0.862) (0.65) (0.337) (1.537) (3.8) 3X (2.03) (2.225) (0.7) 20X (0.8) 36X (0.25) 13X (0.45) 1519

www.ti.com VQFN - 1 mm max heightRFB0019A PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 12X NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. (R0.05) TYP 2X (7.05) 2X (5.95) 22X (0.65) 4X (0.55) 2X (5.05) 2X (3.9) 3X (0.575) (2.8) (3.8) 4X (2.59) 20X (0.8) 36X (0.25) 9X (0.45) 1519 4X (1.41) 2X (1.46) 2X (2.99) (3.975) 2X (1.462) 2X (1.375) 2X (0.075) 2X (0.937) (2.975) 2X (2.137) 8X (1) 4X (1.25) 4X (1.33) 8X (0.98)

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Product Information

LMG2652RFBR specifications and overview.

Summary

LMG2652 650V 140mΩ GaN Half Bridge With Integrated Driver and Current Sense Emulation JANUARY 2025

Description

LMG2652 650V 140mΩ GaN Half Bridge With Integrated Driver and Current Sense Emulation JANUARY 2025

Source title LMG2652RFBR Datasheet(PDF) - Texas Instruments

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LMG2652 TI | Alldatasheet

Document overview

Technical content

1 Features

2 Applications

3 Description

Package Information

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

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5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Thermal Information

19 PINS

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5.5 Electrical Characteristics

5.5 Electrical Characteristics (continued)

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5.6 Switching Characteristics

80 V/ns

5.7 Typical Characteristics

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5.7 Typical Characteristics (continued)

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6 Parameter Measurement Information

6.1 GaN Power FET Switching Parameters

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7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 GaN Power FET Switching Capability

7.3.2 Current-Sense Emulation

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7.3.3 Bootstrap Diode Function

7.3.4 Input Control Pins (EN, INL, INH, GDH)

7.3.5 INL - INH Interlock

7.3.6 AUX Supply Pin

7.3.6.1 AUX Power-On Reset

7.3.6.2 AUX Under-Voltage Lockout (UVLO)

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7.3.7 BST Supply Pin

7.3.7.1 BST Power-On Reset

7.3.7.2 BST Under-Voltage Lockout (UVLO)

7.3.8 Overcurrent Protection

7.3.9 Overtemperature Protection

7.4 Device Functional Modes

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8 Application and Implementation

8.1 Application Information

8.2 Typical Application

8.2.1 LLC Application

8.2.1.1 Design Requirements

8.2.1.2 Detailed Design Procedure

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8.2.1.3 Application Curves

8.2.2 AHB Application

8.3 Power Supply Recommendations

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8.4 Layout

8.4.1 Layout Guidelines

8.4.1.1 Solder-Joint Stress Relief

8.4.1.2 Signal-Ground Connection

8.4.1.3 CS Pin Signal

8.4.2 Layout Example

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9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

9.2 Support Resources

9.3 Trademarks

9.4 Electrostatic Discharge Caution

9.5 Glossary

11 Mechanical, Packaging, and Orderable Information

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