LMF90

LMF90 NSC | Alldatasheet

Document overview

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Technical content

Features

Y Center frequency set by external clock or on-board clock oscillator Y No external components needed to set response char- acteristics Y Notch width, attenuation, and clock-to-center-frequency ratio independently programmable Y 14 pin 0.3 × wide package Key Specifications Y f0 Range 0.1 Hz to 30 kHz Y f0 accuracy over full temperature range (max) 1.5% Y Supply voltage range g2V to g7.5V or 4V to 15V Y Passband Ripple (typ) 0.25 dB Y Attenuation at f 0 (typ) 39 dB or 48 dB (selectable) Y fCLK:f 0 100:1, 50:1, or 33.3:1 Y Notch Bandwidth (typ) 0.127 f 0, 0.26 f 0, or 0.55 f 0 Y Output offset voltage (max) 120 mV

Applications

Y Automatic test equipment Y Communications Y Power line interference rejection Typical Connection

60 Hz Notch Filter

TL/H/10354–1 Connection Diagram Dual-In-Line and Small Outline Packages TL/H/10354–2 Top View Order Number LMF90CCN, LMF90CIWM, LMF90CCWM, LMF90CIJ, LMF90CCJ, LMF90CIN, LMF90CMJ or LMF90CMJ/883 See NS Package Number J14A, M14B or N14A C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&3 ) If Military/Aerospace specified devices are required, Soldering Information (Note 4) please contact the National Semiconductor Sales N Package (Soldering, 10 sec.) 260 §C Office/Distributors for availability and specifications. J Package (Soldering, 10 sec.) 300 §C Supply Voltage (V S e Va b Vb) b0.3V to a16V Storage Temperature Range b65§Ct o a150§C Voltage at any Input or Output V b b0.3V to V a a0.3V Junction Temperature 150 §C Input Current at any Pin (Note 10) 5 mA Operating Ratings (Notes2&3 )Package Input Current (Note 10) 20 mA Temperature Range T MIN s TA s TMAXPower Dissipation (Note 5) 500 mW LMF90CCN, LMF90CCWM,ESD Susceptability (Note 6) LMF90CCJ 0 §C s TA s a70§CPin 9 1800V LMF90CIJ, LMF90CIWM, LMF90CINAll Other Pins 2000V b40§C s TA s a85§C LMF90CMJ, LMF90CMJ/883 b55§C s TA s a125§C Supply Voltage Range 4.0V to 15.0V TA e TMIN to T MAX; all other limits T A e TJ e 25§C. LMF90CCJ, LMF90CCN, LMF90CIJ, LMF90CIWM, LMF90CCWM LMF90CIN, LMF90CMJ Units Symbol Parameter Conditions Typ Tested Design Typ Tested Design (Limit) (Note 7) Limit Limit (Note 7) Limit Limit (Note 8) (Note 9) (Note 8) (Note 9) fO Center Frequency 0.1 0.1 Hz (Min) Range 30 30 30 kHz (Max) fCLK Clock Frequency Pin 6 10 10 Hz (Min) Range Pin 6 1.5 1.5 1.5 MHz (Max) Pins 4 and 5 4.0 4.0 4.0 MHz (Max) HON Passband Gain DC and 20 kHz, W e D e Vb,R e Va, 0 g0.2 g0.2 0 g0.2 dB (Max)fCLK e 167 kHz W e D e R e GND, 0 g0.2 g0.2 0 g0.2 dB (Max)fCLK e 250 kHz W e Va,D e GND, R e Vb, 0 g0.2 g0.2 0 g0.2 dB (Max)fCLK e 500 kHz

TA e TMIN to T MAX; all other limits T A e TJ e 25§C. (Continued) LMF90CCJ, LMF90CCN, LMF90CIJ, LMF90CIWM, LMF90CCWM LMF90CIN, LMF90CMJ Units Symbol Parameter Conditions Typ Tested Design Typ Tested Design (Limit) (Note 7) Limit Limit (Note 7) Limit Limit (Note 8) (Note 9) (Note 8) (Note 9) AMin1@fO1 Gain at W e D e Vb,R e Va, b39 b30 b30 b39 b30 dB (Max)Center Frequency f CLK e 167 kHz AMin2@fO2 W e D e R e GND, b48 b36.5 b36.5 b48 b36.5 dB (Max)fCLK e 250 kHz AMin3@fO3 W e Va,D e GND, R e Vb, b48 b36.5 b36.5 b48 b36.5 dB (Max)fCLK e 500 kHz Additional Center W e GND, D e Vb,R e Va, b36 b30 b30 b36 b30 dB (Max)Frequency Gain f CLK e 167 kHz Tests at f O1 W e Va,D e Vb,R e Va, b36 b30 b30 b36 b30 dB (Max)fCLK e 167 kHz W e Vb,D e GND, R e Va, b42 b30 b30 b42 b30 dB (Max)fCLK e 167 kHz W e D e GND, R e Va, b48 b35 b35 b48 b35 dB (Max)fCLK e 167 kHz W e Va,D e GND,R e Va, b48 b35 b35 b48 b35 dB (Max)fCLK e 167 kHz

TA e TMIN to T MAX; all other limits T A e TJ e 25§C. (Continued) LMF90CCJ, LMF90CCN, LMF90CIJ, LMF90CIWM, LMF90CCWM LMF90CIN, LMF90CMJ Units Symbol Parameter Conditions Typ Tested Design Typ Tested Design (Limit) (Note 7) Limit Limit (Note 7) Limit Limit (Note 8) (Note 9) (Note 8) (Note 9) Additional Center W e Vb,D e Vb,R e GND, b36 b30 b30 b36 b30 dB (Max)Frequency Gain f CLK e 250 kHz Tests at f O2 W e GND, D e Vb,R e GND, b36 b30 b30 b36 b30 dB (Max)fCLK e 250 kHz W e Va,D e Vb,R e GND, b36 b30 b30 b36 b30 dB (Max)fCLK e 250 kHz W e Vb,D e R e GND, b42 b30 b30 b42 b30 dB (Max)fCLK e 250 kHz W e Va,D e R e GND, b48 b35 b35 b48 b35 dB (Max)fCLK e 250 kHz Additional Center W e D e R e Vb, b36 b30 b30 b36 b30 dB (Max)Frequency Gain f CLK e 500 kHz Tests at f O3 W e GND, D e Vb,R e Vb, b36 b30 b30 b36 b30 dB (Max)fCLK e 500 kHz W e Va,D e Vb,R e Vb, b36 b30 b30 b36 b30 dB (Max)fCLK e 500 kHz W e Vb,D e GND, R e Vb, b42 b30 b30 b42 b30 dB (Max)fCLK e 500 kHz W e D e GND, R e Vb, b48 b35 b35 b48 b35 dB (Max)fCLK e 500 kHz A3a Gain at f 3 e 0.995 f O1 W e D e Vb,R e Va, b41 b30 b30 b41 b30 dB (Max) A4a Gain at f 4 e 1.005 f O1 fCLK e 167 kHz b41 b30 b30 b41 b30 dB (Max) A3b Gain at f 3 e 0.992 f O2 W e D e R e GND, f CLK e 250 kHz b40 b35 b35 b40 b35 dB (Max) A4b Gain at f 4 e 1.008 f O2 b40 b35 b35 b40 b35 dB (Max) A3c Gain at f 3 e 0.982 f O3 W e Va,D e GND, R e Vb b41 b35 b35 b41 b35 dB (Max) A4c Gain at f 4 e 1.018 f O3 fCLK e 500 kHz b41 b35 b35 b41 b35 dB (Max) fCLK e 167 kHz 0.25 0 0 0.25 0 dB (Min) 0.25 0 0 0.25 0 dB (Min)

TA e TMIN to T MAX; all other limits T A e TJ e 25§C. (Continued) LMF90CCJ, LMF90CCN, LMF90CIJ, LMF90CIWM, LMF90CCWM LMF90CIN, LMF90CMJ Units Symbol Parameter Conditions Typ Tested Design Typ Tested Design (Limit) (Note 7) Limit Limit (Note 7) Limit Limit (Note 8) (Note 9) (Note 8) (Note 9) fCLK e 250 kHz 0.25 0 0 0.25 0 dB (Min) 0.25 0 0 0.25 0 dB (Min) fCLK e 500 kHz 0.25 0 0 0.25 0 dB (Min) 0.25 0 0 0.25 0 dB (Min) En Output Noise 20 kHz Bandwidth W e D e Vb,R e Va,f CLK e 167 kHz 670 670 mVrms W e D e R e GND, f CLK e 250 kHz 370 370 mVrms W e Va,D e GND, R e Vb, 250 250 mVrmsfCLK e 500 kHz Clock Feedthrough 50 50 mVp–p GBW Output Buffer 1 1 MHzGain Bandwidth SR Output Buffer 33 V / msSlew Rate CL Maximum Capacitive 200 200 pFLoad

TA e TMIN to T MAX; all other limits T A e TJ e 25§C. LMF90CCJ, LMF90CCN, LMF90CIJ, LMF90CIWM, LMF90CCWM LMF90CIN, LMF90CMJ Units Symbol Parameter Conditions Typ Tested Design Typ Tested Design (Limit) (Note 7) Limit Limit (Note 7) Limit Limit (Note 8) (Note 9) (Note 8) (Note 9) VOS Output Offset Voltage W e D e Vb,R e Va,f CLK e 167 kHz g50 g120 g120 g50 g120 mV (Max) W e D e R e GND, f CLK e 250 kHz g60 g140 g140 g60 g140 mV (Max) W e Va,D e GND, R e Vb, g80 g170 g170 g80 g170 mV (Max) fCLK e 500 kHz VI1 Logical ‘‘Low’’ Pins 1, 2, 3, 7, and 10 b4.0 b4.0 b4.0 V (Max)Input Voltage VI2 Logical ‘‘GND’’ Pins 1, 2, 3, 7, and 10 a1.0 a1.0 a1.0 V (Max) Input Voltage b1.0 b1.0 b1.0 V (Min) VI3 Logical ‘‘High’’ Pins 1, 2, 3, and 7 a4.0 a4.0 a4.0 V (Min)Input Voltage IIN Input Current Pins 1, 2, 3, 7, and 10 g10 g10 g10 mA (Max) VIL Logical ‘‘0’’ Input Pin 5, XLS e Va b4.0 b4.0 b4.0 V (Max)Voltage, Pins 5 and 6 or Pin 6, XLS e GND VIH Logical ‘‘1’’ Input a4.0 a4.0 a4.0 V(Min)Voltage, Pins 5 and 6 VIL Logical ‘‘0’’ Input V a b Vb e 10V, XLS e Vb or a0.8 a0.8 a0.8 V (Max)Voltage, Pin 6 V a ea 5V, V b e 0V, XLS ea 2.5V VIH Logical ‘‘1’’ Input a2.0 a2.0 a2.0 V (Min)Voltage, Pin 6 VOL Logical ‘‘0’’ Output XLS e Va, lIOUTl e 4m A b4.0 b4.0 b4.0 V (Max)Voltage, Pin 6 VOH Logical ‘‘1’’ Output a4.0 a4.0 a4.0 V (Min)Voltage, Pin 6

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is intended to be functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: All voltages are measured with respect to GND unless otherwise specified. Note 4: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in any current Linear Data Book for other methods of soldering surface mount devices. Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX, HJA and the ambient temperature, T A. The maximum allowable power dissipation at any temperature is P D e (TJMAX b TA)/HJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T JMAX e 150§C, and the typical thermal resistance ( HJA) when board mounted is 61 §C/W for the LMF90CCN and CIN, 134 §C/W for the LMF90CCWM and CWIM and 59 §C/W for the LMF90CCJ, CIJ and CMJ. Note 6: Human body model, 100 pF discharged through a 1.5 k X resistor. Note 7: Typicals are at T J e 25§C and represent the most likely parametric norm. Note 8: Tested Limits are guaranteed and 100% tested. Note 9: Design Limits are guaranteed, but not 100% tested. Note 10: When the input voltage (V IN) at any pin exceeds the power supplies (V IN k Vb or V IN l Va), the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.

Typical Performance Characteristics Clock Frequency Notch Depth vs Supply Voltage Notch Depth vs vs Temperature Notch Depth vs Power Supply Voltage Power Supply Current vs Temperature Power Supply Current Clock Frequency Offset Voltage vs Supply Voltage Offset Voltage vs Temperature Offset Voltage vs Clock Frequency Passband Width vs Supply Voltage Passband Width vs Temperature Passband Width vs Clock Frequency Stopband Width vs TL/H/10354–3

Typical Performance Characteristics (Continued) vs Supply Voltage Stopband Width vs Temperature Stopband Width vs Clock Frequency Ratio Deviation Clock-to-Center-Frequency vs Supply Voltage Ratio Deviation Clock-to-Center-Frequency vs Temperature Ratio Deviation Clock-to-Center-Frequency vs Supply Voltage Output Swing Swing vs Load Resistance Positive Output Voltage Swing vs Load Resistance Negative Output Voltage vs Temperature Positive Output Swing vs Temperature Negative Output Swing TL/H/10354–4

W (Pin 1) This three-level logic input sets the width of the notch. Notch width is f c2 –fc1 (see Figure 1 ). When W is tied to V a (pin 14), GND (pin 13), or V b (pin 8), the notch width is 0.55 f 0, 0.26 f 0, or 0.127 f 0, respectively. R (Pin 2) This three-level logic input sets the ratio of the clock frequency (f CLK) to the center fre- quency (f 0). When R is tied to V a, GND, or Vb, the clock-to-center-frequency ratio is 33.33:1, 50:1, or 100:1, respectively. LD (Pin 3) This three-level logic input sets the division factor of the clock frequency divider. When LD is tied to V a, GND, or V b, the division factor is 716, 596, or 2, respectively. XTAL2 (Pin 4) This is the output of the internal crystal os- cillator. When using the internal oscillator, the crystal should be tied between XTAL2 and XTAL1. (The capacitors are internalÐ no external capacitors are needed for the oscillator to operate.) When not using the internal oscillator this pin should be left open. XTAL1 (Pin 5) This is the crystal oscillator input. When us- ing the internal oscillator, the crystal should be tied between XTAL1 and XTAL2. XTAL1 can also be used as an input for an external clock signal swinging from V a to V b. The frequency of the crystal or the external clock will be divided internally by the clock divider as determined by the programming voltage on pin 3. CLK (Pin 6) This is the filter clock pin. The clock signal appearing on this pin is the filter clock CLK). When using the internal crystal oscil- lator or an external clock signal applied to pin 5 while pin 7 is tied to V a, the CLK pin is the output of the divider and can be used to drive other LMF90s with its rail-to-rail output swing. When not using the internal crystal oscillator or an external clock on pin 5, the CLK pin can be used as a CMOS or TTL clock input provided that pin 7 is tied to GND or V b. For best performance, the duty cycle of a clock signal applied to this pin should be near 50%, especially at higher clock frequencies. XLS (Pin 7) This is a three-level logic pin. When XLS is tied to V a, the crystal oscillator and fre- quency divider are enabled and CLK (pin 6) is an output. When XLS is tied to GND (pin 13), the crystal oscillator and frequency di- vider are disabled and pin 6 is an input for a clock swinging between V b and V a. When XLS is tied to V b, the crystal oscillator and frequency divider are disabled and pin 6 is a TTL level clock input for a clock signal swinging between GND and V a or between Vb and GND. Vb (Pin 8) This is the negative power supply pin. It should be bypassed with at least a 0.1 mF capacitor. For single-supply operation, connect this pin to system ground. V OUT (Pin 9) This is the filter output. D (Pin 10) This two-level logic input is used to set the depth of the notch (the attenuation at f 0). When D is tied to GND or V b, the typical notch depth is 48 dB or 39 dB, respective- ly. Note, however, that the notch depth is also dependent on the width setting (pin 1). See the Electrical Characteristics for tested limits. V IN2 (Pin 11) This is the input to the difference amplifier section of the notch filter. VIN1 (Pin 12) This is the input to the internal bandpass filter. This pin is normally connected to pin 11. For wide bandwidth applications, an anti-aliasing filter can be inserted between pin 11 and pin 12. GND (Pin 13) This is the analog ground reference for the LMF90. In split supply applications, GND should be connected to the system ground. When operating the LMF90 from a single positive power supply voltage, pin 13 should be connected to a ‘‘clean’’ refer- ence voltage midway between V a and Vb. Va (Pin 14) This is the positive power supply pin. It should be bypassed with at least a 0.1 mF capacitor.

1.0 Definition of Terms

Amax: the maximum amount of gain variation within the fil- ter’s passband (See Figure 1 ). For the LMF90, A Max is nominally equal to 0.25 dB. Amin: the minimum attenuation within the notch’s stopband. (See Figure 1 ). This parameter is adjusted by programming voltage applied to pin 10 (D). Bandwidth (BW) or Passband Width: the difference in fre- quency between the notch filter’s two cutoff frequencies. Cutoff Frequency: for a notch filter, one of the two fre- quencies, f C1 and f C2 that define the edges of the pass- band. At these two frequencies, the filter has a gain equal to the passband gain. f CLK: the frequency of the clock signal that appears at the CLK pin. This frequency determines the filter’s center fre- quency. Depending on the programming voltage on pin 2 (R), f CLK will be either 33.33, 50, or 100 times the center frequency of the notch. f0 or f Notch: the center frequency of the notch filter. This frequency is measured by finding the two frequencies for which the gain b3 dB relative to the passband gain, and calculating their geometrical mean. Passband: for a notch filter, frequencies above the upper cutoff frequency (f C2 in Figure 1 ) and below the lower cutoff frequency (f C1 in Figure 1 ).

1.0 Definition of Terms (Continued)

at the edges of the notch’s stopband. tween the two stopband edges (f S2 –fS1). FIGURE 1. General Form of Notch Response

2.0 Applications Information

2.1 FUNCTIONAL DESCRIPTION

bypass capacitors and a clock (or crystal) are required. ed externally or internally with the aid of an external crystal. internal oscillator circuit. FIGURE 2. LMF90 Block Diagram

2.0 Applications Information (Continued)

2.2 PROGRAMMING PINS

The LMF90 has five control pins that are used to program the filter’s characteristics via a three-level logic scheme. In dual-supply applications, these inputs are tied to either V Vb, or GND in order to select a particular set of characteris- tics. For example, the W input (pin 1) sets the filter’s pass- band width to 0.55 f 0, 0.26 f 0 or 0.127 f 0 when the W input is connected to V a, GND, or V b, respectively. Applying V b and GND to the D input (pin 10) will set the notch depth to 40 dB or 30 dB, respectively. The R input (pin 2) is another three-level logic input, and it sets the clock-to-center-frequency ratio to 33.33:1, 50:1, or 100:1 for input voltages equal to V a, GND, or V b, respec- tively. Note that the clock frequency referred to here is the frequency at the CLK pin and at the frequency divider output (if used). This is different from the frequency at the divider’s input. LD (pin 3) sets the frequency divider’s division factor to either 716, 596, or 2 for input voltages equal to V a, GND, or V b, respectively. XLS (pin 7) enables and disables the crystal oscillator and clock divider. When XLS is connected to the positive supply, the oscillator and divider are enabled, and CLK is the output of the divider and can drive the clock inputs of other LMF90s. When XLS is connected to GND, the oscillator and divider are disabled, and the CLK pin be- comes a clock input for CMOS-level signals. Connecting XLS to the negative supply disables the oscillator and divid- er and causes CLK to operate as a TTL-level clock input. Using an external 3.579545 MHz color television crystal with the internal oscillator and divider, it is possible to build a power line frequency notch for 50 Hz or 60 Hz line frequen- cies or their second and third harmonics using the LMF90. A

60 Hz notch is shown in the Typical Application circuit on

the first page of this data sheet. Connecting LD to V a changes the notch frequency to 50 Hz. Changing the clock- to-center-frequency ratio to 50:1 results in a second-har- monic notch, and a 33:1 ratio causes the LMF90 to notch the third harmonic. Table I illustrates 18 different combinations of filter band- width, depth, and clock-to-center-frequency ratio obtained by choosing the appropriate W, D, and R programming volt- ages.

2.3 DIGITAL INPUTS AND OUTPUTS

As mentioned above, the CLK pin can serve as either an input or an output, depending on the programming voltage on XLS. When CLK is operating as a TTL input, it will oper- ate properly in both dual-supply and single-supply applica- tions, because it has two logic thresholdsÐone referred to V b, and one referred to GND. When operating as an output, CLK swings rail-to-rail (CMOS logic levels). XTAL1 and XTAL2 are the input and output pins for the internal crystal oscillator. When using the internal oscillator (XLS connected to V a), the crystal is connected between these two pins. When the internal oscillator is not used, XTAL2 should be left open. XTAL1 can be used as an input for an external CMOS-level clock signal swinging from V b to V a. The frequency of the crystal or the external clock applied to XTAL1 will be divided by the internal frequency divider as determined by programming voltage on the LD pin.

2.4 SAMPLED-DATA SYSTEM CONSIDERATIONS

Because the LMF90 uses switched-capacitor techniques, its performance differs in several ways from non-sampled (con- tinuous) circuits. The analog signal at the input to the inter- nal bandpass filter (pin 12) is sampled during each clock cycle, and, since the output voltage can change only once every clock cycle, the result is a discontinuous output signal. The bandpass output takes the form of a series of voltage ‘‘steps’’, as shown in Figure 3 . The steps are smaller when the clock frequency is much greater than the signal frequen- cy. Switched-capacitor techniques are used to set the summing amplifier’s gain. Its input and feedback ‘‘resistors’’ are actu- ally made from switches and capacitors. Two sets of these ‘‘resistors’’ are alternated during each clock cycle. Each time these gain-setting components are switched, there will be no feedback connected to the op amp for a short period of time (about 50 ns). This generates very low-amplitude output signals at f CLK a fIN,f CLK b fIN,2f CLK a fIN, etc. The amplitude of each of these intermodulation compo- nents will typically be at least 70 dB below the input signal amplitude and well beyond the spectrum of interest. TABLE I. Operation of LMF90 Programming Pins. Values given are for nominal levels of attenuation. RV b (fCLK/f0 e 100) GND (f CLK/f0 e 50) V a (fCLK/f0 e 33.33) DW Amin BW/f0 SBW/f0 Amin BW/f0 SBW/f0 Amin BW/f0 SBW/f0(dB) (dB) (dB)

sufficient attenuation of unwanted high-frequency signals. FIGURE 3. Output waveform of a switched-capacitor FIGURE 4. Using a simple passive low-pass filter to prevent aliasing in the presence of high-frequency input signals.

volts. The other kind of noise is digital clock feedthrough. high compared to the signal frequency that it is unimportant. more pronounced at elevated operating temperatures. close to 50% for best performance. similar to the switched-capacitor circuit shown in Figure 5 . input impedance doesn’t significantly affect gain. ance will be 83.3 k X with a 1.5 MHz filter clock. FIGURE 5. Simplified LMF90 bandpass section input the input impedance appears to be resistive.

2.5 POWER SUPPLY AND CLOCK OPTIONS

through of power supply noise into the filter’s signal path.

FIGURE 6. Dual supply; external CMOS-level clock. Internal frequency divider disabled. FIGURE 7. Dual supply; TTL-level clock. Internal frequency divider disabled.

FIGURE 8. Dual Supply; external CMOS-level clock. Internal frequency divider enabled. Output of logic divider available on pin 6. FIGURE 9. Dual supply; internal crystal clock oscillator. Internal frequency divider enabled. Output of logic divider available on pin 6.

FIGURE 10. Single a5V supply; external TTL-level clock. Internal frequency divider disabled. FIGURE 11. Single a5V supply; external CMOS-level clock. TL/H/10354–15 Internal frequency divider enabled. Output of logic divider available on pin 6.

FIGURE 12. Single a10V supply; external TTL-level clock. Internal frequency divider disabled. FIGURE 13. Single a10V supply; external CMOS-level clock. Internal frequency divider disabled.

FIGURE 14. Single a10V supply; external CMOS-level clock. Internal frequency divider enabled. Output of logic divider available on pin 6. FIGURE 15. Single a5V or a10V supply; internal crystal clock oscillator. Internal frequency divider enabled. Output of logic divider available on pin 6.

FIGURE 16. 50 Hz and 150 Hz Notch Filter

Physical Dimensions inches (millimeters)

14 Lead Ceramic Dual-In-Line Package (J)

Order Number LMF90CIJ, LMF90CMJ, LMF90CMJ/883 or LMF90CCJ 14 Lead Molded Package, Small Outline, 0.300 × Wide Order Number LMF90CCWM or LMF90CIWM

LMF90 4th-Order Elliptic Notch Filter Physical Dimensions inches (millimeters) (Continued)

14 Lead Molded Dual-In-Line Package (N)

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