LMF100CIWM

LMF100 NSC | Alldatasheet

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Technical content

Features

n Wide 4V to 15V power supply range n Operation up to 100 kHz n Low offset voltage: typically (50:1 or 100:1 mode): Vos1= ±5m V Vos2 = ±15 mV Vos3 = ±15 mV n Low crosstalk −60 dB n Clock to center frequency ratio accuracy±0.2% typical n f0 x Q range up to 1.8 MHz n Pin-compatible with MF10 4th Order 100 kHz Butterworth Lowpass Filter Connection Diagram LMCMOS ™ is a trademark of National Semiconductor Corporation. DS005645-2 DS005645-3 Surface Mount and Dual-In-Line Package DS005645-18 Top View Order Number LMF100CCN or LMF100CIWM See NS Package Number N20A or M20B July 1999 LMF100 High Performance Dual Switched Capacitor Filter © 1999 National Semiconductor Corporation DS005645 www.national.com

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. (Note 14) Supply Voltage (V + −V −) 16V Voltage at Any Pin V + + 0.3V V− − 0.3V Input Current at Any Pin (Note 2) 5 mA Package Input Current (Note 2) 20 mA Power Dissipation (Note 3) 500 mW Storage Temperature 150˚C ESD Susceptability (Note 11) 2000V Soldering Information N Package: 10 sec. 260˚C J Package: 10 sec. 300˚C Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” (Appendix D) for other methods of soldering surface mount devices. Operating Ratings(Note 1) Temperature Range T MIN ≤ TA ≤ TMAX LMF100CCN 0˚C ≤ TA ≤ +70˚C LMF100CIWM −40˚C ≤ TA ≤ +85˚C Supply Voltage 4V ≤ V+ −V − ≤ 15V

Electrical Characteristics

The following specifications apply for Mode 1, Q= 10 (R1 = R 3 = 100k, R2 = 10k), V+ = +5V and V− = −5V unless otherwise specified.Boldface limits apply for TMIN to TMAX ; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions LMF100CCN LMF100CIWM UnitsTypical (Note 8) Tested Limit (Note 9) Design Limit (Note 10) Typical (Note 8) Tested Limit (Note 9) Design Limit (Note 10) Is Maximum Supply Current f CLK = 250 kHz 9 13 13 9 13 mA No Input Signal f0 Center Frequency MIN 0.1 0.1 Hz Range MAX 100 100 kHz fCLK Clock Frequency MIN 5.0 5.0 Hz Range MAX 3.5 3.5 MHz fCLK /f0 Clock to Center Frequency Ratio Deviation VPin12 = 5V or 0V fCLK = 1 MHz Q Error (MAX) (Note 4) Q = 10, Mode 1 VPin12 = 5V or 0V fCLK = 1 MHz H OBP Bandpass Gain at f0 fCLK = 1 MHz 0 ±0.4 ±0.4 0 ±0.4 dB H OLP DC Lowpass Gain R 1 = R 2 = 10k 0 ±0.2 ±0.2 0 ±0.2 dB fCLK = 250 kHz VOS1 DC Offset Voltage (Note 5) fCLK = 250 kHz ±5.0 ±15 ±15 ±5.0 ±15 mV VOS2 DC Offset Voltage (Note 5) fCLK = 250 kHz S A/B = V+ ±30 ±80 ±80 ±30 ±80 mV SA/B = V− ±15 ±70 ±70 ±15 ±70 mV VOS3 DC Offset Voltage (Note 5) fCLK = 250 kHz ±15 ±40 ±60 ±15 ±60 mV Crosstalk (Note 6) A Side to B Side or −60 −60 dB B Side to A Side Output Noise (Note 12) f CLK = 250 kHz N 40 40 20 kHz Bandwidth BP 320 320 µV 100:1 Mode LP 300 300 Clock Feedthrough (Note 13) f CLK = 250 kHz 100:1 Mode 6 6 mV VOUT Minimum Output R L = 5k +4.0 ±3.8 ±3.7 +4.0 ±3.7 V Voltage Swing (All Outputs) −4.7 −4.7 V (All Outputs) −4.6 −4.6 GBW Op Amp Gain BW Product 5 5 MHz SR Op Amp Slew Rate 20 20 V/µs I sc Maximum Output Short Source (All Outputs) 12 12 mA Circuit Current (Note 7) Sink 45 45 mA www.national.com 2

Electrical Characteristics(Continued) The following specifications apply for Mode 1, Q= 10 (R1 = R 3 = 100k, R2 = 10k), V+ = +5V and V− = −5V unless otherwise specified.Boldface limits apply for TMIN to TMAX ; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions LMF100CCN LMF100CIWM UnitsTypical (Note 8) Tested Limit (Note 9) Design Limit (Note 10) Typical (Note 8) Tested Limit (Note 9) Design Limit (Note 10) IIN Input Current on Pins: 4, 5, 10 10 µA 6, 9, 10, 11, 12, 16, 17 The following specifications apply for Mode 1, Q= 10 (R1 = R 3 = 100k, R2 = 10k), V+ = +2.50V and V− = −2.50V unless oth- erwise specified.Boldface limits apply for TMIN to TMAX ; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions LMF100CCN LMF100CIWM Units Typical (Note 8) Tested Limit (Note 9) Design Limit (Note 10) Typical (Note 8) Tested Limit (Note 9) Design Limit (Note 10) Is Maximum Supply Current fCLK = 250 kHz No Input Signal 81 2 12 8 12 mA f0 Center Frequency MIN 0.1 0.1 Hz Range MAX 50 50 kHz fCLK Clock Frequency MIN 5.0 5.0 Hz Range MAX 1.5 1.5 MHz fCLK /f0 Clock to Center V Pin12 = 2.5V or 0V ±0.2 ±1 ±1 ±0.2 ±1 % Frequency Ratio Deviation f CLK = 1 MHz Q Error (MAX) Q = 10, Mode 1 (Note 4) V Pin12 = 5V or 0V ±0.5 ±5 ±8 ±0.5 ±8 % fCLK = 1 MHz H OBP Bandpass Gain at f0 fCLK = 1 MHz 0 ±0.4 ±0.5 0 ±0.5 dB H OLP DC Lowpass Gain R 1 = R 2 = 10k 0 ±0.2 ±0.2 0 ±0.2 dB fCLK = 250 kHz VOS1 DC Offset Voltage (Note 5) f CLK = 250 kHz ±5.0 ±15 ±15 ±5.0 ±15 mV VOS2 DC Offset Voltage (Note 5) f CLK = 250 kHz S A/B = V+ ±20 ±60 ±60 ±20 ±60 mV SA/B = V− ±10 ±50 ±60 ±10 ±60 mV VOS3 DC Offset Voltage (Note 5) f CLK = 250 kHz ±10 ±25 ±30 ±10 ±30 mV Crosstalk (Note 6) A Side to B Side or −65 −65 dB B Side to A Side Output Noise (Note 12) f CLK = 250 kHz N 25 25 20 kHz Bandwidth BP 250 250 µV 100:1 Mode LP 220 220 Clock Feedthrough (Note 13) f CLK = 250 kHz 100:1 Mode 2 2 mV VOUT Minimum Output R L = 5k +1.6 ±1.5 ±1.4 +1.6 ±1.4 V Voltage Swing (All Outputs) −2.2 −2.2 (All outputs) −2.1 −2.1 GBW Op Amp Gain BW Product 5 5 MHz SR Op Amp Slew Rate 18 18 V/µs I sc Maximum Output Short Circuit Source (All Outputs) 10 10 mA Current (Note 7) Sink 20 20 mA www.national.com3

Logic Input Characteristics Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Parameter Conditions LMF100CCN LMF100CIWM Units Typical Tested Design Typical Tested Design (Note 8) Limit Limit (Note 8) Limit Limit (Note 9) (Note 10) (Note 9) (Note 10) CMOS Clock MIN Logical “1” V + = +5V, V− = −5V, +3.0 +3.0 +3.0 V Input Voltage MAX Logical “0” V LSh = 0V −3.0 −3.0 −3.0 V MIN Logical “1” V + = +10V, V− = 0V, +8.0 +8.0 +8.0 V MAX Logical “0” V LSh = +5V +2.0 +2.0 +2.0 V TTL Clock MIN Logical “1” V + = +5V, V− = −5V, +2.0 +2.0 +2.0 V Input Voltage MAX Logical “0” V LSh = 0V +0.8 +0.8 +0.8 V MIN Logical “1” V + = +10V, V− = 0V, +2.0 +2.0 +2.0 V MAX Logical “0” V LSh = 0V +0.8 +0.8 +0.8 V Input Voltage MAX Logical “0” V LSh = 0V −1.5 −1.5 −1.5 V MIN Logical “1” V + = +5V, V− = 0V, +4.0 +4.0 +4.0 V MAX Logical “0” V LSh = +2.5V +1.0 +1.0 +1.0 V TTL Clock MIN Logical “1” V + = +5V, V− = 0V, +2.0 +2.0 +2.0 V Input Voltage MAX Logical “0” V LSh = 0V, VD Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in- tended to be functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not op- erated under the listed test conditions. Note 2:When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA. Note 3:The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX −T A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125˚C, and the typical junction-to-ambient thermal resistance of the LMF100CIN when board mounted is 55˚C/W. For the LMF100CIWM this number is 66˚C/W. Note 4:The accuracy of the Q value is a function of the center frequency (f0). This is illustrated in the curves under the heading “Typical Peformance Characteristics”. Note 5:Vos1,V os2, and Vos3 refer to the internal offsets as discussed in the Applications Information section 3.4. Note 6:Crosstalk between the internal filter sections is measured by applyinga1V RMS 10 kHz signal to one bandpass filter section input and grounding the input of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and the 1 VRMS input signal of the other section. Note 7:The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Note 8:Typicals are at 25˚C and represent most likely parametric norm. Note 9:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10:Design limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) but are not 100% tested. Note 11:Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 12:In 50:1 mode the output noise is 3 dB higher. Note 13:In 50:1 mode the clock feedthrough is 6 dB higher. Note 14:A military RETS specification is available upon request. www.national.com 4

Typical Performance Characteristics Power Supply Current vs Power Supply Voltage DS005645-40 Power Supply Current vs Temperature DS005645-41 Output Swing vs Supply Voltage DS005645-42 Positive Output Swing vs Temperature DS005645-43 Negative Output Swing vs Temperature DS005645-44 Positive Output Voltage Swing vs Load Resistance DS005645-45 Negative Output Voltage Swing vs Load Resistance DS005645-46 fCLK /f0 Ratio vs Q DS005645-47 fCLK /f0 Ratio vs Q DS005645-48 fCLK /f0 Ratio vs fCLK DS005645-49 fCLK /f0 Ratio vs fCLK DS005645-50 fCLK /f0 Ratio vs fCLK DS005645-51 www.national.com5

Typical Performance Characteristics(Continued) fCLK /f0 Ratio vs fCLK DS005645-52 fCLK /f0 Ratio vs Temperature DS005645-53 fCLK /f0 Ratio vs Temperature DS005645-54 Q Deviation vs Clock Frequency DS005645-55 Q Deviation vs Clock Frequency DS005645-56 Q Deviation vs Clock Frequency DS005645-57 Q Deviation vs Clock Frequency DS005645-58 Q Deviation vs Temperature DS005645-59 Q Deviation vs Temperature DS005645-60 www.national.com 6

Typical Performance Characteristics(Continued) LMF100 System Block Diagram Maximum f 0 v sQa t Vs = ±7.5V DS005645-61 Maximum f 0 v sQa t Vs = ±5.0V DS005645-62 Maximum f 0 v sQa t Vs = ±2.5V DS005645-63 DS005645-1 www.national.com7

LP(1,20), BP(2,19), N/AP/HP(3,18) The second order lowpass, bandpass and notch/allpass/highpass outputs. These outputs can typically swing to within 1V of each supply when drivinga5k Ω load. For optimum performance, capacitive loading on these outputs should be minimized. For signal frequencies above 15 kHz the capacitance loading should be kept below 30 pF. INV(4,17) The inverting input of the summing opamp of each filter. These are high impedance inputs. The non-inverting input is internally tied to AGND so the opamp can be used only as an inverting amplifier. S1(5,16) S1 is a signal input pin used in modes 1b, 4, and 5. The input impedance is 1/f CLK x 1 pF. The pin should be driven with a source impedance of less than 1 kΩ .I f S1 is not driven with a signal it should be tied to AGND (mid-supply). S A/B(6) This pin activates a switch that connects one of the inputs of each filter’s second summer either to AGND (S A/B tied to V−)o rt ot h e lowpass (LP) output (SA/B tied to V+). This offers the flexibility needed for configuring the filter in its various modes of operation. V A +(7) (Note 15) This is both the analog and digital positive supply. VD +(8) (Note 15) This pin needs to be tied to V+ except when the device is to operate on a single 5V supply and a TTL level clock is applied. For 5V, TTL operation, V D + should be tied to ground (0V). VA −(14), VD −(13) Analog and digital negative supplies. VA −and VD − should be derived from the same source. They have been brought out separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and bypassed with a single capacitor. LSh(9) Level shift pin. This is used to accommodate various clock levels with dual or single supply operation. With dual ±5V supplies and CMOS ( ±5V) or TTL (0V–5V) clock levels, LSh should be tied to system ground. For 0V–10V single supply operation the AGND pin should be biased at +5V and the LSh pin should be tied to the system ground for TTL clock levels. LSh should be biased at +5V for ±5V CMOS clock levels. The LSh pin is tied to system ground for±2.5V operation. For single 5V operation the LSh and V D + pins are tied to system ground for TTL clock levels. CLK(10,11) Clock inputs for the two switched capacitor filter sections. Unipolar or bipolar clock levels may be applied to the CLK inputs according to the programming voltage applied to the LSh pin. The duty cycle of the clock should be close to 50% , especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal opamps to settle, which yields optimum filter performance. 50/100(12) (Note 15) By tying this pin to V + a 50:1 clock to filter center frequency ratio is obtained. Tying this pin at mid-supply (i.e., system ground with dual supplies) or to V − allows the filter to operate at a 100:1 clock to center frequency ratio. AGND(15) This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a “clean” ground must be provided. Note 15:This device is pin-for-pin compatible with the MF10 except for the following changes: 1. Unlike the MF10, the LMF100 has a single positive supply pin (VA+). 2. On the LMF100 VD + is a control pin and is not the digital positive supply as on the MF10. 3. Unlike the MF10, the LMF100 does not support the current limiting mode. When the 50/100 pin is tied to V− the LMF100 will remain in the 100:1 mode. www.national.com 8

1.0 Definitions of Terms

LMF100, and is the frequency of maximum bandpass gain. observed as the frequency of a notch at the allpass output. filter responses as shown inFigure 6. where QZ = Q for an all-pass response. H OBP :the gain (in V/V) of the bandpass output at f= f0. tities below are used in place of HON . H ON1 :the gain (in V/V) of the notch output as f→ 0 Hz. H ON2 :the gain (in V/V) of the notch output as f→ fCLK /2. FIGURE 1. 2nd-Order Bandpass Response

1.0 Definitions of Terms(Continued)

FIGURE 2. 2nd-Order Low-Pass Response FIGURE 3. 2nd-Order High-Pass Response

FIGURE 4. 2nd-Order Notch Response FIGURE 5. 2nd-Order All-Pass Response

FIGURE 6. Response of various 2nd-order filters as a function of Q. Gains and center frequencies are normalized to unity.

2.0 Modes of Operation

Note:VIN should be driven from a low impedance (<1k Ω ) source. FIGURE 7. MODE 1 FIGURE 8. MODE 1a

2.0 Modes of Operation(Continued)

FIGURE 9. MODE 1b FIGURE 10. MODE 2

problem, connect a small capacitor (10 pF−100 pF) across R4 to provide some phase lead. FIGURE 11. MODE 3

unacceptable, Mode 5 is recommended. FIGURE 12. MODE 3a

FIGURE 13. MODE 4 FIGURE 14. MODE 5 FIGURE 15. MODE 6a

FIGURE 16. MODE 6b FIGURE 17. MODE 6c

FIGURE 18. MODE 7

Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios. 6b H OLP1 = + 1 2 Yes Single pole.

3.0 Applications Information

ter Q and gain are set by external resistor ratios.

(Continued)

3.1 DESIGN EXAMPLE

In order to design a filter using the LMF100, we must define the necessary values of three parameters for each second-order section: f 0, the filter section’s center frequency; H 0, the passband gain; and the filter’s Q. These are deter- mined by the characteristics required of the filter being de- signed. As an example, let’s assume that a system requires a fourth-order Chebyshev low-pass filter with 1 dB ripple, unity gain at dc, and 1000 Hz cutoff frequency. As the system or- der is four, it is realizable using both second-order sections of an LMF100. Many filter design texts (and National’s Switched Capacitor Filter Handbook) include tables that list the characteristics (f 0 and Q) of each of the second-order fil- ter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined above, such a table yields the following characteristics: f 0A = 529 Hz Q A = 0.785 f0B = 993 Hz Q B = 3.559 For unity gain at dc, we also specify: H 0A = 1 H 0B = 1 The desired clock-to-cutoff-frequency ratio for the overall fil- ter of this example is 100 and a 100 kHz clock signal is avail- able. Note that the required center frequencies for the two second-order sections will not be obtainable with clock-to-center-frequency ratios of 50 or 100. It will be nec- essary to adjust externally. FromTable 1, we see that Mode 3 can be used to produce a low-pass filter with resistor-adjustable center fre- quency. In most filter designs involving multiple second-order stages, it is best to place the stages with lower Q values ahead of stages with higher Q, especially when the higher Q is greater than 0.707. This is due to the higher relative gain at the cen- ter frequency of a higher-Q stage. Placing a stage with lower Q ahead of a higher-Q stage will provide some attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage A has the lower Q (0.785) so it will be placed ahead of the other stage. For the first section, we begin the design by choosing a con- venient value for the input resistance: R 1A = 20k. The abso- lute value of the passband gain HOLPA is made equal to 1 by choosing R4A such that: R4A = −H OLPA R 1A = R 1A = 20k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio, we find R 2A by: The resistors for the second section are found in a similar fashion: The complete circuit is shown inFigure 19for split±5V power supplies. Supply bypass capacitors are highly recommended. www.national.com21

3.0 Applications Information(Continued)

FIGURE 19. Fourth-order Chebyshev low-pass filter from example in 3.1. ±5V power supply. 0V–5V TTL or±5V CMOS logic levels. FIGURE 20. Fourth-order Chebyshev low-pass filter from example in 3.1. Single +10V power supply. 0V–5V TTL logic levels. Input signals should be referred to half-supply or applied through a coupling capacitor.

3.2 SINGLE SUPPLY OPERATION

lated) and bypassed with 0.1 µF.

3.3 DYNAMIC CONSIDERATIONS

3.4 OFFSET VOLTAGE

described in the following expressions. FIGURE 21. Three Ways of Generating V+/2 for Single-Supply Operation

Figure 24. This allows adjustment of VOS1 , which will have FIGURE 22. Offset Voltage Sources

3.5 SAMPLED DATA SYSTEM CONSIDERATIONS

FIGURE 23. Second-Order Notch Filter FIGURE 24. Method for Trimming VOS

tio with external resistors. FIGURE 25. The Sampled-Data Output Waveform

Physical Dimensionsinches (millimeters) unless otherwise noted Small Outline Package Order Number LMF100CIWM Molded Dual-In-Line Package (N) Order Number LMF100CCN www.national.com27

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com LMF100 High Performance Dual Switched Capacitor Filter National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.