LMC835

LMC835 NSC | Alldatasheet

Document overview

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Technical content

Features

Y No volume controls required Y Three-wire interface Y 14 bands, 25 steps each Y g12 dB or g6 dB gain ranges Y Low noise and distortion Y TTL, CMOS logic compatible

Applications

TL/H/6753–1 Top View Order Number LMC835N See NS Package N28B Molded Chip Carrier Package TL/H/6753–26 Top View Order Number LMC835V See NS Package V28A C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/H/6753–2

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage, V DDbVSS 18V Allowable Input Voltage (Note 1) V SSb0.3V to V DDa0.3V Storage Temperature, T stg b60§Ct o a150§C Lead Temperature (Soldering, 10 sec), N Pkg a260§C Lead Temperature, V Pkg Vapor Phase (60 sec) a215§C Infrared (15 sec) a220§C Operating Ratings Supply Voltage, V DDbVSS 5V to 16V Digital Ground (Pin 13) V SS to V DD Digital Input (Pins 14, 15, 16) V SS to V DD Analog Input (Pins 1, 2, 3, 4, 25, 26, 27) (Note 1) V SS to V DD Operating Temperature, T opr b40§Ct o a85§C Electrical Characteristics (Note 2) V DDe7.5V, V SSeb7.5V, A.GND e0V LOGIC SECTION Tested Design UnitSymbol Parameter Test Conditions Typ Limit Limit (Limit)(Note 3) (Note 4) IDDL Supply Current Pins 14, 15, 16 are 0V 0.01 0.5 0.5 mA (Max) ISSL Pins 14, 15, 16 are 0V 0.01 0.5 0.5 mA (Max) IDDH Pins 14, 15, 16 are 5V 1.3 5 5 mA (Max) ISSH Pins 14, 15, 16 are 5V 0.9 5 5 mA (Max) VIH High-Level Input Voltage @Pins 14, 15, 16 1.8 2.3 2.5 V (Min) VIL Low-Level Input Voltage @Pins 14, 15, 16 0.9 0.6 0.4 V (Max) fo Clock Frequency @Pin 14 2000 500 500 kHz (Max) tw(STB) Width of STB Input See Figure 1 0.25 1 1 ms (Min) tsetup Data Setup Time See Figure 1 0.25 1 1 ms (Min) thold Data Hold Time See Figure 1 0.25 1 1 ms (Min) tcs Delay from Rising Edge of CLOCK See Figure 1 0.25 1 1 ms (Min) to STB IIN Input Current @Pins 14, 15, 16 0V kVINk5V g0.01 g1 mA (Max) CIN Input Capacitance @Pins 14, 15, 16 f e1 MHz 5 pF Note 1: Pins 2, 3 and 26 have a maximum input voltage range of g22V for the typical application shown in Figure 7 . circuit, Figures 3 and 4 . Note 3: Guaranteed and 100% production tested. Note 4: Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels. Timing Diagram TL/H/6753–3 Note: To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time. FIGURE 1

Electrical Characteristics (Note 2) V DDe7.5V, V SSeb7.5V, D.GND eA.GNDe0V SIGNAL PATH SECTION Tested Design UnitSymbol Parameter Test Conditions Typ Limit Limit (Limit)(Note 3) (Note 4) EA Gain Error A Ve0d B @ g 12 dB Range 0.1 0.5 0.5 dB (Max) AVe0d B @ g 6 dB Range 0.1 1 1 dB (Max) AVeg1d B @ g dB Range 0.1 0.5 0.6 dB (Max) (R5b or R 5c is ON) AVeg2d B @ g 12 dB Range 0.1 0.5 0.6 dB (Max) (R4b or R 4c is ON) AVeg3d B @ g 12 dB Range 0.1 0.5 0.6 dB (Max) (R3b or R 3c is ON) AVeg4d B @ g 12 dB Range 0.1 0.5 0.7 dB (Max) (R2b or R 2c is ON) AVeg5d B @ g12 dB Range 0.1 0.5 0.7 dB (Max) (R1b or R 1c is ON) AVeg9d B @ g 12 dB Range 0.2 1 1.3 dB (Max) (R0b or R 0c is ON) THD Total Harmonic A Ve0d B @ g12 dB Range 0.0015 % Distortion V INe4Vrms,f e1 kHz AVe12 dB @ g 12 dB Range VINe1Vrms,f e1 kHz 0.01 0.1 % (Max) VINe1Vrms,f e20 kHz 0.1 0.5 % (Max) AVeb12 dB @ g12 dB Range VINe4Vrms,f e1 kHz 0.01 0.1 % (Max) VINe4Vrms,f e20 kHz 0.1 0.5 % (Max) VO Max Maximum Output Voltage A Ve0d B @ g12 dB Range 5.5 5.1 5 Vrms (Min) THD k1%, f e1 kHz S/N Signal to Noise Ratio A Ve0d B @ g12 dB Range 114 dB Vrefe1V rms AVe 12 dB @ g12 dB Range 106 dB Vrefe1Vrms AVeb12 dB @ g12 dB Range 116 dB Vrefe1Vrms ILEAK Leakage Current A Ve0d B @ g12 dB Range (All internal switches are OFF) Pin 2 a3, Pin 26 500 nA (Max) Pin 5 EPin 11, Pin 18 EPin 24 50 nA (Max) test circuit, Figures 3 and 4 . Note 3: Guaranteed and 100% production tested. Note 4: Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels. Timing Diagrams TL/H/6753–4 Note: To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time. FIGURE 2

DATA I (Band Selection) D7 D6 D5 D4 D3 D2 D1 D0 H XLLLLLL H XLLLLLH H XLLLLHL H XLLLLH H HXLLLHLL HXLLLHLH HXLLLHHL HX L L LHHH H XLLHLLL HXLLHLLH HXLLHLHL HXLLHLHH H XLLH HLL HXLLHHLH HX L LHHHL HX L LHHHH H X L H Valid Binary Input H X H L Valid Binary Input H X H H Valid Binary Input uuuu w Band Code x jklm j DATA 1 k Don’t Care l Ch A g6 dB/ g12 dB Range m Ch B g6 dB/ g12 dB Range (Ch A: Band 1 E7, Ch B: Band 8 E14) Ch A g 12 dB Range, Ch B g 12 dB Range, No Band Selection Ch A g 12 dB Range, Ch B g 12 dB Range, Band 1 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 2 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 3 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 4 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 5 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 6 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 7 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 8 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 9 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 10 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 11 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 12 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 13 Ch A g 12 dB Range, Ch B g 12 dB Range, Band 14 Ch A g 12 dB Range, Ch B g 12 dB Range, No Band Selection Ch A g 12 dB Range, Ch B g 6 dB Range, Band 1 E14 Ch A g 6 dB Range, Ch B g 12 dB Range, Band 1 E14 Ch A g 6 dB Range, Ch B g 6 dB Range, Band 1 E14 This is the gain if the g12 dB range is selected by DATA I. If the g6d B range is selected, then the values shown must be approximately halved. See the characteristics curves for more exact data. DATA II (Gain Selection) D7 D6 D5 D4 D3 D2 D1 D0 Flat L X L L L L L L 1 dB Boost L H H L L L L L 2 dB Boost L H L H L L L L 3 dB Boost L H L L H L L L 4 dB Boost L H L L L H L L 5 dB Boost L H L L L L H L 6 dB Boost L H L H L L H L 7 dB Boost L H H L H L H L 8 dB Boost L H L H L H H L 9 dB Boost L H L L L L L H 10 dB Boost L H H L H L L H 11 dB Boost L H H L H H L H 12 dB Boost L H H L H H H H $ 1d B E12 dB Cut L L Valid Above Input uu w Gain Code x no n DATA II o Boost/Cut

Typical Performance Characteristics (Continued) Maximum Output Voltage vs Supply Voltage Maximum Output Voltage vs Temperature Nominal Resistor vs Temperature Distortion vs Frequency @ g 12 dB Range Distortion vs Frequency @ g6 dB Range Distortion vs Output Voltage @ g 12 dB Range Distortion vs Output Voltage @ g6 dB Range Gain vs Frequency @ g 12 dB Range (Boost) Gain vs Frequency @ g 12 dB Range (Cut) Gain vs Frequency @ g6 dB Range (Boost) Gain vs Frequency @ g6 dB Range (Cut) Gain vs Temperature TL/H/6753–10

FIGURE 9. 12-Band Equalizer

FIGURE 10. Tuned Circuit for

12 Band Equalizer Application

FIGURE 11. Single Supply Stereo Equalizer

Typical Applications (Continued) Sample Subroutine Program for Figure 14 , LMC835-COP404L CPU Interface HEX CODE LABEL MNEMONICS COMMENTS 3F LMC835: LBI 3F ;POINT TO RAMADDRESS 3F

05 SEND LD ;RAMDATA TO A

22 SC ; SET CARRY

335F OGI ;SET PORT G 4 1111, OPEN THE AND GATES 4F XAS ;SWAP A AND SIO, CLOCK START

05 LD ;RAMDATA TO A, MAKE SURE A 4 DATA

07 XDS ;SWAP A AND RAMDATA, RAMADDRESS 4RAMADDRESS11

05 LD ;RAMDATA TO A

4F XAS ;SWAP A AND SIO

05 LD ;RAMDATA TO A, MAKE SURE A 4NEWDATA

32 RC ;RESET CARRY

4F XAS ;SWAP A AND SIO, CLOCK STOP 335D OGJ 13 ;SET PORT G 41101, MAKE STROBE LOW 335B OGI 11 ;SET PORT G 41011, MAKE STROBE HIGH, CLOSE THE GATES 4E CBA ;BD TO A

43 AISC 3 ;RAMADDRESS

48 RET

80 JP SEND

3C DATA ;GAIN DATA D4 1D7 3D DATA ;GAIN DATA D0 1D3 3E DATA ;BAND DATA D4 1D7 3F DATA ;BAND DATA D0 1D3 Application Hints SWITCHING NOISE The LMC835 uses CMOS analog switches that have small leakages (less than 50 nA). When a band is selected for flat gain, all the switches in that band are open and the resona- tor circuit is not connected to the LMC835 resistor network. It is only in the flat mode that the small leakage currents can cause problems. The input to the resonator circuit is usually a capacitor and the leakage currents will slowly charge up this capacitor to a large voltage if there is no resistive path to limit it. When the band is set to any value other than flat, the charge on the capacitor will be discharged by the resis- tor network and there will be a transient at the output. To limit the size of this transient, R LEAK is necessary. HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE CURRENT (Refer to Figures 7 and 8 ) To avoid switching noise due to leakage currents when changing the gain, it is recommended to put R LEAKe 100 kX between Pin 3 and Pin 5Ð11 each, Pin 26 and Pin 12Ð 24 each. The resistor limits the voltage that the capacitor can charge to, with minimal effects on the equalization. The frequency response change due to R LEAK are shown in Fig- ure 15 . The gain error is only 0.2 dB and Q error is only 5% at 12 dB boost or cut. SIMPLE WORD GENERATOR (Figure 6) Circuit operation revolves around an MM74HC165 parallel- in/serial-out shift register. Data bits D0 through D7 are ap- plied to the parallel of the MM74HC165 from 8 toggle switches. The bits are shifted out to the DATA input of the LMC835 in sync with the clock. When all data bits have been loaded, CLOCK is inhibited and a STROBE pulse is generated: this sequence is initiated by a START pulse. LMC835-COP404L CPU INTERFACE (Refer to Figure 14 ) The diagram shows AND gates between the COP and the LMC835. These permit G2 to inhibit the CLOCK and DATA lines (SK and SO) during a STROBE (G1) pulse. This func- tion may also be implemented in software. As shown in Fig- ure 2 , the data groups are shifted in D0 first. Data is loaded on positive clock edges. POWER SUPPLIES These applications show LM317/337 regulators for the g7.5V supplies for the LMC835. Since the latter draws only 5 mA max., 1k series dropping resistors from the g15V op amp supply and a pair of 7.5V zeners and bypass caps will also suffice.

Physical Dimensions inches (millimeters) Order Number LMC835N

LMC835 Digital Controlled Graphic Equalizer Physical Dimensions inches (millimeters) (Continued) Order Number LMC835V LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd. 2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16 P.O. Box 58090 D-82256 F 4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999 Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998 Fax: (043) 299-2500 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.