LMC6041_14 NSC | Alldatasheet
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www.ti.com SNOS610E –DECEMBER 1994–REVISED MARCH 2013 LMC6041CMOS SingleMicropowerOperationalAmplifier Check forSamples: LMC6041 1FEATURES DESCRIPTION Ultra-lowpower consumptionand low input-leakage 2• Low Supply Current: 14 μA (Typ) currentare thehallmarksoftheLMC6041. Providing• Operates from 4.5Vto15.5VSingleSupply inputcurrentsofonly2 fA typical,theLMC6041 can
- UltraLow InputCurrent: 2 fA (Typ) operate from a singlesupply,has output swing extendingto each supplyrail,and an inputvoltage• Rail-to-RailOutput Swing rangethatincludesground.• InputCommon-Mode Range IncludesGround The LMC6041 isidealforuse in systems requiring ultra-lowpower consumption. In addition,theAPPLICATIONS insensitivitytolatch-up,highoutputdrive,and output• BatteryMonitoringand Power Conditioning swing to ground withoutrequiringexternalpull-down
- Photodiode and InfraredDetectorPreamplifier resistorsmake it idealfor single-supplybattery- powered systems.• SiliconBased Transducer Systems
- Hand-Held AnalyticInstruments OtherapplicationsfortheLMC6041 includebarcode reader amplifiers,magnetic and electricfield• pH Probe BufferAmplifier detectors,and hand-heldelectrometers.• Fireand Smoke DetectionSystems This deviceisbuiltwithTI'sadvanced Double-Poly• Charge AmplifierforPiezoelectricTransducers Silicon-GateCMOS process. See theLMC6042 fora dual,and theLMC6044 fora quad amplifierwiththesefeatures. Connection Diagrams Top View Figure1. 8-PinSOIC or PDIP Package See Package Number D0008A or P0008E Figure2. Low-Leakage Sample and Hold Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1994–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNOS610E –DECEMBER 1994–REVISED MARCH 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) DifferentialInputVoltage ±SupplyVoltage SupplyVoltage(V+ − V−) 16V OutputShortCircuittoV− See (3) OutputShortCircuittoV+ See (4) Lead Temperature (Soldering,10 sec.) 260°C StorageTemperatureRange −65°C to+150°C JunctionTemperature 110°C ESD Tolerance(5) 500V CurrentatInputPin ±5 mA CurrentatOutputPin ±18 mA CurrentatPower SupplyPin 35 mA VoltageatInput/OutputPin (V+)+ 0.3V,(V−)− 0.3V Power Dissipation See (6) (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Operatingconditionsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notensurespecificperformancelimits.Forensuredspecificationsand test conditions,see theElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) Appliestobothsingle-supplyand split-supplyoperation.Continuousshortcircuitoperationatelevatedambienttemperaturecan resultin exceedingthemaximum allowedjunctiontemperatureof110°C. Outputcurrentsinexcessof±30 mA overlongtermmay adversely affectreliability. (4) Do notconnectoutputtoV+ when V+ isgreaterthan13V orreliabilitymay be adverselyaffected. (5) Human body model,1.5kΩ inserieswith100 pF. (6) The maximum power dissipationisa functionofTJ(max),θJA,and TA.The maximum allowablepower dissipationatany ambient temperatureisPD = (TJ(max)− TA)/θJA. OperatingRatings TemperatureRange LMC6041AI, LMC6041I −40°C ≤ TJ ≤ +85°C SupplyVoltage 4.5V≤ V+ ≤ 15.5V Power Dissipation See (1) ThermalResistance(θJA)(2) 8-PinPDIP package 101°C/W 8-PinSOIC package 165°C/W (1) Foroperatingatelevatedtemperaturesthedevicemust be deratedbased on thethermalresistanceθJA withPD = (TJ − TA)/θJA. (2) Allnumbers applyforpackagessoldereddirectlyintoa PC board.
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www.ti.com SNOS610E –DECEMBER 1994–REVISED MARCH 2013 ElectricalCharacteristics Unlessotherwisespecified,alllimitsensuredforTA = TJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 5V, V− = 0V,VCM = 1.5V,VO = V+/2,and R L > 1M unlessotherwisespecified. LMC6041AI LMC6041I UnitsParameter TestConditions Typical(1) Limit(2) Limit(2) (Limit) VOS InputOffsetVoltage 1 3 6 mV 3.3 6.3 max TCV OS InputOffsetVoltage 1.3 μV/°CAverageDrift IB InputBiasCurrent 0.002 pA4 4 max IOS InputOffsetCurrent 0.001 pA2 2 max R IN InputResistance >10 TeraΩ CMRR Common Mode Rejection 0V ≤ VCM ≤ 12.0V 75 68 62 dB Ratio V+ = 15V 66 60 min +PSRR PositivePower Supply 5V ≤ V+ ≤ 15V 75 68 62 dB RejectionRatio VO = 2.5V 66 60 min −PSRR NegativePower Supply 0V ≤ V− ≤ −10V 94 84 74 dB RejectionRatio VO = 2.5V 83 73 min CMR InputCommon-Mode V+ = 5V and 15V −0.4 −0.1 −0.1 V VoltageRange forCMRR ≥ 50 dB 0 0 max V+− 2.5V V+− 2.4V min AV LargeSignalVoltageGain R L = 100 kΩ(3) Sourcing 1000 400 300 V/mV 300 200 min Sinking 500 180 90 V/mV 120 70 min R L = 25 kΩ(3) Sourcing 1000 200 100 V/mV 160 80 min Sinking 250 100 50 V/mV 60 40 min VO OutputSwing V+ = 5V 4.987 4.970 4.940 V R L = 100 kΩ toV+/2 4.950 4.910 min 0.004 0.030 0.060 V 0.050 0.090 max V+ = 5V 4.980 4.920 4.870 V R L = 25 kΩ toV+/2 4.870 4.820 min 0.010 0.080 0.130 V 0.130 0.180 max V+ = 15V 14.970 14.920 14.880 V R L = 100 kΩ toV+/2 14.880 14.820 min 0.007 0.030 0.060 V 0.050 0.090 max V+ = 15V 14.950 14.900 14.850 V R L = 25 kΩ toV+/2 14.850 14.800 min 0.022 0.100 0.150 V 0.150 0.200 max (1) TypicalValuesrepresentthemost likelyparametricnorm. (2) Alllimitsareensuredatroom temperature(standardtypeface)oratoperatingtemperatureextremes(boldfacetype). Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMC6041
SNOS610E –DECEMBER 1994–REVISED MARCH 2013 www.ti.com ElectricalCharacteristics(continued) Unlessotherwisespecified,alllimitsensuredforTA = TJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 5V, V− = 0V,VCM = 1.5V,VO = V+/2,and R L > 1M unlessotherwisespecified. LMC6041AI LMC6041I UnitsParameter TestConditions Typical(1) Limit(2) Limit(2) (Limit) ISC OutputCurrent Sourcing,VO = 0V 22 16 13 mA V+ = 5V 10 8 min Sinking,VO = 5V 21 16 13 mA 8 8 min ISC OutputCurrent Sourcing,VO = 0V 40 15 15 mA V+ = 15V 10 10 min Sinking,VO = 13V (4) 39 24 21 mA 8 8 min IS SupplyCurrent VO = 1.5V 14 20 26 μA 24 30 max V+ = 15V 18 26 34 μA 31 39 max (4) Do notconnectoutputtoV+ when V+ isgreaterthan13V orreliabilitymay be adverselyaffected. AC ElectricalCharacteristics Unlessotherwisespecified,alllimitsensuredforTA = TJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 5V, V− = 0V,VCM = 1.5V,VO = V+/2,and R L > 1M unlessotherwisespecified. LMC6041AI LMC6041I UnitsParameter TestConditions Typ (1) (Limit)Limit(2) Limit(2) SR Slew Rate See (3) 0.02 0.015 0.010 V/μs 0.010 0.007 min GBW Gain-BandwidthProduct 75 kHz φm Phase Margin 60 Deg en Input-ReferredVoltageNoise F = 1 kHz 83 nV/√Hz in Input-ReferredCurrentNoise F = 1 kHz 0.0002 pA/√Hz THD TotalHarmonicDistortion F = 1 kHz,AV = −5 0.01 % R L = 100 kΩ,VO = 2 Vpp ±5V Supply (1) TypicalValuesrepresentthemost likelyparametricnorm. (2) Alllimitsareensuredatroom temperature(standardtypeface)oratoperatingtemperatureextremes(boldfacetype). (3) V+ = 15V.Connectedas VoltageFollowerwith10V stepinput.Number specifiedintheslowerofthepositiveand negativeslewrates.
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www.ti.com SNOS610E –DECEMBER 1994–REVISED MARCH 2013 TypicalPerformance Characteristics VS = ± 7.5V,TA = 25°C unlessotherwisespecified Supply Current OffsetVoltage vs vs Supply Voltage Temperature ofFiveRepresentativeUnits Figure3. Figure4. InputBias Current InputBias Current vs vs Temperature InputCommon-Mode Voltage Figure5. Figure6. InputCommon-Mode VoltageRange vs Output Characteristics Temperature CurrentSinking Figure7. Figure8. Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMC6041
SNOS610E –DECEMBER 1994–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) VS = ± 7.5V,TA = 25°C unlessotherwisespecified InputVoltageNoise Output Characteristics vs CurrentSourcing Frequency Figure9. Figure10. Power Supply RejectionRatio CMRR vs vs Frequency Frequency Figure11. Figure12. CMRR Open-Loop VoltageGain vs vs Temperature Temperature Figure13. Figure14.
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www.ti.com SNOS610E –DECEMBER 1994–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) VS = ± 7.5V,TA = 25°C unlessotherwisespecified Gain and Phase Responses Open-Loop vs Frequency Response Load Capacitance Figure15. Figure16. Gain and Phase Responses Gain Error(VOS vs vs Temperature VOUT ) Figure17. Figure18. Common-Mode Error Non-InvertingSlew Rate vs vs Common-Mode VoltageofThree RepresentativeUnits Temperature Figure19. Figure20. Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMC6041
SNOS610E –DECEMBER 1994–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) VS = ± 7.5V,TA = 25°C unlessotherwisespecified InvertingSlew Rate Non-InvertingLarge vs SignalPulse Response Temperature (AV = +1) Figure21. Figure22. Non-InvertingSmall InvertingLarge-Signal SignalPulse Response Pulse Response Figure23. Figure24. Stability InvertingSmall Signal vs Pulse Response CapacitiveLoad (AV = +1) Figure25. Figure26.
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www.ti.com SNOS610E –DECEMBER 1994–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) VS = ± 7.5V,TA = 25°C unlessotherwisespecified Stability vs CapacitiveLoad (AV = ±10) Figure27. Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMC6041
SNOS610E –DECEMBER 1994–REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6041 incorporatesa novelop-amp designtopologythatenablesittomaintainrail-to-railoutputswing even when drivinga largeload.Insteadofrelyingon a push-pullunitygainoutputbufferstage,theoutputstage istakendirectlyfrom theinternalintegrator,which providesbothlow outputimpedance and largegain.Special feed-forwardcompensationdesign techniquesare incorporatedto maintainstabilityover a wider range of operatingconditionsthan traditionalmicropowerop-amps. These featuresmake the LMC6041 both easierto designwith,and providehigherspeed thanproductstypicallyfoundinthisultra-lowpower class. COMPENSATING FOR INPUT CAPACITANCE Itisquitecommon touse largevaluesoffeedbackresistancewithamplifierswithultra-lowinputcurrent,likethe LMC6041. AlthoughtheLMC6041 ishighlystableovera wide range ofoperatingconditions,certainprecautionsmust be met toachievethedesiredpulseresponsewhen a largefeedbackresistorisused.Largefeedbackresistorsand even smallvaluesofinputcapacitance,due totransducers,photodiodes,and circuitsboard parasitics,reduce phase margins. When highinputimpedance aredemanded, guardingoftheLMC6041 issuggested.Guardinginputlineswillnot onlyreduce leakage,but lowersstrayinputcapacitanceas well.(See Printed-Circuit-BoardLayout forHigh Impedance Work.) Figure28. CancellingtheEffectofInputCapacitance The effectofinputcapacitancecan be compensated forby addinga capacitor.Adding a capacitor,C f,around thefeedbackresistor(asinFigure28 )such that: (1) or R 1 C IN ≤ R 2 C f (2) Sinceitisoftendifficulttoknow theexactvalueofC IN,C f can be experimentallyadjustedso thatthedesired pulse response is achieved.Refer to the LMC660 and the LMC662 fora more detaileddiscussionon compensatingforinputcapacitance. CAPACITIVE LOAD TOLERANCE Directcapacitiveloadingwillreducethephase marginofmany op-amps.A poleinthefeedbackloopiscreated by thecombinationoftheop-amp'soutputimpedance and thecapacitiveload.Thispoleinducesphase lagatthe unity-gaincrossoverfrequencyoftheamplifierresultingineitheran oscillatoryorunderdamped pulseresponse. Witha few externalcomponents,op amps can easilyindirectlydrivecapacitiveloads,as shown inFigure29.
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www.ti.com SNOS610E –DECEMBER 1994–REVISED MARCH 2013 Figure29. LMC6041 NoninvertingGain of10 Amplifier,Compensated toHandle CapacitiveLoads InthecircuitofFigure29,R1 and C1 servetocounteractthelossofphase marginby feedingthehighfrequency component of the outputsignalback to the amplifier'sinvertinginput,therebypreservingphase margin inthe overallfeedbackloop. Capacitiveloaddrivingcapabilityisenhanced by usinga pullup resistortoV+ (Figure30 ).Typicallya pullup resistorconducting10 μA or more willsignificantlyimprovecapacitiveloadresponses.The valueofthepullup resistormust be determinedbased on thecurrentsinkingcapabilityoftheamplifierwithrespecttothedesired outputswing.Open loop gain of the amplifiercan also be affectedby the pullup resistor(see Electrical Characteristics). Figure30. Compensating forLarge CapacitiveLoads witha PullUp Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK Itisgenerallyrecognizedthatany circuitwhichmust operatewithlessthan1000 pA ofleakagecurrentrequires speciallayoutof the PC board.When one wishes to take advantage of the ultra-lowbias currentof the LMC6041, typicallylessthan 2fA,itisessentialto have an excellentlayout.Fortunately,the techniquesof obtaininglow leakagesare quitesimple.First,theusermust notignorethesurfaceleakageofthePC board, even though itmay sometimes appear acceptablylow,because under conditionsof highhumidityor dustor contamination,thesurfaceleakagewillbe appreciable. To minimizetheeffectofany surfaceleakage,layouta ringoffoilcompletelysurroundingtheLMC6041's inputs and the terminalsof capacitors,diodes,conductors,resistors,relayterminals,etc.connectedto the op-amp's inputs,as inFigure31.To have a significanteffect,guardringsshouldbe placedon boththetopand bottomof thePC board.ThisPC foilmust thenbe connectedtoa voltagewhich isatthesame voltageas theamplifer inputs,sinceno leakagecurrentcan flowbetween two pointsatthesame potential.For example,a PC board trace-to-padresistanceof 1012Ω, which isnormallyconsidereda verylargeresistance,couldleak5 pA ifthe tracewere a 5V bus adjacentto the pad of the input.This would cause a 100 timesdegradationfrom the LMC6041's actualperformance.However, ifa guard ringis held within5 mV of the inputs,then even a resistanceof1011Ω would cause only0.05pA ofleakagecurrent.See Figure34 fortypicalconnectionsofguard ringsforstandardop-amp configurations. Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMC6041
SNOS610E –DECEMBER 1994–REVISED MARCH 2013 www.ti.com Figure31. Example ofGuard Ring inP.C.Board Layout Figure32. InvertingAmplifier Figure33. Follower Non-InvertingAmplifier Figure34. TypicalConnections ofGuard Rings The designershouldbe aware thatwhen itisinappropriateto layout a PC board forthe sake of justa few circuits,thereisanothertechniquewhich iseven betterthan a guard ringon a PC board:Don'tinsertthe amplifier'sinputpinintothe board at all,but bend itup inthe airand use onlyairas an insulator.Airisan excellentinsulator.Inthiscase you may have toforegosome oftheadvantagesofPC board construction,but theadvantagesaresometimeswellworththeeffortofusingpoint-to-pointup-in-the-airwiring.See Figure35.
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www.ti.com SNOS610E –DECEMBER 1994–REVISED MARCH 2013 (InputpinsareliftedoutofPC boardand soldereddirectlytocomponents.AllotherpinsconnectedtoPC board.) Figure35. AirWiring TypicalSingle-SupplyApplications (V+ = 5.0VDC ) The extremelyhighinputimpedance,and low power consumption,oftheLMC6041 make itidealforapplications thatrequirebattery-poweredinstrumentationamplifiers.Examples ofthesetypeofapplicationsarehand-heldpH probes,analyticmedical instruments,magnetic fielddetectors,gas detectors,and siliconbased pressure transducers. Figure36. Two Op-Amp InstrumentationAmplifier The circuitinFigure36 isrecommended forapplicationswhere thecommon-mode inputrange isrelativelylow and thedifferentialgainwillbe intherangeof10 to1000.Thistwo op-amp instrumentationamplifierfeaturesan independentadjustmentofthegainand common-mode rejectiontrim,and a totalquiescentsupplycurrentofless than28 μA. To maintainultra-highinputimpedance,itisadvisabletouse ground ringsand considerPC board layoutan importantpartof the overallsystem design(see Printed-Circuit-BoardLayout forHigh Impedance Work).Referringto Figure36, the inputvoltagesare representedas a common-mode inputVCM plus a differentialinputVD . Rejectionofthecommon-mode component oftheinputisaccomplishedby making theratioofR1/R2 equalto R3/R4.So thatwhere, (3) A suggesteddesignguidelineistominimizethedifferenceofvaluebetween R1 throughR4. Thiswilloftenresult inimprovedresistortempco,amplifiergain,and CMRR overtemperature.IfRN = R1 = R2 = R3 = R4 thenthe gainequationcan be simplified: (4) Due tothe“zero-in,zero-out”performanceoftheLMC6041, and outputswingrail-rail,thedynamic rangeisonly limitedtotheinputcommon-mode rangeof0V toVS–2.3V,worstcase atroom temperature.Thisfeatureofthe LMC6041 makes itan idealchoiceforlow-powerinstrumentationsystems. Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMC6041
SNOS610E –DECEMBER 1994–REVISED MARCH 2013 www.ti.com A completeinstrumentationamplifierdesignedfora gainof 100 isshown inFigure37. Provisionshave been made forlowsensitivitytrimmingofCMRR and gain. Figure37. Low-Power Two-Op-Amp InstrumentationAmplifier Figure38. Low-Leakage Sample and Hold Figure39. InstrumentationAmplifier Figure40. 1 Hz Square-Wave Oscillator
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www.ti.com SNOS610E –DECEMBER 1994–REVISED MARCH 2013 Figure41. AC Coupled Power Amplifier Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMC6041
SNOS610E –DECEMBER 1994–REVISED MARCH 2013 www.ti.com
REVISION HISTORY
Changes from RevisionD (March 2013)toRevisionE Page
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www.ti.com 1-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMC6041AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 41AIM LMC6041AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 41AIM LMC6041AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 41AIM LMC6041IM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 41IM LMC6041IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 41IM LMC6041IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC60 41IM LMC6041IN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) SN | CU SN Level-1-NA-UNLIM -40 to 85 LMC60 41IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
www.ti.com 1-Nov-2013 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6041AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6041IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 2
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