LMC6034 TI1 | Alldatasheet
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www.ti.com SNOS608C –MAY 1998–REVISED MARCH 2013 LMC6034CMOS QuadOperationalAmplifier Check forSamples: LMC6034 1FEATURES DESCRIPTION The LMC6034 isa CMOS quad operationalamplifier 2• Specifiedfor2 kΩ and 600Ω Loads whichcan operatefromeithera singlesupplyordual• High VoltageGain:126 dB supplies.Itsperformancefeaturesincludean input
- Low OffsetVoltageDrift:2.3μV/°C common-mode range thatreachesground,low input biascurrent,and highvoltagegainintorealisticloads,• UltraLow InputBias Current:40 fA such as 2 kΩ and 600Ω.• InputCommon-Mode Range IncludesV− This chip is builtwithNational'sadvanced Double-• OperatingRange from +5V to+15V Supply PolySilicon-GateCMOS process.• ISS = 400 μA/Amplifier;IndependentofV+ See the LMC6032 datasheet for a CMOS dual• Low Distortion:0.01% at10 kHz operationalamplifierwiththese same features.For• Slew Rate:1.1V/μs higher performance characteristicsrefer to the
- Improved Performance Over TLC274 LMC660.
APPLICATIONS
- High-Impedance Bufferor Preamplifier
- Current-to-VoltageConverter
- Long-Term Integrator
- Sample-and-Hold Circuit
- MedicalInstrumentation Connection Diagram Figure1. 14-PinSOIC (Top View) Guard Ring Connections – Non-InvertingAmplifier Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1998–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNOS608C –MAY 1998–REVISED MARCH 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) DifferentialInputVoltage ±SupplyVoltage SupplyVoltage(V+ − V−) 16V OutputShortCircuittoV+ See (3) OutputShortCircuittoV− See (4) Lead Temperature(Soldering,10 sec.) 260°C StorageTemperatureRange −65°C to+150°C Power Dissipation See (5) VoltageatOutput/InputPin (V+)+0.3V,(V−)−0.3V CurrentatOutputPin ±18 mA CurrentatInputPin ±5 mA CurrentatPower SupplyPin 35 mA JunctionTemperature(5) 150°C ESD Tolerance(6) 1000V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothecomponent may occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand test conditions,see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) Do notconnectoutputtoV+,when V+ isgreaterthan13V orreliabilitymay be adverselyaffected. (4) Appliestobothsingle-supplyand split-supplyoperation.Continuousshortcircuitoperationatelevatedambienttemperatureand/or multipleOp Amp shortscan resultinexceedingthemaximum allowedjunctiontemperatureof150°C. Outputcurrentsinexcessof±30 mA overlongtermmay adverselyaffectreliability. (5) The maximum power dissipationisa functionofTJ(max),θJA,TA.The maximum allowablepower dissipationatany ambienttemperature isPD = (TJ(max)–TA)/θJA. (6) Human body model,100 pF dischargedthrougha 1.5kΩ resistor. OPERATING RATINGS (1) TemperatureRange −40°C ≤ TJ ≤ +85°C SupplyVoltageRange 4.75Vto15.5V Power Dissipation See (2) ThermalResistance(θJA)(3) 14-PinSOIC 115°C/W (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothecomponent may occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand test conditions,see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted. (2) Foroperatingatelevatedtemperaturesthedevicemust be deratedbased on thethermalresistanceθJA withPD = (TJ − TA)/θJA. (3) Allnumbers applyforpackagessoldereddirectlyintoa PC board. DC ELECTRICAL CHARACTERISTICS Unlessotherwisespecified,alllimitsguaranteedforTJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 5V, V− = GND = 0V,VCM = 1.5V,VOUT = 2.5V,and R L > 1M unlessotherwisespecified. Symbol Parameter Conditions Typical(1) LMC6034I Units Limit(2) VOS InputOffsetVoltage 1 9 mV 11 max ΔVOS /ΔT InputOffsetVoltage 2.3 μV/°C AverageDrift IB InputBiasCurrent 0.04 pA 200 max (1) Typicalvaluesrepresentthemost likelyparametricnorm. (2) Alllimitsareguaranteedatroom temperature(standardtypeface)oratoperatingtemperatureextremes(bold typeface).
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www.ti.com SNOS608C –MAY 1998–REVISED MARCH 2013 DC ELECTRICAL CHARACTERISTICS (continued) Unlessotherwisespecified,alllimitsguaranteedforTJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 5V, V− = GND = 0V,VCM = 1.5V,VOUT = 2.5V,and R L > 1M unlessotherwisespecified. Symbol Parameter Conditions Typical(1) LMC6034I Units Limit(2) IOS InputOffsetCurrent 0.01 pA 100 max R IN InputResistance >1 TeraΩ CMRR Common Mode 0V ≤ VCM ≤ 12V 83 63 dB RejectionRatio V+ = 15V 60 min +PSRR PositivePower Supply 5V ≤ V+ ≤ 15V 83 63 dB RejectionRatio VO = 2.5V 60 min −PSRR NegativePower Supply 0V ≤ V− ≤ −10V 94 74 dB RejectionRatio 70 min VCM InputCommon-Mode V+ = 5V & 15V −0.4 −0.1 V VoltageRange ForCMRR ≥ 50 dB 0 max V+ − 2.6 min AV LargeSignalVoltageGain R L = 2 kΩ(3) 2000 200 V/mV Sourcing 100 min Sinking 500 90 V/mV 40 min R L = 600Ω(3) 1000 100 V/mV Sourcing 75 min Sinking 250 50 V/mV 20 min VO OutputVoltageSwing V+ = 5V 4.87 4.20 V R L = 2 kΩ to2.5V 4.00 min 0.10 0.25 V 0.35 max V+ = 5V 4.61 4.00 V R L = 600Ω to2.5V 3.80 min 0.30 0.63 V 0.75 max V+ = 15V 14.63 13.50 V R L = 2 kΩ to7.5V 13.00 min 0.26 0.45 V 0.55 max V+ = 15V 13.90 12.50 V R L = 600Ω to7.5V 12.00 min 0.79 1.45 V 1.75 max Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMC6034
SNOS608C –MAY 1998–REVISED MARCH 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) Unlessotherwisespecified,alllimitsguaranteedforTJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 5V, V− = GND = 0V,VCM = 1.5V,VOUT = 2.5V,and R L > 1M unlessotherwisespecified. Symbol Parameter Conditions Typical(1) LMC6034I Units Limit(2) IO OutputCurrent V+ = 5V 22 13 mA Sourcing,VO = 0V 9 min Sinking,VO = 5V 21 13 mA 9 min V+ = 15V 40 23 mA Sourcing,VO = 0V 15 min Sinking,VO = 13V (4) 39 23 mA 15 min IS SupplyCurrent AllFourAmplifiers 1.5 2.7 mA VO = 1.5V 3.0 max (4) Do notconnectoutputtoV+,when V+ isgreaterthan13V orreliabilitymay be adverselyaffected. AC ELECTRICAL CHARACTERISTICS Unlessotherwisespecified,alllimitsguaranteedforTJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 5V, V− = GND = 0V,VCM = 1.5V,VOUT = 2.5V,and R L > 1M unlessotherwisespecified. Symbol Parameter Conditions Typical(1) LMC6034I Units Limit(2) SR Slew Rate See (3) 1.1 0.8 V/μs 0.4 min GBW Gain-BandwidthProduct 1.4 MHz φM Phase Margin 50 Deg G M Gain Margin 17 dB Amp-to-Amp Isolation See (4) 130 dB en Input-ReferredVoltageNoise F = 1 kHz 22 nV/√Hz in Input-ReferredCurrentNoise F = 1 kHz 0.0002 pA/√Hz THD TotalHarmonicDistortion F = 10 kHz,AV = −10 R L = 2 kΩ,VO = 8 VPP 0.01 % ±5V Supply (1) Typicalvaluesrepresentthemost likelyparametricnorm. (2) Alllimitsareguaranteedatroom temperature(standardtypeface)oratoperatingtemperatureextremes(bold typeface). (3) V+ = 15V.Connectedas VoltageFollowerwith10V stepinput.Number specifiedistheslowerofthepositiveand negativeslewrates. (4) Inputreferred.V+ = 15V and R L = 10 kΩ connectedtoV+/2.Each amp excitedinturnwith1 kHz toproduceVO = 13 VPP .
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www.ti.com SNOS608C –MAY 1998–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±7.5V,TA = 25°C unlessotherwisespecified Note:Avoidresistiveloadsoflessthan500Ω,as theymay cause instability Supply Current vs Supply Voltage InputBias Current Figure2. Figure3. Output Characteristics Output Characteristics CurrentSinking CurrentSourcing Figure4. Figure5. CMRR InputVoltageNoise vs vs Frequency Frequency Figure6. Figure7. Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMC6034
SNOS608C –MAY 1998–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) VS = ±7.5V,TA = 25°C unlessotherwisespecified Note:Avoidresistiveloadsoflessthan500Ω,as theymay cause instability Open-Loop Frequency Frequency Response Response vs CapacitiveLoad Figure8. Figure9. Non-InvertingLarge Signal Stabilityvs Pulse Response CapacitiveLoad Figure10. Figure11. Stabilityvs CapacitiveLoad Figure12.
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www.ti.com SNOS608C –MAY 1998–REVISED MARCH 2013 APPLICATIONS HINT AmplifierTopology The topologychosen fortheLMC6034, shown inFigure13,isunconventional(comparedtogeneral-purposeop amps) inthatthetraditionalunity-gainbufferoutputstageisnotused;instead,theoutputistakendirectlyfrom theoutputoftheintegrator,toallowa largeroutputswing.Sincethebuffertraditionallydeliversthepower tothe load,whilemaintaininghighop amp gainand stability,and must withstandshortstoeitherrail,thesetasksnow falltotheintegrator. As a resultofthesedemands, theintegratorisa compound affairwithan embedded gainstagethatisdoublyfed forward(viaC f and Cff)by a dedicatedunity-gaincompensationdriver.In addition,the outputportionof the integratorisa push-pullconfigurationfordeliveringheavy loads.Whilesinkingcurrentthewhole amplifierpath consistsof threegainstageswithone stagefed forward,whereas whilesourcingthe path containsfourgain stageswithtwo fedforward. Figure13. LMC6034 CircuitTopology (Each Amplifier) The largesignalvoltagegainwhilesourcingiscomparabletotraditionalbipolarop amps, even witha 600Ω load. The gainwhilesinkingishigherthanmost CMOS op amps, due totheadditionalgainstage;however,under heavy load(600Ω)thegainwillbe reducedas indicatedintheElectricalCharacteristics. Compensating InputCapacitance The highinputresistanceoftheLMC6034 op amps allowstheuse oflargefeedbackand sourceresistorvalues withoutlosinggainaccuracydue toloading.However, thecircuitwillbe especiallysensitivetoitslayoutwhen theselarge-valueresistorsareused. Every amplifierhas some capacitancebetween each inputand AC ground, and also some differential capacitancebetween the inputs.When the feedback network around an amplifieris resistive,thisinput capacitance(alongwithany additionalcapacitancedue tocircuitboardtraces,thesocket,etc.)and thefeedback resistorscreatea poleinthefeedbackpath.InthefollowingGeneralOperationalAmplifiercircuit,thefrequency ofthispoleis (1) where C S is the totalcapacitanceat the invertinginput,includingamplifierinputcapcitanceand any stray capacitancefromtheIC socket(ifone isused),circuitboardtraces,etc.,and R P istheparallelcombinationofR F and R IN. This formula,as wellas allformulaederivedbelow,apply to invertingand non-invertingop-amp configurations. When thefeedbackresistorsare smallerthana few kΩ,thefrequencyofthefeedbackpolewillbe quitehigh, sinceC S isgenerallylessthan 10 pF. Ifthe frequencyof the feedbackpoleismuch higherthan the “ideal” closed-loopbandwidth(thenominalclosed-loopbandwidthintheabsence ofC S),thepolewillhave a negligible effecton stability,as itwilladd onlya smallamount ofphase shift. However,ifthefeedbackpoleislessthanapproximately6 to10 timesthe“ideal” −3 dB frequency,a feedback capacitor,C F,shouldbe connectedbetween theoutputand theinvertinginputoftheop amp. Thisconditioncan alsobe statedintermsoftheamplifier'slow-frequencynoisegain:To maintainstabilitya feedbackcapacitorwill probablybe needed if Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMC6034
SNOS608C –MAY 1998–REVISED MARCH 2013 www.ti.com (2) where (3) istheamplifier'slow-frequencynoisegainand GBW istheamplifier'sgainbandwidthproduct.An amplifier'slow- frequencynoisegainisrepresentedby theformula (4) regardlessof whether the amplifierisbeing used in invertingor non-invertingmode. Note thata feedback capacitorismore likelytobe needed when thenoisegainislowand/orthefeedbackresistorislarge. Ifthe above conditionismet (indicatinga feedbackcapacitorwillprobablybe needed),and the noisegainis largeenough that: (5) thefollowingvalueoffeedbackcapacitorisrecommended: (6) If (7) thefeedbackcapacitorshouldbe: (8) Note thatthese capacitorvalues are usuallysignificantlysmallerthan those given by the older,more conservativeformula: (9) C S consistsoftheamplifier's inputcapacitanceplusany straycapacitancefromthecircuitboardand socket.C F compensatesforthepolecaused by C S and thefeedbackresistors. Figure14. GeneralOperationalAmplifierCircuit
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www.ti.com SNOS608C –MAY 1998–REVISED MARCH 2013 Usingthesmallercapacitorswillgivemuch higherbandwidthwithlittledegradationoftransientresponse.Itmay be necessaryinany oftheabove cases touse a somewhat largerfeedbackcapacitortoallowforunexpected straycapacitance,ortotolerateadditionalphase shiftsintheloop,orexcessivecapacitiveload,ortodecrease the noise or bandwidth,or simply because the particularcircuitimplementationneeds more feedback capacitancetobe sufficientlystable.For example,a printedcircuitboard'sstraycapacitancemay be largeror smallerthanthebreadboard's,so theactualoptimum valueforC F may be differentfromtheone estimatedusing the breadboard.In most cases,the valuesof C F shouldbe checked on the actualcircuit,startingwiththe computed value. CapacitiveLoad Tolerance Likemany otherop amps, theLMC6034 may oscillatewhen itsappliedloadappearscapacitive.The thresholdof oscillationvariesboth withloadand circuitgain.The configurationmost sensitiveto oscillationisa unity-gain follower.See TypicalPerformanceCharacteristics. The load capacitanceinteractswiththe op amp's outputresistanceto createan additionalpole.Ifthispole frequencyissufficientlylow,itwilldegradetheop amp's phase marginso thattheamplifierisno longerstableat low gains.As shown inFigure15, the additionof a smallresistor(50Ω to 100Ω) inserieswiththe op amp's output,and a capacitor(5 pF to10 pF) from invertinginputtooutputpins,returnsthephase margintoa safe value withoutinterferingwith lower-frequencycircuitoperation.Thus largervalues of capacitancecan be toleratedwithoutoscillation.Note thatinallcases,theoutputwillringheavilywhen theloadcapacitanceisnear thethresholdforoscillation. Figure15. Rx, Cx Improve CapacitiveLoad Tolerance Capacitiveloaddrivingcapabilityisenhanced by usinga pullup resistortoV+ (Figure16).Typicallya pullup resistorconducting500 μA ormore willsignificantlyimprovecapacitiveloadresponses.The valueofthepullup resistormust be determinedbased on thecurrentsinkingcapabilityoftheamplifierwithrespecttothedesired outputswing.Open loop gain of the amplifiercan also be affectedby the pullup resistor(see Electrical Characteristics). Figure16. Compensating forLarge CapacitiveLoads witha PullUp Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK Itisgenerallyrecognizedthatany circuitwhichmust operatewithlessthan1000 pA ofleakagecurrentrequires speciallayoutof the PC board.When one wishes to take advantage of the ultra-lowbias currentof the LMC6034, typicallylessthan0.04pA, itisessentialtohave an excellentlayout.Fortunately,thetechniquesfor obtaininglow leakagesare quitesimple.First,theusermust notignorethesurfaceleakageofthePC board, even though itmay sometimes appear acceptablylow,because under conditionsof highhumidityor dustor contamination,thesurfaceleakagewillbe appreciable. Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMC6034
SNOS608C –MAY 1998–REVISED MARCH 2013 www.ti.com To minimizetheeffectofany surfaceleakage,layouta ringoffoilcompletelysurroundingtheLMC6034's inputs and the terminalsof capacitors,diodes,conductors,resistors,relayterminals,etc.connectedto the op-amp's inputs.See Figure17 .To have a significanteffect,guardringsshouldbe placedon boththetopand bottomof thePC board.ThisPC foilmust thenbe connectedtoa voltagewhich isatthesame voltageas theamplifier inputs,sinceno leakagecurrentcan flowbetween two pointsatthesame potential.For example,a PC board trace-to-padresistanceof 1012Ω, which isnormallyconsidereda verylargeresistance,couldleak5 pA ifthe tracewere a 5V bus adjacentto the pad of an input.This would cause a 100 timesdegradationfrom the LMC6034's actualperformance.However, ifa guard ringis held within5 mV of the inputs,then even a resistanceof1011Ω would cause only0.05pA ofleakagecurrent,or perhapsa minor(2:1)degradationofthe amplifier'sperformance.See Figure18, Figure19 and , Figure20 fortypicalconnectionsof guard ringsfor standardop-amp configurations.Ifbothinputsareactiveand athighimpedance,theguardcan be tiedtoground and stillprovidesome protection;see Figure21. Figure17. Example ofGuard Ring inP.C.Board Layout Figure18. Guard Ring Connections InvertingAmplifier Figure19. Guard Ring Connections Non-InvertingAmplifier Figure20. Guard Ring Connections Follower
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www.ti.com SNOS608C –MAY 1998–REVISED MARCH 2013 Figure21. Guard Ring Connections Howland CurrentPump The designershouldbe aware thatwhen itisinappropriateto layout a PC board forthe sake of justa few circuits,thereisanothertechniquewhich iseven betterthan a guard ringon a PC board:Don'tinsertthe amplifier'sinputpinintothe board at all,but bend itup inthe airand use onlyairas an insulator.Airisan excellentinsulator.Inthiscase you may have toforegosome oftheadvantagesofPC board construction,but theadvantagesaresometimeswellworththeeffortofusingpoint-to-pointup-in-the-airwiring.See Figure22. (InputpinsareliftedoutofPC boardand soldereddirectlytocomponents.AllotherpinsconnectedtoPC board.) Figure22. AirWiring BIAS CURRENT TESTING The testmethod of Figure23 is appropriateforbench-testingbias currentwith reasonableaccuracy.To understanditsoperation,firstcloseswitchS2 momentarily.When S2 isopened,then (10) Figure23. Simple InputBias CurrentTestCircuit A suitablecapacitorforC2 would be a 5 pF or 10 pF silvermica, NPO ceramic,or air-dielectric.When determiningthemagnitudeofIb−,theleakageofthecapacitorand socketmust be takenintoaccount.SwitchS2 shouldbe leftshortedmost ofthetime,orelsethedielectricabsorptionofthecapacitorC2 couldcause errors. Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMC6034
SNOS608C –MAY 1998–REVISED MARCH 2013 www.ti.com Similarly,ifS1 isshortedmomentarily(whileleavingS2 shorted) (11) where C x isthestraycapacitanceatthe+ input. TypicalSingle-SupplyApplications (V+ = 5.0VDC) Additionalsingle-supplyapplicationsideascan be found inthe LM324 datasheet.The LMC6034 ispin-for-pin compatiblewiththeLM324 and offersgreaterbandwidthand inputresistanceovertheLM324. These features willimprovetheperformanceofmany existingsingle-supplyapplications.Note,however,thatthesupplyvoltage rangeoftheLMC6034 issmallerthanthatoftheLM324. Figure24. Low-Leakage Sample-and-Hold Figure25. InstrumentationAmplifier (12) (13) For good CMRR overtemperature,low driftresistorsshouldbe used.MatchingofR3 toR6 and R4 toR7 affect CMRR. Gain may be adjustedthroughR2. CMRR may be adjustedthroughR7.
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www.ti.com SNOS608C –MAY 1998–REVISED MARCH 2013 (V+ = 5.0VDC) Figure26. Sine-Wave Oscillator Oscillatorfrequencyisdeterminedby R1, R2, C1, and C2: fosc= 1/2πRC, where R = R1 = R2 and C = C1 = C2. Thiscircuit,as shown,oscillatesat2.0kHz witha peak-to-peakoutputswingof4.0V. Figure27. 1 Hz Square-Wave Oscillator Figure28. Power Amplifier Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMC6034
SNOS608C –MAY 1998–REVISED MARCH 2013 www.ti.com (V+ = 5.0VDC) fO = 10 Hz Q = 2.1 Gain = −8.8 Figure29. 10 Hz Bandpass Filter fc = 10 Hz d = 0.895 Gain = 1 2 dB passband ripple Figure30. 10 Hz High-Pass Filter fc = 1 Hz d = 1.414 Gain = 1.57 Figure31. 1 Hz Low-Pass Filter(MaximallyFlat,Dual Supply Only)
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www.ti.com SNOS608C –MAY 1998–REVISED MARCH 2013 (V+ = 5.0VDC) Gain = −46.8 Outputoffsetvoltagereducedtotheleveloftheinputoffsetvoltageofthebottomamplifier(typically1 mV). Figure32. High Gain AmplifierwithOffsetVoltageReduction Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMC6034
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REVISION HISTORY
Changes from RevisionB (March 2013)toRevisionC Page
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www.ti.com 9-Aug-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMC6034IM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LMC6034IM LMC6034IM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6034IM LMC6034IMX NRND SOIC D 14 TBD Call TI Call TI -40 to 85 LMC6034IM LMC6034IMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6034IM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
www.ti.com 9-Aug-2016 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6034IMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 Pack Materials-Page 2
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