LMC6032

LMC603x CMOS Dual Operational Amplifiers datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNOS609,D]
• PDF pages: 34

Technical content

LMC603x CMOS Dual Operational Amplifiers

1 Features

• Specified for 2kΩ and 600Ω loads
• High voltage gain: 126dB, 2kΩ
• Low offset voltage drift: 2.3μV/°C
• Ultra-low input bias current: 40fA
• Input common-mode range includes V−
• Operates on standard 5V and 15V supplies
• IQ = 375μA/amplifier; independent of V+
• Low noise: 22nV/√Hz
• Slew rate: 1.1V/μs
• Improved performance over TLC272

2 Applications

• High-impedance buffer or preamplifier
• Current-to-voltage converter
• Long-term integrator
• Sample-and-hold circuit
• Medical instrumentation

3 Description

The dual LMC6032 and quad LMC6034 (LMC603x) are CMOS operational amplifiers that operate from either a single supply or dual supplies. Device performance features include an input common-mode range that reaches ground, low input bias current, and high voltage gain into realistic loads, such as 2k Ω and 600Ω. This chip is built with TI's advanced CMOS process. For higher-performance characteristics, see the OPA928. Device Information PART NUMBER CHANNEL PACKAGE(1) LMC6032 Dual D (SOIC, 8) P (PDIP, 8) LMC6034 Quad D (SOIC, 14) P (PDIP, 14) (1) For more information, see Section 9. RES11A00-Q1 10k 10k IN IN+ LMC603x RES11A90-Q1 REF OUTLMC603x LMC603x C3 C1 C4 Typical Application: Instrumentation Amplifier With RES11A Typical Application: 10Hz High-Pass Filter LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

9 Mechanical, Packaging, and Orderable Information..21

4 Pin Configuration and Functions

2±IN A 7 OUT B 3+IN A 6 ±IN B 4V± 5 +IN B Not to scale Table 4-1. Pin Functions: LMC6032 PIN TYPE DESCRIPTION NAME NO. +IN A 3 Input Noninverting input, channel A –IN A 2 Input Inverting input, channel A +IN B 5 Input Noninverting input, channel B –IN B 6 Input Inverting input, channel B OUT A 1 Output Output, channel A OUT B 7 Output Output, channel B V+ 8 Power Positive (highest) power supply V– 4 Power Negative (lowest) power supply LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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2±IN A 7 OUT B 3+IN A 6 ±IN B 4V± 5 +IN B Not to scale Table 4-2. Pin Functions: LMC6034 PIN TYPE DESCRIPTION NAME NO. +IN A 3 Input Noninverting input, channel A +IN B 5 Input Noninverting input, channel B +IN C 10 Input Noninverting input, channel C +IN D 12 Input Noninverting input, channel D –IN A 2 Input Inverting input, channel A –IN B 6 Input Inverting input, channel B –IN C 9 Input Inverting input, channel C –IN D 13 Input Inverting input, channel D OUT A 1 Output Output, channel A OUT B 7 Output Output, channel B OUT C 8 Output Output, channel C OUT D 14 Output Output, channel D V+ 4 Power Positive (highest) power supply V– 11 Power Negative (lowest) power supply www.ti.com LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMC6032 LMC6034

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT Differential input voltage ±Supply voltage V Supply voltage, VS = (V+) – (V–) Single supply 0 16 V Dual supply ±8 Output short circuit To V+ See(2) mA To V– See(3) Signal input pins Voltage (V–) – 0.3 (V+) + 0.3 V Current ±5 mA Output pin current ±18 mA Power supply pin Current 35 mA Power dissipation See(4) Temperature Operating, TA –40 150 Junction, TJ 150 Storage, Tstg –65 150 Lead (soldering, 10 sec.) 260 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. (3) Do not connect output to V+, when V+ is greater than 13V or reliability will be adversely affected. (4) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) – TA) / θJA

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT Supply voltage, VS = (V+) – (V–) Single supply 4.75 15.5 V Dual supply ±2.375 ±7.75 Specified temperature –40 85 °C Power dissipation See(2) (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. (2) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA) / θJA. All numbers apply for packages soldered directly into a printed circuit board. LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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5.4 Thermal Information LMC6032

THERMAL METRIC(1) LMC6032 UNITD (SOIC) P (PDIP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 165 101 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Thermal Information LMC6034

THERMAL METRIC(1) LMC6034 UNITD (SOIC) P(PDIP)

14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 115 85 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMC6032 LMC6034

5.6 Electrical Characteristics

at TA = +25°C, VS = 5V (V– = 0V), VCM = 1.5V, VOUT = VS / 2, and RL = 1MΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±1 ±9 mV TA = –40°C to +85°C ±11 dVOS/dT Input offset voltage drift TA = –40°C to +85°C ±2.3 µV/°C PSRR Power-supply rejection ratio Positive, 5V ≤ V+ ≤ 15V 63 83 dB TA = –40°C to +85°C 60 Negative, –5V ≤ V+ ≤ –10V 74 94 TA = –40°C to +85°C 70 INPUT BIAS CURRENT IB Input bias current ±40 fA TA = –40°C to +85°C ±200 pA IOS Input offset current ±10 fA TA = –40°C to +85°C ±100 pA NOISE en Input voltage noise density f = 1kHz 22 nV/√Hz in Input current noise density f = 1kHz 4 fA/√Hz THD Total harmonic distortion f= 10kHz, G = –10V/V, RL = 2kΩ, VO = 8Vpp, VS = ±5V 0.2 % INPUT VOLTAGE VCM Common-mode voltage range To positive rail, 5V ≤ VS ≤ 15V, CMRR > 50dB V To negative rail, 5V ≤ VS ≤ 15V, CMRR > 50dB TA = –40°C to +85°C (V–) CMRR Common-mode rejection ratio VS = 15V, 0V < VCM < 12V 63 83 dB TA = –40°C to +85°C 60 INPUT IMPEDANCE RIN Input resistance > 1 TΩ OPEN-LOOP GAIN AOL Open-loop voltage gain Sourcing, VS = 15V, VCM = 7.5V, 7.5V < VO < 11.5V, RL = 2kΩ 200 2000 V/mV TA = –40°C to +85°C 100 Sinking, VS = 15V, VCM = 7.5V, 2.5V < VO < 7.5V, RL = 2kΩ 90 500 TA = –40°C to +85°C 40 Sourcing, VS = 15V, VCM = 7.5V, 7.5V < VO < 11.5V, RL = 600Ω 100 1000 TA = –40°C to +85°C 75 Sinking, VS = 15V, VCM = 7.5V, 2.5V < VO < 7.5V, RL = 600Ω 50 250 TA = –40°C to +85°C 20 FREQUENCY RESPONSE GBW Gain bandwidth product 1.4 MHz SR Slew rate(1) VS = 15V, 10V step 0.8 1.1 V/µs TA = –40°C to +85°C 0.4 θm Phase margin 50 ° Crosstalk Dual and quad channel, VS = 15V, RL = 10kΩ to 7.5V, f = 1kHz, VO = 13Vpp 130 dB LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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5.6 Electrical Characteristics (continued)

at TA = +25°C, VS = 5V (V– = 0V), VCM = 1.5V, VOUT = VS / 2, and RL = 1MΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Voltage output swing Positive rail VS = 5V, RL = 2kΩ to mid-supply 4.20 4.87 V TA = –40°C to +85°C 4.00 Negative rail VS = 5V, RL = 2kΩ to mid-supply 0.10 0.25 TA = –40°C to +85°C 0.35 Positive rail VS = 5V, RL = 600Ω to mid-supply 4.00 4.61 TA = –40°C to +85°C 3.80 Negative rail VS = 5V, RL = 600Ω to mid-supply 0.30 0.63 TA = –40°C to +85°C 0.75 Positive rail VS = 15V, RL = 2kΩ to mid-supply 13.50 14.63 TA = –40°C to +85°C 13.00 Negative rail VS = 15V, RL = 2kΩ to mid-supply 0.26 0.45 TA = –40°C to +85°C 0.55 Positive rail VS = 15V, RL = 600Ω to mid-supply 12.50 13.90 TA = –40°C to +85°C 12.00 Negative rail VS = 15V, RL = 600Ω to mid-supply 0.79 1.45 TA = –40°C to +85°C 1.75 ISC Short-circuit current Sourcing VS = 5V, VO = 0V 13 22 mA TA = –40°C to +85°C 9 Sinking VS = 5V, VO = 5V 13 21 TA = –40°C to +85°C 9 Sourcing VS = 15V, VO = 0V 23 40 TA = –40°C to +85°C 15 Sinking VS = 15V, VO = 13V(2) 23 39 TA = –40°C to +85°C 15 POWER SUPPLY IQ Quiescent current per amplifier VO = 1.5V LMC6032 375 800 µA LMC6032, TA = –40°C to +85°C 950 LMC6034 375 675 LMC6034, TA = –40°C to +85°C 750 (1) Specification limit established from device population bench system measurements across multiple lots. Number specified is the slower of either the positive or negative slew rates. (2) Do not connect output to V+, when V+ is greater than 13V or reliability can be adversely affected. www.ti.com LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMC6032 LMC6034

at TA = 25°C, VS = ±7.5V, VOUT = mid-supply, and RL > 1MΩ (unless otherwise noted) Figure 5-1. Supply Current vs Supply Voltage Input Common Mode Voltage (V) Input Offset Voltage (mV) -8 -6 -4 -2 0 2 4 6 8 (V+) −1.9V Figure 5-2. Offset Voltage vs Input Common-Mode Voltage Figure 5-3. Input Bias Current Input Common Mode Voltage (V) Input Bias Current (pA) -8 -6 -4 -2 0 2 4 6 8 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 (V+) −1.9V Figure 5-4. Input Bias Current vs Input Common-Mode Voltage Input Common Mode Voltage (V) Input Bias Current (pA) -3 -2 -1 0 1 2 3 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 (V+) −1.9V VS = ±2.5V Figure 5-5. Input Bias Current vs Input Common-Mode Voltage Figure 5-6. Output Characteristics Current Sinking LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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Typical Characteristics (continued) at TA = 25°C, VS = ±7.5V, VOUT = mid-supply, and RL > 1MΩ (unless otherwise noted) Figure 5-13. Stability vs Capacitive Load Figure 5-14. Stability vs Capacitive Load Figure 5-15. Stability vs Capacitive Load Avoid resistive loads of less than 500Ω because these loads can cause instability. Figure 5-16. Stability vs Capacitive Load LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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6 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

6.1 Application Information

6.1.1 Amplifier Topology

The topology chosen for the LMC603x, shown in Figure 6-1, is unconventional compared to general-purpose op amps. The LMC603x incorporates novel op-amp design that enables a wide input common-mode range and rail to rail output swing even when driving a large load. The input common-mode range includes ground, making the LMC603x an excellent choice for single-supply applications. While the LMC603x supports both a wide supply and common-mode voltage range, large input common-mode voltage can cause a degradation of input bias current performance. 16V Differential Front End Ultra-Low Bias Rail-to-Rail IN+ IN OUT LMC603x Figure 6-1. LMC603x Circuit Topology (Each Amplifier) The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, even with a 600Ω load. The gain while sinking is greater than most CMOS op amps as a result of the additional gain stage; however, under heavy load (600Ω), the gain can be reduced as indicated in Section 5.6.

6.1.2 Compensating Input Capacitance

The high input resistance of the LMC603x op amps allows the use of large feedback and source resistor values without losing gain accuracy due to loading. However, the circuit can be especially sensitive to the printed circuit board (PCB) layout when these large-value resistors are used. Every amplifier has some capacitance between each input and ac ground, and also some differential capacitance between the inputs. When the feedback network around an amplifier is resistive, this input capacitance (along with any additional capacitance due to circuit board traces, the socket, and so on) and the feedback resistors create a pole in the feedback path. In Figure 6-2, the frequency of this pole is: f p = 1 2 π C S R P (1) where C S is the total capacitance at the inverting input, including amplifier input capacitance and any stray capacitance from the IC socket (if one is used), circuit board traces, and so on, and R P is the parallel combination of RF and RIN. This formula, as well as all the following formulas, apply to inverting and noninverting op-amp configurations. When the feedback resistors are smaller than a few k Ω, the frequency of the feedback pole can be quite high, since C S is generally less than 10pF. If the frequency of the feedback pole is much greater than the ideal closed-loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole has a negligible effect on stability, as only a small amount of phase shift is added. www.ti.com LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMC6032 LMC6034

However, if the feedback pole is less than approximately 6 to 10 times the ideal −3dB frequency, add a feedback capacitor, CF, between the output and the inverting input of the op amp. This condition can also be stated in terms of the amplifier low-frequency noise gain: To maintain stability, a feedback capacitor is probably needed if: R F R I N + 1 ≤ 6 × 2 π × G BW × R F × C S (2) where R F R I N + 1 is the amplifier low-frequency noise gain.

• GBW is the amplifier gain bandwidth product. An amplifier low-frequency noise gain is represented by the following formula: R F R I N + 1 (3) regardless of whether the amplifier is being used in an inverting or noninverting mode. A feedback capacitor is more likely to be needed when the noise gain is low, the feedback resistor is large. or both. If the previous condition is met (indicating a feedback capacitor is probably be needed), and the noise gain is large enough that R F R I N + 1 ≥ 2 G BW × R F × C S , the following value of feedback capacitor is recommended: C F = C S

2 R F

(4) If R F R I N + 1 < 2 G BW × R F × C S , the feedback capacitor is: C F = C S GB W × R F (5) These capacitor values are usually significantly smaller than those given by the older, more conservative formula: C F = C S R I N R F (6) CS consists of the amplifier input capacitance plus any stray capacitance from the circuit board and socket. CF compensates for the pole caused by CS and the feedback resistor. Figure 6-2. General Operational Amplifier Circuit Using the smaller capacitors give much higher bandwidth with little degradation of transient response. Using a somewhat larger feedback capacitor can be necessary in any of the above cases to allow for unexpected stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease the noise or bandwidth, or simply because the particular circuit implementation needs more feedback capacitance LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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to be sufficiently stable. For example, a PCB stray capacitance can be larger or smaller than the breadboard capacitance, so the actual preferred value for C F can be different from the one estimated using the breadboard. In most cases, check the value of CF on the actual circuit, starting with the computed value.

6.1.3 Capacitive Load Tolerance

Like many other op amps, the LMC603x can oscillate when applied a load that appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain follower. See also Section Typical Characteristics. The load capacitance interacts with the op amp output resistance to create an additional pole. If this pole frequency is sufficiently low, the op amp phase margin is degraded so that the amplifier is no longer stable at low gains. Figure 6-3 shows that the addition of a small resistor (50 Ω to 100Ω) in series with the op amp output, and a capacitor (5pF to 10pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. In all cases, the output can ring heavily when the load capacitance is near the threshold for oscillation. Figure 6-3. Rx, Cx Improve Capacitive Load Tolerance Capacitive load driving capability is enhanced by using a pullup resistor to V + (Figure 6-4). Typically, a pullup resistor conducting 500 μA or more significantly improves capacitive load responses. The value of the pullup resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. The open-loop gain of the amplifier can also be affected by the pullup resistor (see Section 5.6). Figure 6-4. Compensating for Large Capacitive Loads with a Pullup Resistor www.ti.com LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMC6032 LMC6034

6.1.4 Bias Current Testing

The test method of Figure 6-5 is appropriate for bench-testing bias current with reasonable accuracy. To understand the circuit operation, first close switch S2 momentarily. When S2 is opened, then: I b − = d V OU T dt × C 2 (7) Figure 6-5. Simple Input Bias Current Test Circuit A recommended capacitor for C2 is a 5pF or 10pF silver mica, NPO ceramic, or air-dielectric. When determining the magnitude of I b−, the leakage of the capacitor and socket must be taken into account. Leave switch S2 shorted most of the time, or else the dielectric absorption of the capacitor C2 can cause errors. Similarly, if S1 is shorted momentarily (while leaving S2 shorted), then: I b + = dV OU T dt × C 1 + C x (8) where Cx is the stray capacitance at the + input. LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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6.2 Typical Applications

Typical Single-Supply Applications Additional single-supply applications ideas are found in the LM358 data sheet. The LMC603x is pin-for-pin compatible with the LM358 and offers greater bandwidth and input resistance over the LM358. These features can improve the performance of many existing single-supply applications. Be aware, however, the supply voltage range of the LMC603x is smaller than that of the LM358. Figure 6-6. Instrumentation Amplifier If R1 = R5, R3 = R6, and R4 = R7, then AV = 100 for circuit shown. Use low-drift resistors for good CMRR performance over temperature. Matching of R3 to R6 and R4 to R7 affects CMRR. Gain is adjusted through R2. CMRR is adjusted through R7. An improved circuit can be designed using the RES11A-Q1, low-drift, precision, matched resistor pairs. Figure 6-7 shows how a precise gain of 99 is easily implemented. The capacitors are optional and are be used to improve noise performance, if needed. RES11A00-Q1 10k 10k IN IN+ LMC603x RES11A90-Q1 REF OUTLMC603x LMC603x C3 C1 C4 Figure 6-7. Improved Instrumentation Amplifier With RES11A www.ti.com LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMC6032 LMC6034

Oscillator frequency is determined by R1, R2, C1, and C2: fOSC = 1/2πRC where R = R1 = R2 and C = C1 = C2. Figure 6-8. Sine-Wave Oscillator This circuit, as shown, oscillates at 2.0kHz with a peak-to-peak output swing of 4.0V. Figure 6-9. Low-Leakage Sample-and-Hold Figure 6-10. 1Hz Square-Wave Oscillator Figure 6-11. Power Amplifier fO = 10Hz, Q = 2.1, gain = −8.8 Figure 6-12. 10Hz Bandpass Filter LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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6.3 Layout

6.3.1 Layout Guidelines

6.3.1.1 Printed Circuit Board Layout for High-Impedance Work

Generally, any circuit that operates with less than 1000pA of leakage current requires special layout of the printed circuit board (PCB). To take advantage of the ultra-low bias current of the LMC603x, typically less than 40fA, an excellent layout is essential. Fortunately, the techniques for obtaining low leakages are quite simple. Foremost, do not ignore the surface leakage of the PCB, even though the leakage can sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage can be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC603x inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, and so on, connected to the op amp inputs. See Figure 6-16. To have a significant effect, place guard rings on both the top and bottom of the PCB. This PCB foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PCB trace-to-pad resistance of 10 12Ω, which is normally considered a very large resistance, can leak 5pA if the trace were a 5V bus adjacent to the pad of an input. This causes a 100 times degradation from the LMC603x actual performance. However, if a guard ring is held within 5mV of the inputs, then even a resistance of 10 11Ω causes only 50fA of leakage current, or perhaps a minor (2:1) degradation of the amplifier performance. See Figure 6-17, Figure 6-18, Figure 6-19 for typical connections of guard rings for standard op amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide some protection; see Figure 6-20. Figure 6-16. Example of Guard Ring in PCB Layout Figure 6-17. Inverting Amplifier Guard-Ring Connections LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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7 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

7.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

7.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

7.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

7.4 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

8 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D (February 2024) Page Changes from Revision B (March 2013) to Revision C (March 2013) Page LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 www.ti.com

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9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LMC6032, LMC6034 SNOS609D – NOVEMBER 1994 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMC6032 LMC6034

www.ti.com 5-Mar-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMC6032IM/NOPB Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 LMC60 32IM LMC6032IMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LMC60 32IM LMC6032IMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LMC60 32IM LMC6032IMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LMC60 32IM LMC6032IN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LMC 6032IN LMC6032IN/NOPB.A Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LMC 6032IN LMC6032IN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LMC 6032IN LMC6034IM/NOPB Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 LMC6034IM LMC6034IMX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LMC6034IM LMC6034IMX/NOPB.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LMC6034IM LMC6034IMX/NOPB.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LMC6034IM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 1

www.ti.com 5-Mar-2026 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6032IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6032IMX/NOPB SOIC D 8 2500 353.0 353.0 32.0 LMC6034IMX/NOPB SOIC D 14 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LMC6032IN/NOPB P PDIP 8 40 506 13.97 11230 4.32 LMC6032IN/NOPB P PDIP 8 40 502 14 11938 4.32 LMC6032IN/NOPB.A P PDIP 8 40 506 13.97 11230 4.32 LMC6032IN/NOPB.A P PDIP 8 40 502 14 11938 4.32 LMC6032IN/NOPB.B P PDIP 8 40 502 14 11938 4.32 LMC6032IN/NOPB.B P PDIP 8 40 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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