LMC6024

LMC6024 Low Power CMOS Quad Operational Amplifier datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNOS621,D]
• PDF pages: 25

Technical content

www.ti.com SNOS621D –AUGUST 2000–REVISED MARCH 2013 LMC6024LowPowerCMOS QuadOperationalAmplifier Check forSamples: LMC6024 1FEATURES DESCRIPTION The LMC6024 isa CMOS quad operationalamplifier 2• Specifiedfor100 kΩ and 5 kΩ Loads whichcan operatefromeithera singlesupplyordual• High VoltageGain 120 dB supplies.Itsperformancefeaturesincludean input

• Low OffsetVoltageDrift 2.5μV/°C common-mode range thatreachesV−,low inputbias currentand voltagegain(into100 kΩ and 5 kΩ loads)• UltraLow InputBias Vurrent 40 fA thatisequaltoorbetterthanwidelyacceptedbipolar• InputCommon-mode Range IncludesV− equivalents,whilethe power supplyrequirementis
• OperatingRange from +5V to+15V Supply lessthan1 mW.
• Low Distortion 0.01% at1 kHz This chipisbuiltwithTexas Instrument'sadvanced
• Slew Rate 0.11V/μs Double-PolySilicon-GateCMOS process.
• Micropower Operation 1 mW See the LMC6022 datasheet for a CMOS dual operationalamplifierwiththesesame features.

APPLICATIONS

• High-impedance Bufferor Preamplifier
• Current-to-voltageConverter
• Long-term Integrator
• Sample-and-holdCircuit
• Peak Detector
• MedicalInstrumentation
• IndustrialControls Connection Diagram Top View Figure1. 14-PinDIP and SOIC Package See Package Number D0014A These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2000–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOS621D –AUGUST 2000–REVISED MARCH 2013 www.ti.com AbsoluteMaximum Ratings (1)(2) DifferentialInputVoltage ±SupplyVoltage SupplyVoltage(V+ − V−) 16V Lead Temperature Soldering,10 sec. 260°C StorageTemperatureRange −65°C to+150°C VoltageatOutput/InputPin (V+)+ 0.3V,(V−)− 0.3V CurrentatInputPin ±5 mA CurrentatOutputPin ±18 mA CurrentatPower SupplyPin 35 mA OutputShortCircuittoV+ See (3) OutputShortCircuittoV− See (4) JunctionTemperature 150°C ESD Tolerance(5) 1000V Power Dissipation See (6) (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothecomponent may occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand test conditions,see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) Do notconnectoutputtoV+ when V+ isgreaterthan13V orreliabilitymay be adverselyaffected. (4) Appliestobothsingle-supplyand split-supplyoperation.Continuousshortcircuitoperationatelevatedambienttemperatureand/or multipleOp Amp shortscan resultinexceedingthemaximum allowedjunctiontemperatureof150°C. Outputcurrentsinexcessof±30 mA overlongtermmay adverslyaffectreliability. (5) Human body model,100 pF dischargethrougha 1.5kΩ resistor. (6) The maximum power dissipationisa functionofTJ(max),θJA,and TA.The maximum allowablepower dissipationatany ambient temperatureisPD = (TJ(max)− TA)/θJA. OperatingRatings TemperatureRange −40°C ≤ TJ ≤ +85°C SupplyVoltageRange 4.75Vto15.5V Power Dissipation See (1) ThermalResistance(θJA)(2) 14-PinDIP 85°C/W 14-PinSOIC 115°C/W (1) Foroperatingatelevatedtemperaturesthedevicemust be deratedbased on thethermalresistanceθJA withPD = (TJ − TA)/θJA. (2) Allnumbers applyforpackagessoldereddirectlyintoa PC board.

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www.ti.com SNOS621D –AUGUST 2000–REVISED MARCH 2013 DC ElectricalCharacteristics The followingspecificationsapplyforV+ = 5V,V− = 0V,VCM = 1.5V,VO = 2.5V,and R L = 1M unlessotherwisenoted. Boldfacelimitsapplyatthetemperatureextremes;allotherlimitsTJ = 25°C. LMC6024IParameter TestConditions Typical(1) UnitsLimit(2) VOS InputOffsetVoltage 1 9 mV

11 Max

ΔVOS /ΔT InputOffsetVoltageAverage 2.5 μV/°CDrift IB InputBiasCurrent 0.04 pA

200 Max

IOS InputOffsetCurrent 0.01 pA

100 Max

R IN InputResistance >1 TeraΩ CMRR Common Mode Rejection 0V ≤ VCM ≤ 12V 83 63 dB Ratio MinV+ = 15V 61 +PSRR PositivePower Supply 5V ≤ V+ ≤ 15V 83 63 dB RejectionRatio Min61 −PSRR NegativePower Supply 0V ≤ V− ≤ −10V 94 74 dB RejectionRatio Min73 VCM InputCommon-Mode Voltage V+ = 5V and 15V −0.4 −0.1 V Range ForCMRR ≥ 50 DB Max0 MinV+ − 2.5 AV LargeSignalVoltageGain R L = 100 kΩ(3) Sourcing 1000 200 V/mV Min100 Sinking 500 90 V/mV Min40 R L = 5 kΩ(3) Sourcing 1000 100 V/mV Min75 Sinking 250 50 V/mV Min20 VO OutputVoltageSwing V+ = 5V 4.987 4.40 V R L = 100 kΩ to2.5V Min4.43 0.004 0.06 V Max0.09 V+ = 5V 4.940 4.20 V R L = 5 kΩ to2.5V Min4.00 0.040 0.25 V Max0.35 V+ = 15V 14.970 14.00 V R L = 100 kΩ to7.5V Min13.90 0.007 0.06 V Max0.09 V+ = 15V 14.840 13.70 V R L = 5 kΩ to7.5V Min13.50 0.110 0.32 V Max0.40 (1) Typicalvaluesrepresentthemost likelyparametricnorm. (2) Alllimitsareguaranteedby testingorcorrelation. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMC6024

SNOS621D –AUGUST 2000–REVISED MARCH 2013 www.ti.com DC ElectricalCharacteristics(continued) The followingspecificationsapplyforV+ = 5V,V− = 0V,VCM = 1.5V,VO = 2.5V,and R L = 1M unlessotherwisenoted. Boldfacelimitsapplyatthetemperatureextremes;allotherlimitsTJ = 25°C. LMC6024IParameter TestConditions Typical(1) UnitsLimit(2) IO OutputCurrent V+ = 5V 22 13 mA Sourcing,VO = 0V Min9SinkingVO = 5V (4) 21 13 mA Min9 V+ = 15V 40 23 mA Sourcing,VO = 0V Min15Sinking,VO = 13V (5) 39 23 mA Min15 IS SupplyCurrent AllFourAmplifiers 160 240 μA VO = 1.5V Max280 (4) Appliestobothsingle-supplyand split-supplyoperation.Continuousshortcircuitoperationatelevatedambienttemperatureand/or multipleOp Amp shortscan resultinexceedingthemaximum allowedjunctiontemperatureof150°C. Outputcurrentsinexcessof±30 mA overlongtermmay adverslyaffectreliability. (5) Do notconnectoutputtoV+ when V+ isgreaterthan13V orreliabilitymay be adverselyaffected. AC ElectricalCharacteristics The followingspecificationsapplyforV+ = 5V,V− = 0V,VCM = 1.5V,VO = 2.5V,and R L = 1M unlessotherwisenoted. Boldfacelimitsapplyatthetemperatureextremes;allotherlimitsTJ = 25°C. LMC6024IParameter TestConditions Typical(1) UnitsLimit(2) SR Slew Rate See (3) 0.11 0.05 V/μs Min0.03 GBW Gain-BandwidthProduct 0.35 MHz θM Phase Margin 50 Deg G M Gain Margin 17 dB Amp-to-Amp Isolation See (4) 130 dB en Input-ReferredVoltageNoise F = 1 kHz 42 nV/√Hz in Input-ReferredCurrentNoise F = 1 kHz 0.0002 pA/√Hz (1) Typicalvaluesrepresentthemost likelyparametricnorm. (2) Alllimitsareguaranteedby testingorcorrelation. (3) V+ = 15V.Connectedas VoltageFollowerwith10V stepinput.Number specifiedistheslowerofthepositiveand negativeslewrates. (4) Inputreferred,V+ = 15V and R L = 100 kΩ connectedto7.5V.Each amp excitedinturnwith1 kHz toproduceVO = 13 VPP .

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www.ti.com SNOS621D –AUGUST 2000–REVISED MARCH 2013 TypicalPerformance Characteristics VS = ±7.5V,TA = 25°C unlessotherwisespecified Supply Current InputBias Current vs Supply Voltage vs Temperature Figure2. Figure3. Common-Mode Voltage Range vs Output Characteristics Temperature CurrentSinking Figure4. Figure5. Output Characteristics InputVoltageNoise CurrentSourcing vs Frequency Figure6. Figure7. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMC6024

SNOS621D –AUGUST 2000–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) VS = ±7.5V,TA = 25°C unlessotherwisespecified CMRR CrosstalkRejection vs vs Frequency Frequency Figure8. Figure9. Power Supply Rejection CMRR Ratio vs vs Temperature Frequency Figure10. Figure11. Open-Loop Voltage Gain vs Open-Loop Temperature Frequency Response Figure12. Figure13.

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www.ti.com SNOS621D –AUGUST 2000–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) VS = ±7.5V,TA = 25°C unlessotherwisespecified Gain and Phase Responses Gain and Phase Responses vs vs Load Capacitance Temperature Figure14. Figure15. Gain Error (VOS vs Non-InvertingSlew Rate VOUT ) vs Temperature Figure16. Figure17. Large-SignalPulse InvertingSlew Rate Non-InvertingResponse vs Temperature (AV = +1) Figure18. Figure19. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMC6024

SNOS621D –AUGUST 2000–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) VS = ±7.5V,TA = 25°C unlessotherwisespecified Non-InvertingSmall SignalPulse Response InvertingLarge-Signal (AV = +1) Pulse Response Figure20. Figure21. Stability InvertingSmall-Signal vs Pulse Response CapacitiveLoad Avoidresistiveloadsoflessthan500Ω,as theymay cause instability. Figure22. Figure23. Stability vs CapacitiveLoad Figure24.

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www.ti.com SNOS621D –AUGUST 2000–REVISED MARCH 2013 APPLICATION HINTS AMPLIFIER TOPOLOGY The topologychosen forthe LMC6024 isunconventional(compared to general-purposeop amps) inthatthe traditionalunity-gainbufferoutputstageisnotused;instead,theoutputistakendirectlyfrom theoutputofthe integrator,to allowrail-to-railoutputswing.Since the buffertraditionallydeliversthe power to the load,while maintaininghighop amp gainand stability,and must withstandshortstoeitherrail,thesetasksnow falltothe integrator. As a resultofthesedemands, theintegratorisa compound affairwithan embedded gainstagethatisdoublyfed forward(viaC f and C ff) by a dedicatedunity-gaincompensationdriver.In addition,the outputportionof the integratorisa push-pullconfigurationfordeliveringheavy loads.Whilesinkingcurrentthewhole amplifierpath consistsof threegainstageswithone stagefed forward,whereas whilesourcingthe path containsfourgain stageswithtwo fedforward. Figure25. LMC6024 CircuitTopology (Each Amplifier) The largesignalvoltagegainwhilesourcingiscomparabletotraditionalbipolarop amps, forloadresistanceofat least5 kΩ. The gain whilesinkingishigherthan most CMOS op amps, due to the additionalgain stage; however,when drivingloadresistanceof 5 kΩ or less,the gainwillbe reduced as indicatedinthe Electrical Characterisitics.The op amp can driveloadresistanceas lowas 500Ω withoutinstability. COMPENSATING INPUT CAPACITANCE RefertotheLMC660 orLMC662 datasheetstodeterminewhetherornota feedbackcapacitorwillbe necessary forcompensationand what thevalueofthatcapacitorwouldbe. CAPACITIVE LOAD TOLERANCE Likemany otherop amps, theLMC6024 may oscillatewhen itsappliedloadappearscapacitive.The thresholdof oscillationvariesboth withloadand circuitgain.The configurationmost sensitiveto oscillationisa unity-gain follower.See theTypicalPerformanceCharacteristics. The load capacitanceinteractswiththe op amp's outputresistanceto createan additionalpole.Ifthispole frequencyissufficientlylow,itwilldegradetheop amp's phase marginso thattheamplifierisno longerstableat low gains.The additionofa smallresistor(50Ω to100Ω)inserieswiththeop amp's output,and a capacitor(5 pF to10 pF) frominvertinginputtooutputpins,returnsthephase margintoa safevaluewithoutinterferingwith lower-frequencycircuitoperation.Thus, largervaluesof capacitancecan be toleratedwithoutoscillation.Note thatinallcases,theoutputwillringheavilywhen theloadcapcitanceisnearthethresholdforoscillation. Figure26. Rx, Cx Improve CapacitiveLoad Tolerance Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMC6024

SNOS621D –AUGUST 2000–REVISED MARCH 2013 www.ti.com Capacitiveloaddrivingcapabilityisenhanced by usinga pullup resistortoV+ (Figure27).Typicallya pullup resistorconducting50 μA or more willsignificantlyimprovecapacitiveloadresponses.The valueofthepullup resistormust be determinedbased on thecurrentsinkingcapabilityoftheamplifierwithrespecttothedesired outputswing.Open loopgainof the amplifiercan alsobe affectedby the pullup resistor(see DC Electrical Characteristics). Figure27. Compensating forLarge CapacitiveLoads witha PullUp Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK Itisgenerallyrecognizedthatany circuitwhichmust operatewithlessthan1000 pA ofleakagecurrentrequires speciallayoutof the PC board.When one wishes to take advantage of the ultra-lowbias currentof the LMC6024, typicallylessthan0.04pA, itisessentialtohave an excellentlayout.Fortunately,thetechniquesfor obtaininglow leakagesare quitesimple.First,theusermust notignorethesurfaceleakageofthePC board, even though itmay sometimes appear acceptablylow,because under conditionsof highhumidityor dustor contamination,thesurfaceleakagewillbe appreciable. To minimizetheeffectofany surfaceleakage,layouta ringoffoilcompletelysurroundingtheLMC6024's inputs and the terminalsof capacitors,diodes,conductors,resistors,relayterminals,etc.connectedto the op-amp's inputs.See Figure28.To have a significanteffect,guardringsshouldbe placedon boththetopand bottomof thePC board.ThisPC foilmust thenbe connectedtoa voltagewhich isatthesame voltageas theamplifier inputs,sinceno leakagecurrentcan flowbetween two pointsatthesame potential.For example,a PC board trace-to-padresistanceof1012 ohms, whichisnormallyconsidereda verylargeresistance,couldleak5 pA ifthe tracewere a 5V bus adjacentto the pad of an input.This would cause a 100 timesdegradationfrom the LMC6024's actualperformance.However, ifa guard ringis held within5 mV of the inputs,then even a resistanceof1011 ohms would cause only0.05pA ofleakagecurrent,or perhapsa minor(2:1)degradationof theamplifier'sperformance.See Figure28,Figure30,and Figure31 fortypicalconnectionsofguard ringsfor standardop-amp configurations.Ifbothinputsareactiveand athighimpedance,theguardcan be tiedtoground and stillprovidesome protection;see Figure32. Figure28. Example ofGuard Ring inP.C.Board Layout (UsingtheLMC6024)

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www.ti.com SNOS621D –AUGUST 2000–REVISED MARCH 2013 Guard Ring Connections Figure29.InvertingAmplifierGuard Ring Figure30.Non-InvertingAmplifierGuard Ring Connections Connections Figure31.FollowerGuard Ring Connections Figure32.Howland CurrentPump Guard Ring Connections The designershouldbe aware thatwhen itisinappropriateto layout a PC board forthe sake of justa few circuits,thereisanothertechniquewhich iseven betterthan a guard ringon a PC board:Don'tinsertthe amplifier'sinputpinintothe board at all,but bend itup inthe airand use onlyairas an insulator.Airisan excellentinsulator.Inthiscase you may have toforegosome oftheadvantagesofPC board construction,but theadvantagesaresometimeswellworththeeffortofusingpoint-to-pointup-in-the-airwiring.See Figure33. (InputpinsareliftedoutofPC boardand soldereddirectlytocomponents.AllotherpinsconnectedtoPC board.) Figure33. AirWiring Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMC6024

SNOS621D –AUGUST 2000–REVISED MARCH 2013 www.ti.com BIAS CURRENT TESTING The testmethod of Figure34 is appropriateforbench-testingbias currentwith reasonableaccuracy.To understanditsoperation,firstcloseswitchS2 momentarily.When S2 isopened,then (1) Figure34. Simple InputBias CurrentTestCircuit A suitablecapacitorforC2 would be a 5 pF or 10 pF silvermica, NPO ceramic,or air-dielectric.When determiningthemagnitudeofI−,theleakageofthecapacitorand socketmust be takenintoaccount.SwitchS2 shouldbe leftshortedmost ofthetime,orelsethedielectricabsorptionofthecapacitorC2 couldcause errors. Similarly,ifS1 isshortedmomentarily(whileleavingS2 shorted) (2) where C x isthestraycapacitanceatthe+input. TypicalSingle-SupplyApplications (V+ = 5.0VDC ) A 5V biason thephotodiodecan cutitscapacitanceby a factorof2 or3,leadingtoimprovedresponseand lower noise.However,thisbiason thephotodiodewillcause photodiodeleakage(alsoknown as itsdarkcurrent). Figure35. Photodiode Current-to-VoltageConverter

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www.ti.com SNOS621D –AUGUST 2000–REVISED MARCH 2013 (V+ = 5.0VDC ) Figure36. (Upperlimitofoutputrangedictatedby inputcommon-mode range;lowerlimitdictatedby minimum current requirementofLM385.) Figure37. Micropower CurrentSource Figure38. Low-Leakage Sample-and-Hold IfR1 = R5, R3 = R6, and R4 = R7; Then ∴AV ≈ 100 forcircuitshown. Forgood CMRR overtemperature,lowdriftresistorsshouldbe used.MatchingofR3 toR6 and R4 toR7 affects CMRR. Gain may be adjustedthroughR2. CMRR may be adjustedthroughR7. Figure39. InstrumentationAmplifier Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMC6024

SNOS621D –AUGUST 2000–REVISED MARCH 2013 www.ti.com (V+ = 5.0VDC ) fO = 10 Hz Q = 2.1 Gain = −8.8 Figure40. 10 Hz Bandpass Filter fc = 10 Hz d = 0.895 Gain = 1 Figure41. 10 Hz High-Pass Filter(2dB Dip) Figure42. 1 Hz Low-Pass Filter(MaximallyFlat,Dual Supply Only)

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www.ti.com SNOS621D –AUGUST 2000–REVISED MARCH 2013 (V+ = 5.0VDC ) Gain = −46.8 Outputoffsetvoltagereducedtothe leveloftheinputoffsetvoltageof thebottomamplifier(typically1 mV), referredtoVBIAS. Figure43. High Gain AmplifierwithOffsetVoltageReduction Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMC6024

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REVISION HISTORY

Changes from RevisionC (March 2013)toRevisionD Page

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www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMC6024IM/NOPB Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LMC6024IM LMC6024IM/NOPB.A Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LMC6024IM LMC6024IM/NOPB.B Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LMC6024IM LMC6024IMX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LMC6024IM LMC6024IMX/NOPB.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LMC6024IM LMC6024IMX/NOPB.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LMC6024IM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6024IMX/NOPB SOIC D 14 2500 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LMC6024IM/NOPB D SOIC 14 55 495 8 4064 3.05 LMC6024IM/NOPB.A D SOIC 14 55 495 8 4064 3.05 LMC6024IM/NOPB.B D SOIC 14 55 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

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