LMC6001-MIL TI1 | Alldatasheet
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±VIN VOUT LMC6001 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMC6001-MIL SNOSD60 –JUNE 2017 LMC6001-MILUltra,Ultra-LowInputCurrentAmplifier
1 Features
1• (Maximum Limit, 25°C Unless Otherwise Noted)
- Input Current (100% Tested): 25 fA
- Input Current Over Temperature: 2 pA
- Low Power: 750 µA
- Low VOS: 350 µV
- Low Noise: 22 nV/√Hz at 1 kHz Typical
2 Applications
- Electrometer Amplifiers
- Photodiode Preamplifiers
- Ion Detectors
- A.T.E. Leakage Testing
3 Description
Featuring 100% tested input currents of 25 fA maximum, low operating power, and ESD protection of 2000 V, the LMC6001-MIL device achieves a new industry benchmark for low input current operational amplifiers. By tightly controlling the molding compound, Texas Instruments is able to offer this ultra-low input current in a lower cost molded package. To avoid long turnon settling times common in other low input current op amps, the LMC6001A is tested three times in the first minute of operation. Even units that meet the 25-fA limit are rejected if they drift. Because of the ultra-low input current noise of 0.13 fA/√Hz, the LMC6001-MIL can provide almost noiseless amplification of high resistance signal sources. Adding only 1 dB at 100 kΩ, 0.1 dB at 1 MΩ and 0.01 dB or less from 10 MΩ to 2,000 MΩ, the LMC6001-MIL is an almost noiseless amplifier. The LMC6001-MIL is ideally suited for electrometer applications requiring ultra-low input leakage such as sensitive photodetection transimpedance amplifiers and sensor amplifiers. Because input referred noise is only 22 nV/√Hz, the LMC6001-MIL can achieve higher signal to noise ratio than JFET input type electrometer amplifiers. Other applications of the LMC6001-MIL include long interval integrators, ultra- high input impedance instrumentation amplifiers, and sensitive electrical-field measurement circuits. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMC6001-MIL PDIP (8) 9.81 mm × 6.35 mm TO-99 (8) 9.08 mm × 9.08 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic
SNOSD60 –JUNE 2017 www.ti.com Product Folder Links: LMC6001-MIL Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table of Contents
11 Mechanical, Packaging, and Orderable
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4 Pin Configuration and Functions
NAME PDIP NO. TO-99 NO. CAN — 8 — No internal connection; connected to the external casing. +IN 3 3 I Noninverting Input –IN 2 2 I Inverting Input NC 1, 5, 8 1, 5 — No connection OUTPUT 6 6 O Output V+ 7 7 — Positive (higher) power supply V– 4 4 — Negative (lower) power supply (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely affect reliability. (4) Do not connect the output to V+, when V+ is greater than 13 V or reliability will be adversely affected.
5 Specifications
5.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX Unit Differential Input Voltage ±Supply Voltage Voltage at Input/Output Pin (V+) + 0.3 (V−) − 0.3 V Supply Voltage (V+ − V−) −0.3 +16 V Output Short Circuit to V+ See (3)(4) Output Short Circuit to V− See (3) Lead Temperature (Soldering, 10 Sec.) 260 °C Junction Temperature 150 °C Current at Input Pin ±10 mA Current at Output Pin ±30 mA Current at Power Supply Pin 40 mA Storage Temperature, Tstg −65 150 °C
SNOSD60 –JUNE 2017 www.ti.com Product Folder Links: LMC6001-MIL Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) Human body model, 1.5 kΩ in series with 100 pF.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000 V
5.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). MIN MAX UNIT VSS Supply input voltage 4.5 15.5 V TJ Operating junction temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
5.4 Thermal Information
THERMAL METRIC(1) LMC6001-MIL UNITP (PDIP) LMC (TO-99)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 100 145 °C/W RθJC(top) Junction-to-case (top) thermal resistance — 45 °C/W (1) All limits are specified by testing or statistical analysis. (2) Typical values represent the most likely parametric norm.
5.5 DC Electrical Characteristics for LMC6001AI
Limits are ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V, VCM = 1.5 V, and RL > 1 M. PARAMETER TEST CONDITIONS LMC6001AI UNIT MIN(1) TYP(2) MAX(1) IB Input Current Either Input, VCM = 0 V, VS = ±5 V 10 25 fA At the temperature extremes 2000 IOS Input Offset Current At the temperature extremes 1000 VOS Input Offset Voltage 0.7 mV At the temperature extremes 1 VS = ±5 V, VCM = 0 V At the temperature extremes 1.35 TCVOS Input Offset Voltage Drift 2.5 µV/°C RIN Input Resistance >1 TΩ CMRR Common Mode 0 V ≤ VCM ≤ 7.5 V 75 83 dB Rejection Ratio V+ = 10 V At the temperature extremes 72 +PSRR Positive Power Supply Rejection Ratio
5 V ≤ V+ ≤ 15 V
At the temperature extremes 70 −PSRR Negative Power Supply Rejection Ratio
0 V ≥ V− ≥ −10 V
At the temperature extremes 77 AV Large Signal Voltage Gain Sourcing, RL = 2 kΩ(3) 400 1400 V/mV 300 Sinking, RL = 2 kΩ(3) 180 350 At the temperature extremes 100
www.ti.com SNOSD60 –JUNE 2017 Product Folder Links: LMC6001-MIL Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Limits are ensured for TJ = 25°C unless otherwise specified. Unless otherwise specified, V+ = 5 V, V− = 0 V, VCM = 1.5 V, and RL > 1 M. PARAMETER TEST CONDITIONS LMC6001AI UNIT MIN(1) TYP(2) MAX(1) (4) Do not connect the output to V + , when V + is greater than 13 V or reliability will be adversely affected. VCM Input Common- Mode Voltage V+ = 5 V and 15 V For CMRR ≥ 60 dB VCM Low –0.4 –0.1 V At the temperature extremes 0 VCM High V+ − 2.3 V+ − 1.9 At the temperature extremes V+ − 2.5 VO Output Swing V+ = 15 V, RL = 2 kΩ to 2.5 V VO Low 0.1 0.14 V At the temperature extremes 0.17 VO High 4.8 4.87 At the temperature extremes 4.73 V+ = 15 V, RL = 2 kΩ to 7.5 V VO Low 0.26 0.35 At the temperature extremes 0.45 VO High 14.5 14.63 At the temperature extremes 14.34 IO Output Current Sourcing, V+ = 5 V, VO = 0 V 16 22 mA At the temperature extremes 10 Sinking, V+ = 5 V, VO = 5 V 16 21 At the temperature extremes 13 Sourcing, V+ = 15 V, VO = 0 V 28 30 At the temperature extremes 22 Sinking, V+ = 15 V, VO = 13 V(4) 28 34 At the temperature extremes 22 IS Supply Current V+ = 5 V, VO = 1.5 V 450 750 µA At the temperature extremes 900 V+ = 15 V, VO = 7.5 V 550 850 At the temperature extremes 950 (1) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA.
5.6 Dissipation Ratings
Power Dissipation See (1)
5.7 Typical Characteristics
Figure 1. Input Current vs. Temperature Figure 2. Input Current vs. VCM Figure 3. Supply Current vs. Supply Voltage Figure 4. Input Voltage vs. Output Voltage Figure 5. Common-Mode Rejection Ratio vs. Frequency Figure 6. Power Supply Rejection Ratio vs. Frequency
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6 Detailed Description
6.1 Overview
LMC6001-MIL has an extremely low input current of 25 fA. In addition, its ultra-low input current noise of 0.13 fA/√Hz allows almost noiseless amplification of high-resistance signal sources. LMC6001-MIL is ideally suited for electrometer applications requiring ultra-low input leakage current such as sensitive photodetection transimpedance amplifiers and sensor amplifiers.
6.2 Functional Block Diagram
6.3 Feature Description
6.3.1 Amplifier Topology
The LMC6001-MIL incorporates a novel op amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional op amps. These features make the LMC6001-MIL both easier to design with, and provide higher speed than products typically found in this low-power class.
6.3.2 Latch-up Prevention
CMOS devices tend to be susceptible to latch-up due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC6001-MIL is designed to withstand 100-mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR, there is a minimum holding current for any latch-up mode. Limiting current to the supply pins will also inhibit latch-up susceptibility.
6.4 Device Functional Modes
The LMC6001-MIL has a single functional mode and operates according to the conditions listed in Recommended Operating Conditions.
7 Applications and Implementation
validate and test their design implementation to confirm system functionality.
7.1 Application Information
7.1.1 Compensating for Input Capacitance
discussion on compensating for input capacitance. Figure 19. Cancelling the Effect of Input Capacitance
7.1.2 Capacitive Load Tolerance
resistive load in parallel with the capacitive load. See Typical Characteristics.
Figure 20. LMC6001 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads Characteristics for LMC6001AI. Figure 21. Compensating for Large Capacitive Loads with a Pullup Resistor
7.2 Typical Application
pH probes, analytic medical instruments, electrostatic field detectors and gas chromotographs. Figure 22. Typical Application Schematic, LMC6001
7.2.1 Two Op Amp, Temperature Compensated Ph Probe Amplifier
input current is an ideal choice for this application. digital panel meter. Total current consumption will be about 1 mA for the whole system.
- The LMC6001A ensures a 25-fA limit on input current at 25°C.
- The input ESD protection diodes in the LMC6042 are only rated at 500 V while the LMC6001 has much more
robust protection that is rated at 2000 V. Figure 23. Ph Probe Amplifier
7.2.1.1 Design Requirements
The theoretical output of the standard Ag/AgCl pH probe is 59.16 mV/pH at 25°C with 0 V out at a pH of 7.00. must be mounted where it will be at the same temperature as the liquid being measured.
7.2.1.2 Detailed Design Procedure
The set-up and calibration is simple with no interactions to cause problems.
- Disconnect the pH probe and with R3 set to about mid-range and the noninverting input of the LMC6001
grounded, adjust R8 until the output is 700 mV.
- Apply −414.1 mV to the noninverting input of the LMC6001. Adjust R3 for and output of 1400 mV. This
adjustments should be made by trimming while measuring a precision buffer solution.
7.2.1.3 Application Curve
Figure 24. Input Current vs. VCM
7.3 System Example
7.3.1 Ultra-Low Input Current Instrumentation Amplifier
precision matched resistors. For good CMRR over temperature, low-drift resistors should be used. ∴AV ≈ 100 for circuit shown (R2 = 9.85k). Figure 25. Instrumentation Amplifier
8 Power Supply Recommendations
and operating junction temperature.
9 Layout
9.1 Layout Guidelines
9.1.1 Printed-Circuit-Board Layout For High-Impedance Work
surface leakage will be appreciable. the trace were a 5-V bus adjacent to the pad of the input. Figure 28 for typical connections of guard rings for standard op amp configurations. Figure 26. Inverting Amplifier Figure 27. Noninverting Amplifier Figure 28. Typical Connections of Guard Rings
are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 29. (Input pins are lifted out of PCB and soldered directly to components. All other pins connected to PCB). Figure 29. Air Wiring adhered to, during all phases of inspection, test and assembly.
9.2 Layout Example
Figure 30. Examples of Guard
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
- LMC660 CMOS Quad Operational Amplifier, SNOSBZ3
- LMC662 CMOS Dual Operational Amplifier, SNOSC51
10.2 Related Links
tools and software, and quick access to sample or buy. Table 1. Related Links
10.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
10.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
10.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 29-Jun-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMC6001A MDC ACTIVE DIESALE Y 0 270 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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