LMC555_16 TI1 | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMC555 SNAS558M –FEBRUARY 2000–REVISED JULY 2016 LMC555CMOSTimer
1 Features
1• Industry's Fastest Astable Frequency of 3 MHz
- Available in Industry's Smallest 8-Bump DSBGA Package (1.43mm × 1.41mm)
- Less Than 1 mW Typical Power Dissipation at 5 V Supply
- 1.5 V Supply Operating Voltage Ensured
- Output Fully Compatible With TTL and CMOS Logic at 5 V Supply
- Tested to −10 mA, 50 mA Output Current Levels
- Reduced Supply Current Spikes During Output Transitions
- Extremely Low Reset, Trigger, and Threshold Currents
- Excellent Temperature Stability
- Pin-for-Pin Compatible With 555 Series of Timers
2 Applications
- Precision Timing
- Pulse Generation
- Sequential Timing
- Time Delay Generation
- Pulse Width Modulation
- Pulse Position Modulation
- Linear Ramp Generators
3 Description
The LMC555 device is a CMOS version of the industry standard 555 series general-purpose timers. In addition to the standard package (SOIC, VSSSOP, and PDIP) the LMC555 is also available in a chip- sized package (8-bump DSBGA) using TI's DSBGA package technology. The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation and supply current spikes. When operated as a one-shot, the time delay is precisely controlled by a single external resistor and capacitor. In the astable mode the oscillation frequency and duty cycle are accurately set by two external resistors and one capacitor. The use of TI's LMCMOS process extends both the frequency range and the low supply capability. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMC555 SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm PDIP (8) 9.81 mm × 6.35 mm DSBGA (8) 1.43 mm × 1.41 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Pulse Width Modulator Pulse Width Modulator Waveform: Top Waveform - Modulation Bottom Waveform - Output Voltage
SNAS558M –FEBRUARY 2000–REVISED JULY 2016 www.ti.com Product Folder Links: LMC555 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Table of Contents
12 Device and Documentation SupportChanged
layout of National Semiconductor Data Sheet to
12.1 Receiving Notification of Documentation Updates 18
13 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision L (February 2016) to Revision M Page Changes from Revision K (January 2015) to Revision L Page Changes from Revision J (March 2013) to Revision K Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision I (March 2013) to Revision J Page
www.ti.com SNAS558M –FEBRUARY 2000–REVISED JULY 2016 Product Folder Links: LMC555 Submit Documentation FeedbackCopyright © 2000–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
D, DGK, and P Packages 8-Pin SOIC, VSSOP, and PDIP (Top View) 8-Pin DSBGA (Top View) Pin Functions PIN I/O DESCRIPTIONSOIC, VSSOP, and PDIP NO. DSBGA NO. NAME
1 A3 GND O Ground reference voltage
2 B3 Trigger I Responsible for transition of the flip-flop from set to reset. The output of the timer depends on the amplitude of the external trigger pulse applied to this pin
3 C3 Output O Output driven waveform
4 C2 Reset I Negative pulse applied to this pin to disable or reset the timer. When not used for reset purposes, it should be connected to VCC to avoid false triggering
5 C1 Control
I Control voltage controls the threshold and trigger levels. It determines the pulse width of the output waveform. An external voltage applied to this pin can also be used to modulate the output waveform
6 B1 Threshold I Compares the voltage applied to the terminal with a reference voltage of 2/3
Vcc. The amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop.
7 A1 Discharge I Open collector output which discharges a capacitor between intervals (in phase
with output). It toggles the output from high to low when voltage reaches 2/3 of the supply voltage
8 A2 V+ I Supply voltage with respect to GND
SNAS558M –FEBRUARY 2000–REVISED JULY 2016 www.ti.com Product Folder Links: LMC555 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) See AN-1112 (SNVA009) for DSBGA considerations. (3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted.(1)(2)(3) MIN MAX UNIT Voltage Supply 15 V Input –0.3 (V+) + 0.3 V Output 15 V Curent Output 100 mA Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Temperature Range LMC555IM −40 125 °C LMC555CM/MM/N/TP −40 85 °C Maximum Allowable Power Dissipation at 25°C PDIP-8 1126 mW SOIC-8 740 mW VSSOP-8 555 mW 8-bump DSBGA 568 mW (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1) LMC555 UNITSOIC VSSOP PDIP 8-BUMP DSBGA
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 169 225 111 220 °C/W
www.ti.com SNAS558M –FEBRUARY 2000–REVISED JULY 2016 Product Folder Links: LMC555 Submit Documentation FeedbackCopyright © 2000–2016, Texas Instruments Incorporated (1) All voltages are measured with respect to the ground pin, unless otherwise specified. (2) If the RESET pin is to be used at temperatures of −20°C and below VS is required to be 2.0 V or greater.
6.5 Electrical Characteristics
Test Circuit, T = 25°C, all switches open, RESET to VS unless otherwise noted(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IS Supply Current VS = 1.5 V VS = 5 V VS = 12 V 100 150 150 250 400 µA VCTRL Control Voltage VS = 1.5 V VS = 5 V VS = 12 V 0.8 2.9 7.4 1.0 3.3 8.0 1.2 3.8 8.6 V VDIS Discharge Saturation Voltage VS = 1.5 V, IDIS = 1 mA VS = 5 V, IDIS = 10 mA 150 150 300 mV VOL Output Voltage (Low) VS = 1.5 V, IO = 1 mA VS = 5 V, IO = 8 mA VS = 12 V, IO = 50 mA 0.2 0.3 1.0 0.4 0.6 2.0 V VOH Output Voltage (High) VS = 1.5 V, IO = −0.25 mA VS = 5 V, IO = −2 mA VS = 12 V, IO = −10 mA 1.0 4.4 10.5 1.25 4.7 11.3 V VTRIG Trigger Voltage VS = 1.5V VS = 12V 0.4 3.7 0.5 4.0 0.6 4.3 V ITRIG Trigger Current VS = 5V 10 pA VRES Reset Voltage VS = 1.5 V (2) VS = 12 V 0.4 0.4 0.7 0.75 1.0 1.1 V IRES Reset Current VS = 5 V 10 pA ITHRESH Threshold Current VS = 5 V 10 pA IDIS Discharge Leakage VS = 12 V 1.0 100 nA t Timing Accuracy SW 2, 4 Closed VS = 1.5 V VS = 5 V VS = 12 V 0.9 1.0 1.0 1.1 1.1 1.1 1.25 1.20 1.25 ms Δt/ΔVS Timing Shift with Supply VS = 5V ± 1 V 0.3% V Δt/ΔT Timing Shift with Temperature VS = 5 V 75 ppm/°C fA Astable Frequency SW 1, 3 Closed, VS = 12 V 4.0 4.8 5.6 kHz fMAX Maximum Frequency Max. Freq. Test Circuit, VS = 5 V 3.0 MHz tR, tF Output Rise and Fall Times Max. Freq. Test Circuit VS = 5V, CL = 10 pF 15 ns tPD Trigger Propagation Delay VS = 5 V, Measure Delay from Trigger to Output 100 ns
7 Parameter Measurement Information
For device pinout, see Pin Configuration and Functions. Figure 1. Test Circuit For device pinout, see Pin Configuration and Functions. Figure 2. Maximum Frequency Test Circuit
www.ti.com SNAS558M –FEBRUARY 2000–REVISED JULY 2016 Product Folder Links: LMC555 Submit Documentation FeedbackCopyright © 2000–2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The LMC555 is a CMOS version of the industry standard 555 series general-purpose timers. In addition to the standard package (SOIC, VSSSOP, and PDIP) the LMC555 is also available in a chip-sized package (8-bump DSBGA) using TI’s DSBGA package technology. The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation and supply current spikes. When operated as a one-shot, the time delay is precisely controlled by a single external resistor and capacitor. In the astable mode, the oscillation frequency and duty cycle are accurately set by two external resistors and one capacitor. The use of TI’s LMCMOS process extends both the frequency range and the low supply capability. The LMC555 is available in an 8-pin PDIP, SOIC, VSSOP, and 8-bump DSBGA package.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Low-Power Dissipation
The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation. A power dissipation of less than 0.2 mW can be achieved with a 1.5-V operating supply voltage and less than 1 mW with a 5-V operating supply voltage. The use of TI’s LMCMOS process allows this low supply current and voltage capability. Reduced supply current spikes during output transitions and extremely low reset, trigger and threshold currents also provide low power dissipation advantages with the LMC555.
8.3.2 Various Packages and Compatibility
8.3.3 Operates in Both Astable and Monostable Mode
The LMC555 can operate in both astable and monostable mode depending on the application requirements.
- Monostable mode: The LMC555 timer acts as a “one-shot” pulse generator. The pulse begins when the LMC555 timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shortened depending on the application by adjusting the R and C values.
- Astable (free-running) mode: The LMC555 timer can operate as an oscillator and puts out a continuous stream of rectangular pulses having a specified frequency. The frequency of the pulse stream depends on the values of RA, RB, and C.
8.4 Device Functional Modes
8.4.1 Monostable Operation
terminal, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high. Figure 3. Monostable (One-Shot) are both directly proportional to supply voltage, the timing internal is independent of supply.
8.4.2 Astable Operation
through RB. Thus the duty cycle may be precisely set by the ratio of these two resistors. Figure 6. Astable (Variable Duty Cycle Oscillator) mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage. Figure 7 shows the waveform generated in this mode of operation. VCC = 5 V Top Trace: Output 5 V/Div. TIME = 20 µs/Div. Bottom Trace: Capacitor Voltage 1 V/Div. Figure 7. Astable Waveforms
Figure 8. Free-Running Frequency
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
specific time duration. A pushbutton is used as the trigger to output a high pulse when trigger pin is pulsed low. This simple application can be modified to fit any application requirement.
9.2 Typical Application
Figure 9 shows the schematic of the LM555 that flashes an LED in monostable mode. Figure 9. Schematic of Monostable Mode to Flash an LED
9.2.1 Design Requirements
calculated by: t= 1.1*R*C seconds.
9.2.2 Detailed Design Procedure
- RC equals 4.545 (7) If R is chosen as 100 kΩ, C = 45.4 µF. The values of R = 100 kΩ and C = 47 µF was chosen based on standard values of resistors and capacitors. A momentary push button switch connected to ground is connected to the trigger input with a 10-kΩ current limiting resistor pull up to the supply voltage. When the push button is pressed, the trigger pin goes to GND. An LED is connected to the output pin with a current limiting resistor in series from the output of the LMC555 to GND. The reset pin is not used and was connected to the supply voltage.
9.2.3 Application Curve
- Top Waveform (Blue) – Capacitor voltage
- Middle Waveform (Purple) – Trigger
- Bottom Waveform (Green) – Output As the trigger pin pulses low, the capacitor voltage starts charging and the output goes high. The output goes low as soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and C value. For this example, the time delay is 5.17 seconds.
Figure 10. Trigger, Capacitor Voltage, and Output Waveforms in Monostable Mode
9.3 Frequency Divider
cycle. Figure 12 shows the waveforms generated in a divide by three circuit. Figure 11. Monostable (One-Shot)
9.3.1 Design Requirements
Design a frequency divider by adjusting the length of the timing cycle.
9.3.2 Application Curve
Figure 12. Frequency Divider Waveforms
9.4 Pulse Width Modulator
in Figure 14 are some waveform examples. Figure 13. Pulse Width Modulator
9.4.1 Design Requirements
Modulator the output pulse width by the signal applied to the control voltage terminal.
9.4.2 Application Curve
Figure 14. Pulse Width Modulator Waveforms
9.5 Pulse Position Modulator
Figure 15. Pulse Position Modulator
9.5.1 Design Requirements
Using astable operation vary the pulse position with a modulating signal applied to the control voltage terminal.
9.5.2 Application Curve
Figure 16. Pulse Position Modulator Waveforms
Figure 17. 50% Duty Cycle Oscillator
9.6.1 Design Requirements
An oscillator with a 50% duty cycle output.
10 Power Supply Recommendations
capacitors as close as possible to the LM555 and minimize the trace length.
11 Layout
11.1 Layout Guidelines
11.2 Layout Example
The figure below is the basic layout for various applications.
- C1 – based on time delay calculations
- C2 – 0.01 µF bypass capacitor for control voltage pin
- C3 – 0.1 µF bypass ceramic capacitor
- C4 – 1-µF electrolytic bypass capacitor
- R1 – based on time delay calculations
- U1 – LMC555
Figure 18. PCB Layout
SNAS558M –FEBRUARY 2000–REVISED JULY 2016 www.ti.com Product Folder Links: LMC555 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 27-Jul-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMC555 MD8 ACTIVE DIESALE Y 0 400 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LMC555 MDA ACTIVE DIESALE Y 0 400 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 LMC555CM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC 555CM LMC555CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC 555CM LMC555CMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 ZC5 LMC555CMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 ZC5 LMC555CMMX NRND VSSOP DGK 8 3500 TBD Call TI Call TI -40 to 85 ZC5 LMC555CMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 ZC5 LMC555CMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC 555CM LMC555CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC 555CM LMC555CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC 555CN LMC555CTP/NOPB ACTIVE DSBGA YPB 8 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 F LMC555CTPX/NOPB ACTIVE DSBGA YPB 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 F LMC555IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMC 555IM LMC555IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMC 555IM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
www.ti.com 27-Jul-2016 Addendum-Page 2 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 10-May-2016 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC555CMM VSSOP DGK 8 1000 210.0 185.0 35.0 LMC555CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMC555CMMX VSSOP DGK 8 3500 367.0 367.0 35.0 LMC555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMC555CMX SOIC D 8 2500 367.0 367.0 35.0 LMC555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC555CTP/NOPB DSBGA YPB 8 250 210.0 185.0 35.0 LMC555CTPX/NOPB DSBGA YPB 8 3000 210.0 185.0 35.0 LMC555IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 10-May-2016 Pack Materials-Page 2
www.ti.com TPA08XXX (Rev A) 0.5±0.045 D E 4215100/A 12/12 A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. NOTES: D: Max = E: Max = 1.464 mm, Min = 1.438 mm, Min = 1.403 mm 1.377 mm
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