LMC2626

LMC2626 NSC | Alldatasheet

Document overview

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Technical content

Features

Y Used in conjunction with LM2625 chip Y High output current buffer Y Low buffer on resistance Y System shutdown control Y LDO voltage regulator Y LDOR dropout 0.3V maximum at 150 mA Y Thermal shutdown/short circuit protection Y External reference required for LDOR Y VREF pin converts to a digital pin to shutdown LM2625 Connection Diagram 8-Pin SO TL/H/12541–1 Top View Pin Description Pin Ý Pin Name Description 1V REF 1.218V to 1.242V Ext. Reference from LM2625 (see Note 8) 2S D System Shutdown input pin for LMC2626 and LMC2625

3 SYNC Digital input square wave from FPD

4 GND Ground

5 P5V Precision Regulated a5V Supply

6V OUT Power Buffer Output 7V IN FPD System Supply ( a4.5V to a5.5V) 8V SH Low Drop-Out Voltage Regulator Output

Ordering Information

Package Temperature Range NSC Transport b40§Ct o a85§C Drawing Media 8-Pin SO LMC2626IM M08A Rail Tape and Reel C1996 National Semiconductor Corporation RRD-B30M26/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) ESD Tolerance 2 kV HBM, 200V MM (Note 4) Sync Input Voltage P5V Supply Voltage (V IN, P5V) 6.3V Continuous Total Power Dissipation (Note 1) Lead Temperature (less than 10 sec) 260 Storage Temperature Range b65§Ct o a150§C Junction Temperature 150 §C Operating Ratings (Note 1) VIN Supply Voltage 4.5V s VIN s 5.5V P5V Supply Voltage (Note 5) 4.8V s P5V s 5.2V Junction Temperature Range b25§Ct o a125§C Ambient Temperature Range b40§Ct o a85§C Unless otherwise specified, all limits guaranteed for b20§C s TA s a85§C, P5V e 5V and 4.5V s VIN s 5.5V, V REF e 1.227V SYNC(OPEN), SD (OPEN) k P5V e VIN e 5V VSH LDO Voltage Regulator (Notes 7, 10, 11) Symbol Parameter Conditions Min Typ Max Units(Note 9) VO(VREF) VREF Voltage Level SD e 0V in Shutdown I VREF eb 1 mA 4.00 4.76 V VIN e 5V IVREF DC Current from b40.0 b13.3 b5 mAVREF Pin VSH Output Voltage on 4.5V s VIN s 5.5V VSH Pin (see Note 2) 20 mA s IL s 150 mA 4.10 4.20 4.30 V 1.218 s VREF s 1.242 DVSH Variation of V SH over 4.5V s VIN s 5.5V 4 126 mVTemperature 20 mA s IL s 150 mA VDO LDOR Voltage Dropout IL e 150 mA 0.17 0.30 V(VIN –VSH) IS(VIN) VIN Supply Current 230 394 500 mA Load Regulation of LDO 4.5V s VIN s 5.5V 0.002 0.015 %/mAVoltage Regulation 20 mA s IL s 150 mA Line Regulation of LDOR 4.5V s VIN s 5.5V 0.24 0.95 %/V20 mA s IL s 150 mA TSD Thermal Shutdown (see Note 8) 160 §CThreshold IOUT Output Load Current (see Note 2) 300 mA Shutdown Control (Note 8) Symbol Parameter Conditions Min Typ Max Units(Note 9) IIL(SD) Low Level Input Current V IN e 5V b300 b217 b150 mAfor SD Pin SD e 0V IIH(SD) High Level Input Current SD e 5V 310 1000 nAfor SD Pin Is(SD) VIN Supply Current 180 285 400 mAin Shutdown Mode Cin(SYNC) Input Capacitance SYNC e 5V 20 pFat SYNC Pin (Note 6) T A e 27§C

Unless otherwise specified, all limits guaranteed for b20§C s TA s a85§C, P5V e 5V and 4.5V s VIN s 5.5V, V REF e 1.227V SYNC(OPEN), SD (OPEN) k P5V e VIN e 5V (Continued) Buffer Symbol Parameter Conditions Min Typ Max Units(Note 9) VOUT Peak to Peak Output SYNC e 5Vpp 4.997 4.999 VVoltage Swing or V OUT (no load) VOL Low Level Output SYNC e 0V 0.2 2 mVVoltage (No Load) VOH High Level Output SYNC e 5V 4.999 VVoltage (No Load) DVOUT Variation of V OUT 0.2 1 3 mVOver Temperature VIH High Level Input 3.5 5 VSYNC, SD Voltage VIL Low Level Input 0 1.5 VSYNC, SD Voltage IIL(SYNC) Low Level Input SYNC e 0V 5.0 42 1000 nACurrent for SYNC IIH(SYNC) High Level Input SYNC e 5VDC 170 215 275 mACurrent for SYNC IOUT-AVE VOUT Maximum Average SYNC e 5VPP 100 mALoad Current from (see Note 2) RON On Resistance IL e 150 mA 0.9 1.5 XN-Channel T A e 27§C RON On Resistance IL e 150 mA 0.7 1.2 XP-Channel T A e 27§C RON On Resistance IL e 150 mA 0.18 0.6 XMatching T A e 27§C Is Supply Current No SYNC 200 355 950 mAfrom P5V

Unless otherwise specified, all limits guaranteed for T A e 27§C, V IN ee P5V e 5V. Other conditions are shown in the test circuit. Conditions that deviate from those shown in the test circuit are listed in the conditions column. Symbol Parameter Conditions Min Typ Max Units(Note 9) ts(OUT) Settling Time for V OUT To 98% p-p V OUT, 5.0 msVIN e 5V (see Note 3) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions the device is intended to be functional, but device parameter specifications may not be guaranteed under these conditions. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The typical junction-ambient thermal resistance of the molded plastic SO(M) package is 155 §C/W. Therefore the maximum current for the buffer and voltage regulator are limited to the maximum total power dissipation that the package can allow in order to keep the die comfortably below the maximum operating junction temperature of 125 §C. Note 3: The settling time of the Power Buffer is mostly dependent upon the TFT effective series RC load. The measurement of the settling time is taken for the application when driving an all black display. The number in the datasheet reflects a series RC load (R e 6.8X and C e 0.22 mF). Note 4: Human Body Model 100 pF and 1.5 k X. Machine Model 0 X. Note 5: The precision of the P5V supply determines the output voltage swing precision of the buffer for very small loads. The operating range of P5V in this datasheet assumes a g4% error in V OUT p-p such that the total error of the signal at the output of the buffer never exceeds g5%. Note 6: This capacitance is dominated by the ESD protection zeners connected to the SYNC pin. Note 7: It is important to understand that the load current of the low drop-out voltage regulator must not drop below 2 mA. Otherwise, the internal error amplifier will not have sufficient drive capability to the large series pass transistor. If load requirements from the FPD system is less than 2 mA, an external pre- Ioad resistor must be connected from V SH to ground in order to satisfy the previously mentioned load requirements. Note 8: The thermal shutdown mode of the voltage regulator and the system shutdown mode are identical. When either of the two functions are enabled, two results occur. The pass transistor of the voltage regulator is shut off and The V REF pin of the LMC2626 is pulled up to the V IN supply to shutdown the LM2625 switching regulator. Note 9: Typical values represent the most likely parametric norm. Note 10: The typical closed loop voltage gain of the low drop-out voltage regulator is 3.44(10.7 dB). Note 11: The minimum load current of the voltage regulator is a specific parameter used to guarantee that the regulated output voltage of the LDO regulator stays within the limits specified in the datasheet for 1.216V k VREF k 1.242V. For applications requiring minimum load current less than 20 mA, regulated output voltage limits of the voltage regulator and V REF voltage range must be carefully determined by characterizing the change in regulated output voltage at the minimum load current needed.

LMC2626 CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems Physical Dimensions inches (millimeters) 8-Lead (0.150 × Wide) Molded Small Outline Package, JEDEC Order Number LMC2626IM LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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