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1 Features 3 Description
The LM9061 is a charge-pump device which provides 1• Qualified for Automotive Applications the gate drive to an external power MOSFET of any• AEC-Q100 Qualified With the Following Results: size configured as a high-side driver or switch. This – Device HBM ESD Classification Level 2 includes multiple parallel connected MOSFETs for very high current applications. A CMOS logic– Device CDM ESD Classification Level C4B compatible ON/OFF input controls the output gate• Withstands 60-V Supply Transients drive voltage. In the ON state, the charge pump
- Overvoltage Shut-OFF With VCC > 30V voltage, which is well above the available VCC supply, is directly applied to the gate of the MOSFET. A built-• Lossless Overcurrent Protection Latch-OFF in 15-V Zener clamps the maximum gate to source– Current Sense Resistor is Not Required voltage of the MOSFET. When commanded OFF a– Minimizes Power Loss With High Current 110-µA current sink discharges the gate capacitances Loads of the MOSFET for a gradual turn-OFF characteristic to minimize the duration of inductive load transient• Programmable Delay of Protection Latch-OFF voltages and further protect the power MOSFET.• Gradual turn-OFF to Minimize Inductive Load Transient Voltages Lossless protection of the power MOSFET is a key feature of the LM9061. The voltage drop (VDS) across• CMOS Logic Compatible ON/OFF Control Input the power device is continually monitored and compared against an externally programmable2 Applications threshold voltage. A small current sensing resistor in
- Transmission Control Unit (TCU) series with the load, which causes a loss of available energy, is not required for the protection circuitry. If• Engine Control Unit (ECU) the VDS voltage, due to excessive load current,• Valve, Relay and Solenoid Drivers exceeds the threshold voltage, the output is latched• Lamp Drivers OFF in a more gradual fashion (through a 10-µA
- DC Motor PWM Drivers output current sink) after a programmable delay time interval.• Logic-Controlled Power Supply Distribution Switch
- Electronic Circuit Breaker Device Information(1)
- High-Power Audio Speakers PART NUMBER PACKAGE BODY SIZE (NOM) LM9061/-Q1 SOIC (8) 4.9 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. High-Side Driving and Protection to a Connected Load An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM9061,LM9061-Q1 SNOS738H –APRIL 1995–REVISED JANAURY 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (November 2014) to Revision H Page Changes from Revision F (April 1995) to Revision G Page
- Added Handling Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Changes from Revision E (April 2013) to Revision F Page
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5 Pin Configuration and Functions
NAME NO. The inverting input to the protection comparator, connected to the external MOSFET source pin andSense 1 I the load. The noninverting input to the protection comparator, and a current sink for the threshold resistor toThreshold 2 I set the allowed voltage drop across the external MOSFET. Ground 3 — Ground Output 4 O The gate drive connection. Charges, and discharges, the MOSFET gate. The voltage supply pin. The VCC operating range has a minimum value of 7 V, and a maximum valueVCC 5 I of 26 V. A resistor on this pin to ground sets the current through the threshold resistor, which sets the allowedIREF 6 O voltage drop across the external MOSFET. The control pin. A low voltage, VIN(0), will disable device operation, while a high voltage, VIN(1), willOn/Off 7 I enable device operation. A capacitor on this pin to ground will provide a delay time between when the protection comparatorDelay 8 O detects excessive VGS across the MOSFET and when the gate drive circuitry is latched-OFF. Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM9061 LM9061-Q1
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Supply Voltage 60 V Output Voltage VCC + 15 V Voltage at Sense and Threshold (through 1 kΩ) −25 60 V ON/OFF Input Voltage −0.3 VCC + 0.3 V Reverse Supply Current 20 mA Junction Temperature 150 °C Lead Temperature Soldering, 10 seconds 260 °C Storage temperature, Tstg −55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions(). Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
6.2 ESD Ratings: LM9061
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: LM9061-Q1
Human body model (HBM), per AEC Q100-002(1) ±2000 V(ESD) Electrostatic discharge All pins ±1000 VCharged-device model (CDM), per AEC Q100-011 Corner pins (1, 4, 5, and 8) ±1000 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.4 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply Voltage 7 26 V ON/OFF Input Voltage −0.3 VCC V Ambient Temperature Range: LM9061 −40 125 °C Junction Temperature Range: LM9061-Q1 −40 125 °C (1) Operating Ratings indicate conditions for which the device is intended to be functional, but may not meet the ensured specific performance limits. For ensured specifications and test conditions see the Typical Characteristics.
6.5 Thermal Information
THERMAL METRIC(1) SOIC UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 150 RθJC(top) Junction-to-case (top) thermal resistance 46.7 RθJB Junction-to-board thermal resistance 49.1 °C/W ψJT Junction-to-top characterization parameter 6.2 ψJB Junction-to-board characterization parameter 48.4 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM9061 LM9061-Q1
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6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) 7V ≤ VCC ≤ 20V, RREF = 15.4 kΩ, −40°C ≤ TJ ≤ +125°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY IQ Quiescent Supply Current ON/OFF = “0” 5 mA ON/OFF = “1”, CLOAD = 0.025 µF, ICC Operating Supply Current Includes Turn-ON 40 mA Transient Output Current ON/OFF CONTROL INPUT VIN(0) ON/OFF Input Logic “0” VOUT = OFF 1.5 V VIN(1) ON/OFF Input Logic “1” VOUT = ON 3.5 V VHYST ON/OFF Input Hysteresis Peak to Peak 0.8 2 V IIN ON/OFF Input Pull-Down Current VON/OFF = 5 V 50 250 µA GATE DRIVE OUTPUT VOH Charge Pump Output Voltage ON/OFF = “1” VCC + 7 VCC + 15 V VOL OFF Output Voltage ON/OFF = “0”, ISINK = 110 µA 0.9 V Sense to Output ON/OFF = “1,VCLAMP 11 15 VClamp Voltage VSENSE = VTHRESHOLD ISINK(Normal- Output Sink Current ON/OFF = “0”, VDELAY = 0 V, 75 145 µA OFF) Normal Operation VSENSE = VTHRESHOLD Output Sink Current with VDELAY = 7 V,ISINK(Latch-OFF) 5 15 µAProtection Comparator Tripped VSENSE < VTHRESHOLD PROTECTION CIRCUITRY VREF Reference Voltage 1.15 1.35 V IREF Threshold Pin Reference Current VSENSE = VTHRESHOLD 75 88 µA VCC = Open, 7 V ≤ VTHRESHOLD ≤ 20ITHR(LEAKAGE) Threshold Pin Leakage Current 10 µAV ISENSE Sense Pin Input Bias Current VSENSE = VTHRESHOLD 10 µA DELAY TIMER VTIMER Delay Timer Threshold Voltage 5 6.2 V Discharge Transistor SaturationVSAT IDIS = 1 mA 0.4 VVoltage IDIS Delay Capacitor Discharge Current VDELAY = 5 V 2 10 mA IDELAY Delay Pin Source Current 6.74 15.44 µA
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6.7 Switching Characteristics
7V ≤ VCC ≤ 20V, RREF = 15.4 kΩ, −40°C ≤ TJ ≤ +125°C, CLOAD = 0.025 µF, CDELAY = 0.022 µF, unless otherwise specified. reference purposes only. Smaller load capacitances will have proportionally faster turn-ON and turn-OFF times. Figure 1. Typical Operating Waveforms
Figure 2. Timing Definitions
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6.8 Typical Characteristics
Figure 3. Standby Supply Current vs VCC Figure 4. Operating Supply Current vs VCC Figure 6. Output Sink Current vs TemperatureFigure 5. Output Voltage vs VCC Figure 7. Output Sink Current vs Temperature Figure 8. Output Source Current vs Output Voltage
Figure 9. Reference Voltage vs Temperature Figure 10. Delay Threshold vs Temperature Figure 11. Delay Charge Current vs Temperature
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7 Detailed Description
7.1 Overview
The LM9061 is a high-side controller that can protect the load from overcurrent and overvoltage. An internal charge pump circuit generates the gate voltage to drive the high-side MOSFET. The voltage drop, VDS, across the MOSFET is monitored to protect from excessive current. Should the VDS voltage, due to excessive load current, exceed the threshold voltage, the output is latched OFF after a programmable delay time interval.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 MOSFET Gate Drive
The LM9061 contains a charge pump circuit that generates a voltage in excess of the applied supply voltage to provide the gate drive to high-side MOSFET transistors. Any size of N-channel power MOSFET, including multiple parallel connected MOSFETs for very high current applications, can be used to apply power to a ground referenced load circuit in what is referred to as “high-side drive” applications. Figure 12 shows the basic application of the LM9061. Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM9061 LM9061-Q1
Figure 12. Basic Application Circuit
7.3.2 Basic Operation
of the LM9061 is clamped to limit the maximum VGS to 15 V. reaches VCC, the output current will typically be 1 mA with VCC at 14 V. sinking current is only 10 µA (see Lossless Overcurrent Protection).
7.3.3 Turn On and Turn Off Characteristics
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LM9061,LM9061-Q1 www.ti.com SNOS738H –APRIL 1995–REVISED JANAURY 2015 Feature Description (continued) towards the VCC supply of the LM9061. The source current from pin 4 is typically 30 mA which quickly charges CGD and CGS. As soon as the gate reaches the VGS(ON) threshold of the MOSFET, the switch turns ON and the source voltage starts rising towards VCC. VGS remains equal to the threshold voltage until the source reaches VCC. While VGS is constant only CGD is charging. When the source voltage reaches VCC, at time t2, the charge pump takes over the drive of the gate to ensure that the MOSFET remains ON. The charge pump is basically a small internal capacitor that acquires and transfers charge to the output pin. The clock rate is set internally at typically 300 kHz. In effect the charge pump acts as a switched capacitor resistor (approximately 67k) connected to a voltage that is clamped at 13V above the Sense input pin of the LM9061 which is equal to the VCC supply in typical applications. The gate voltage rises above VCC in an exponential fashion with a time constant dependent upon the sum of CGD and CGS. At this time however the load is fully energized. At time t3, the charge pump reaches its maximum potential and the switch remains ON. At time t4, the ON/OFF input goes low to turn OFF the MOSFET and remove power from the load. At this time the charge pump is disconnected and an internal 110 µA current sink begins to discharge the gate input capacitances to ground. The discharge rate (ΔV/ΔT) is equal to 110 µA/ (CGD + CGS). The load is still fully energized until time t5 when the gate voltage has reached a potential of the source voltage (VCC) plus the VGS(ON) threshold voltage of the MOSFET. Between time t5 and t6, the VGS voltage remains constant and the source voltage follows the gate voltage. With the voltage on CGD held constant the discharge rate now becomes 110 µA/CGD. At time t6 the source voltage reaches 0V. As the gate moves below the VGS(ON) threshold the MOSFET tries to turn OFF. With an inductive load, if the current in the load has not collapsed to zero by time t6, the action of the MOSFET turning OFF will create a negative voltage transient (flyback) across the load. The negative transient will be clamped to −VGS(ON) because the MOSFET must turn itself back ON to continue conducting the load current until the energy in the inductance has been dissipated (at time t7).
7.3.4 Lossless Overcurrent Protection
A unique feature of the LM9061 is the ability to sense excessive power dissipation in the MOSFET and latch it OFF to prevent permanent failure. Instead of sensing the actual current flowing through the MOSFET to the load, which typically requires a small valued power resistor in series with the load, the LM9061 monitors the voltage drop from drain to source, VDS, across the MOSFET. This “lossless”technique allows all of the energy available from the supply to be conducted to the load as required. The only power loss is that of the MOSFET itself and proper selection of a particular power device for an application will minimize this concern. Another benefit of this technique is that all applications use only standard inexpensive ¼W or less resistors. To use this lossless protection technique requires knowledge of key characteristics of the power MOSFET used. In any application the emphasis for protection can be placed on either the power MOSFET or on the amount of current delivered to the load, with the assumption that the selected MOSFET can safely handle the maximum load current. Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LM9061 LM9061-Q1
Figure 13. Turn ON and Turn OFF Waveforms will never exceed its rated maximum. RDS(ON) of discrete MOSFETs is rarely specified) over the required operating temperature range. event that the load is inadvertently shorted to ground, the power device will automatically be turned-OFF. is switched to only 10 µA to gradually turn OFF the power device. Figure 14 illustrates how the threshold voltage for the internal protection comparator is established.
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VDS across the MOSFET before the protection comparator trips. the ensured performance characteristics it is recommended that a 15.4-kΩ resistor be used for RREF. Figure 14. Protection Comparator Biasing
- RREF = 15.4 kΩ.
- ISENSE is the input bias current to the protection comparator.
- RSENSE is the resistor connected to pin 1.
- VOS is the offset voltage of the protection comparator (typically in the range of ±10 mV). (5) Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LM9061 LM9061-Q1
voltage at the inverting input (Sense). larger than 0.1 µF, and is not needed for most applications.
7.3.5 Delay Timer
timer function is provided. This timer delays the actual latching OFF of the MOSFET for a programmable interval. latch the MOSFET OFF. It will not restart until the ON/OFF Input is toggled low then high.
- Typically, VTIMER = 5.5 V.
- IDELAY = 10 µA. (6) Charging of the delay capacitor is clamped at approximately 7.5 V which is the internal bias voltage for the 10 µA current source.
Figure 15. Delay Timer
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7.3.5.1 Minimum Delay Time
OFF thereby never allowing the load to be energized. (TSTART-UP). Some experimentation is required if a specific minimum delay time characteristic is desired. In the absence of a specific delay time requirement, TI recommends a value for CDELAY of 0.1 µF.
7.3.6 Overvoltage Protection
normal operating range the device will return to normal operation without requiring toggling the ON/OFF input. transients, such as automotive applications. of a Zener on the Sense input (pin 1) will provide a maximum voltage reference for the Protection Comparator. MOSFET will be latched off. The ON/OFF input must be toggled to restart the MOSFET. Figure 16. Adding Overvoltage Protection
7.3.7 Reverse Battery
significantly from the charge pump gate overdrive output voltage.
7.3.8 Low Battery
pump will be disabled and the gate will be discharged at the Normal-OFF current sink rate, typically 110 μA. overvoltage latch-OFF, and overcurrent latch-OFF. and the LM9061 will be turned off. Figure 17. Electronic Circuit Breaker
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7.3.9 Increasing MOSFET Turnon Time
recalculated with the extended switching transition time. Figure 18. Increasing MOSFET Turnon Time
LM9061,LM9061-Q1 SNOS738H –APRIL 1995–REVISED JANAURY 2015 www.ti.com
7.4 Device Functional Modes
7.4.1 Operation With VCC > 30 V
If VCC increases to more than typically 30 V the LM9061 will turn off the MOSFET to protect the load from excessive voltage. When VCC has returned to the normal operating range the device will return to normal operation without requiring toggling the ON/OFF input. This feature will allow MOSFET operation to continue in applications that are subject to periodic voltage transients, such as automotive applications. 7.4.2 Operation With VCC < 6.2 V When VCC falls below the UVSO threshold of 6.2 V the charge pump will be disabled and the gate will be discharged at the Normal-OFF current sink rate, typically 110 μA.
7.4.3 Operation With ON/OFF Control
In the ON state, the charge pump voltage, which is well above the available VCC supply, is directly applied to the gate of the MOSFET. When commanded OFF a 110 µA current sink discharges the gate capacitances of the MOSFET for a gradual turn-OFF characteristic to minimize the duration of inductive load transient voltages and further protect the power MOSFET.
7.4.4 MOSFET Latch-OFF
In the event of excessive power dissipation in the MOSFET as detected by the LM9061 sense and threshold pins, the MOSFET is latched OFF to prevent permanent failure. It will not restart until the ON/OFF Input is toggled low then high.
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
gate drive operation and Turn On and Turn Off Characteristics for details on the gate drive timing characteristics.
8.2 Typical Application
Figure 19. Driving Multiple MOSFETs
8.2.1 Design Requirements
discharge the total gate capacitance in a timely manner to prevent damage to the MOSFETs.
8.2.2 Detailed Design Procedure
RTHRESHOLD value of 6.2 kΩ as shown in Figure 19 will set the VDS threshold voltage to approximately 500 mV. at 125°C. See Lossless Overcurrent Protection for details on calculating RTHRESHOLD. possible when operating near the maximum load currents.
8.2.3 Application Curves
Figure 20. MOSFET Gate During Start-up, Total Gate Figure 21. MOSFET Gate During Shut Down, Total Gate
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9 Power Supply Recommendations
It is important to remember that during the Turn-ON of the MOSFET the output current to the Gate is drawn from the VCC supply pin. The VCC pin should be bypassed with a capacitor with a value of at least ten times the Gate capacitance, and no less than 0.1 μF. If the VCC supply should be taken negative with respect to ground, for example during a reverse battery condition, the current from the VCC pin should be limited to 20 mA. The addition of a diode in series with the VCC input is recommended. This diode drop does not subtract significantly from the charge pump gate overdrive output voltage.
10 Layout
10.1 Layout Guidelines
- The bypass capacitor for VCC should be placed as close as possible to the VCC pin. 2. The resistor RREF should be placed as close as possible to the IREF and Ground pins with minimal trace length to keep the IREF current as accurate as possible. The LM9061 is optimized for use with a 15.4 kΩ ±1% resistor for RREF. 3. In applications where the VCC supply is subject to high levels of transient noise, a bypass capacitor across RREF is recommended. This bypass capacitor should be no larger than 0.1 μF and should be placed as close as possible to the IREF pin. 4. The RTHRESHOLD and RSENSE resistors should be placed as close as possible to the MOSFET drain and source pins respectively. This will allow accurate monitoring of the VDS voltage across the MOSFET. 5. An array of vias can be placed along the high current path to the output load. These vias can help conduct heat to any inner plane areas or to a bottom-side copper plane.
10.2 Layout Example
Figure 22 and Figure 23 are layout examples for the LM9061/LM9061-Q1. These examples are taken from the LM9061EVM. For information on the operation and schematic of the EVM, see the LM9061EVM User's Guide (SNOU132). Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: LM9061 LM9061-Q1
Figure 22. LM9061EVM Layout Example (Top)
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Figure 23. LM9061EVM Layout Example (Bottom)
11 Device and Documentation Support
11.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 1. Related Links
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 31-Jan-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM9061M LIFEBUY SOIC D 8 95 TBD Call TI Call TI -40 to 125 LM90 61M LM9061M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM90 61M LM9061MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM90 61M LM9061QDQ1 PREVIEW SOIC D 8 TBD Call TI Call TI -40 to 125 9061Q1 LM9061QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168HRS -40 to 125 9061Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
www.ti.com 31-Jan-2016 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM9061, LM9061-Q1 :
- Catalog: LM9061
- Automotive: LM9061-Q1 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 7-Jan-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM9061MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM9061QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jan-2015 Pack Materials-Page 2
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