LM87CIMT

LM87 TI | Alldatasheet

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 LM87SerialInterfaceSystemHardwareMonitorwithRemoteDiodeTemperatureSensing Check forSamples: LM87 1FEATURES DESCRIPTION The LM87 is a highlyintegrateddata acquisition 234• Remote diode temperaturesensing (2 system forhardwaremonitoringofservers,Personalchannels) Computers, or virtuallyany microprocessor-based• 8 positivevoltageinputswithscalingresistors system.In a PC, the LM87 can be used to monitor formonitoring+5 V,+12 V,+3.3V,+2.5V, power supplyvoltages,motherboardand processor Vccp power suppliesdirectly temperatures,and fan speeds. Actual values for theseinputscan be read atany time.Programmable• 2 inputsselectableforfanspeed or voltage WATCHDOG limitsin the LM87 activatea fullymonitoring programmable and maskable interruptsystem with• 8-bitDAC outputforcontrollingfanspeed two outputs(INT#and THERM#).

• Chassis IntrusionDetectorinput The LM87 has an on-chipdigitaloutputtemperature• WATCHDOG comparison ofallmonitored sensorwith8-bitresolutionas wellas thecapabilityofvalues monitoring2 externaldiode temperaturesto 8-bit resolution,an 8 channelanaloginputADC with8-bit• SMBus ™ or I2C SerialBus interface resolutionand an 8-bitDAC. A channelon theADCcompatibility measures the supplyvoltageappliedto the LM87,• VID0-VID4or IRQ0-IRQ4 monitoringinputs nominally3.3 V. Two of the ADC inputscan be• On chiptemperaturesensor redirectedtoa counterthatcan measure thespeed of up to 2 fans.A slow speed ΣΔ ADC architecture APPLICATIONS allowsstablemeasurement ofsignalsinan extremely noisyenvironment.The DAC, witha 0 to2.5V output• System Thermal and Hardware Monitoringfor voltagerange,can be used forfan speed control.Servers,Workstationsand PCs Additionalinputsare providedforChassis Intrusion
• Networking and Telecom Equipment detectioncircuits,and VID monitorinputs.The VID monitorinputscan alsobe used as IRQ inputsifVID• OfficeElectronics monitoringis not required.The LM87 has a Serial• ElectronicTestEquipment and Bus interfacethatiscompatiblewithSMBus ™ andInstrumentation I2C ™ . KEY SPECIFICATIONS Connection Diagram
• VoltageMonitoringError±2 % (max)
• ExternalTemperature Error±4 °C (max)
• InternalTemperature Error – −40 °C to+125 °C ± 3 °C (typ)
• Supply VoltageRange 2.8to3.8V
• Supply Current0.7mA (typ)
• ADC and DAC Resolution8 Bits
• Temperature Resolution1.0°C Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2SMBus isa trademarkofIntelCorporation. 3I2C isa trademarkofdcl_owner. 4Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2000–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com Block Diagram

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 PIN DESCRIPTIONS (1) Pin Pin Number Type DescriptionName(s) Number ofPins Thispinnormallyfunctionsas a three-stateinputthatcontrolsthetwo LSBs of theSerialBus Address.When thispinistiedtoVCC thetwo LSBs are01. When tiedtoGround,thetwo LSBs are10.Ifthispinisnotconnected,thetwo LSBs are00.Thispinalsofunctionsas an outputduringNAND TreetestsADD/NTEST_OUT 1 1 DigitalI/0 (board-levelconnectivitytesting).To ensureproperNAND treefunction,this pinshouldnotbe tieddirectlytoVCC orGround.Instead,a series5 kΩ resistor shouldbe used toallowthetestoutputfunctiontowork.RefertoNAND TREE TESTS on NAND Treetesting. Thispinfunctionsas an open-draininterruptoutputfortemperatureinterrupts THERM# 2 1 DigitalI/O only,oras an interruptinputforfancontrol.Ithas an on-chip100 kΩ pullup resistor. SMBData 3 1 DigitalI/O SerialBus bidirectionalData.Open-drainoutput. SMBCLK 4 1 DigitalInput SerialBus Clock. FAN1/AIN1- Analog/DigitalProgrammable as analoginputs(0to2.5V)ordigitalSchmittTriggerfan5-6 2FAN2/AIN2 Inputs tachometerinputs. An activehighinputfroman externalcircuitwhichlatchesa ChassisIntrusion event.Thislinecan go highwithoutany clampingactionregardlessofthe CI 7 1 DigitalI/O powered stateoftheLM87. Thereisalsoan internalopen-drainoutputon this line,controlledby Bit7 oftheCI ClearRegister(46h),toprovidea minimum 20 ms pulse. The systemgroundpin.Internallyconnectedtoallcircuitry.The ground referenceforallanaloginputsand theDAC output.Thispinneeds tobeGND 8 1 GROUND connectedtoa lownoiseanaloggroundplaneforoptimum performanceofthe DAC output. Interruptactivelowopen-drainoutput.Thisoutputisenabledwhen Bit1 inthe ConfigurationRegisterissetto1.The defaultstateisdisabled.Ithas an on-INT# /ALERT# 10 1 DigitalOutput chip100 kΩ pullupresistor.Alternatelyused as an activelowoutputtosignal SMBus AlertResponse Protocol. Analog 0 V to+2.5V amplitude8-bitDAC output.When forcedhighon power up by DACOut/NTEST_IN 11 1 Output/Digitalan externalvoltagetheNAND TreeTestmode isenabledwhichprovides Input board-levelconnectivitytesting. MasterReset,5 mA driver(open-drain),activelowoutputwitha 20 ms minimum pulsewidth.Availablewhen enabledviaBit4 intheConfigurationRESET# 12 1 DigitalI/O register.Italsoactsas an activelowpower on RESET input.Ithas an on-chip 100 kΩ pullupresistor. AnaloginputformonitoringthecathodeofthefirstexternaltemperatureD1 − 13 1 AnalogInput sensingdiode. Analoginputformonitoringtheanode ofthefirstexternaltemperaturesensingD1+ 14 1 AnalogInput diode. +12Vin 15 1 AnalogInput Analoginputformonitoring+12 V. +5Vin 16 1 AnalogInput Analoginputformonitoring+5 V. DigitallyprogrammableanaloginputformonitoringVccp2 (0to3.6V inputVccp2/D2− 17 1 AnalogInput range)orthecathodeofthesecond externaltemperaturesensingdiode. Digitallyprogrammableanaloginputformonitoring+2.5V ortheanode ofthe+2.5Vin/D2+ 18 1 AnalogInput second externaltemperaturesensingdiode. Analoginput(0to3.6V inputrange)formonitoringVccp1,thecorevoltageofVccp1 19 1 AnalogInput processore1. Digitallyprogrammabledualfunctiondigitalinputs.Can be programmed to monitortheVID pinsofthePentium/PRO and PentiumIIprocessors,thatVID4/IRQ4- 20-24 5 DigitalInputs indicatetheoperatingvoltageoftheprocessor,oras interruptinputs.TheVID0/IRQ0 valuesarereadintheVID/FanDivisorRegisterand theVID4 Register.These inputshave on-chip100 kΩ pullupresistors. TOTAL PINS 24 (1) # IndicatesActiveLow (“Not”) Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2)(3)(4) PositiveSupplyVoltage(V+) +6.0V Voltageon Any InputorOutputPin: +12Vin −0.3V to+16 V ADD/NTESTOUT, DACOut/NTEST_IN, AIN1,AIN2 −0.3V to(V++ 0.3V) Allotherpins −0.3V to+6 V InputCurrentatany Pin (5) ±5 mA Package InputCurrent(5) ±20 mA Maximum JunctionTemperature (TJ max) 150 °C ESD Susceptibility(6) Human Body Model 2500 V Machine Model 150V StorageTemperature −65 °C to+150 °C Forsolderingspecifications: See productfolderatwww.ti.comand http://www.ti.com/lit/SNOA549 (1) Allvoltagesaremeasured withrespecttoGND, unlessotherwisespecified. (2) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. V+ + 0.55V or6 V,whicheverissmaller. (4) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (5) When theinputvoltage(VIN)atany pinexceedsthepower supplies(VIN< GND orVIN>V +),thecurrentatthatpinshouldbe limitedto 5 mA. The 20 mA maximum package inputcurrentratinglimitsthenumber ofpinsthatcan safelyexceed thepower supplieswithan inputcurrentof5 mA tofour. (6) The human body model isa 100 pF capacitordischargedthrougha 1.5kΩ resistorintoeach pin. OperatingRatings (1)(2) OperatingTemperatureRange T MIN ≤ TA ≤ TMAX LM87 −40 °C ≤ TA ≤ +125 °C SpecifiedTemperatureRange T MIN ≤ TA ≤ TMAX LM87 −40 °C ≤ TA ≤ +125 °C JunctiontoAmbientThermalResistance(θJA (3)) SupplyVoltage(V+) +2.8V to+3.8V V IN VoltageRange: +12Vin −0.05V to+15 V +5Vin −0.05V to+6.0V +3.3Vin −0.05V to+4.6V +2.5Vin −0.05V to+3.6V VID0 -VID4,Vccp,FAN1, FAN2, SMBCLK, SMBDATA −0.05V to+6.0V Allotherinputs −0.05V to(V++ 0.05V) (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND, unlessotherwisespecified. (3) The maximum power dissipationmust be deratedatelevatedtemperaturesand isdictatedby TJmax, θJA and theambienttemperature, TA.The maximum allowablepower dissipationatany temperatureisPD = (TJmax −TA)/θ JA.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 DC ElectricalCharacteristics The followingspecificationsapplyfor+2.8VDC ≤ V+ ≤ +3.8VDC ,AnalogvoltageinputsR S = 510 Ω,unlessotherwisespecified. BoldfacelimitsapplyforTA = T J = TMIN toTMAX ;allotherlimitsTA = TJ = 25 °C.(1) Typical Limits Units Symbol Parameter Conditions (2) (3) (Limits) POWER SUPPLY CHARACTERISTICS Normal Mode, Interface 0.7 2.0 mA (max) InactiveI+ SupplyCurrent Shutdown Mode 0.5 mA TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS TemperatureErrorusingInternalDiode ±3 °C TemperatureErrorusingRemote PentiumDiode 0 °C ≤ TA ≤ +125 °C, Vcc = ±3 °C (max) Sensor (4)and (5) 3.3Vdc TemperatureErrorusingRemote 2N3904 Sensor −40 °C ≤ TA ≤ +125 °C, Vcc ±4 °C (max) (4)and (5) = 3.3Vdc Resolution 8 bits 1.0 °C (min) LM87 ANALOG-TO-DIGITAL CONVERTER CHARACTERISTICS Resolution 8 bits TUE TotalUnadjustedError (6) ±2 % (max) DNL DifferentialNon-Linearity ±1 LSB (max) tC TotalMonitoringCycleTime (7) 0.28 sec ADC INPUT CHARACTERISTICS InputResistance(AllanaloginputsexceptAIN1 130 90 kΩ (min)and AIN2) AIN1 and AIN2 DC InputCurrent 12 μA DAC CHARACTERISTICS Resolution 8 Bits V,Code = 255 V+ = 3.3V,3/4Scale,code +3.7 %DAC Error 192 3.3V,Code = 8(8) R L OutputLoad Resistance VO = 2.5V 1250 Ω (min) C L OutputLoad Capacitance 20 pF (max) (1) Parasiticsand orESD protectioncircuitryareshown inFigure2 fortheLM87 's pins.The nominalbreakdown voltageofthezenerD3 is 6.5V.Care shouldbe takennottoforwardbiastheparasiticdiode,D1, presenton pins:A0/NTEST_OUT, A1 and DACOut/NTEST_IN. Doingso by more than50 mV may corrupta temperatureorvoltagemeasurement. (2) TypicalsareatTJ = TA = 25 °C and representmost likelyparametricnorm. (3) LimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel). (4) The TemperatureErrorspecificationdoes notincludean additionalerrorof±1°C, caused by thequantizationerror. (5) The TemperatureErrorwillvarylessthan±1°C overtheoperatingVcc rangeof2.8Vto3.8V. (6) TUE (TotalUnadjustedError)includesOffset,Gain and LinearityerrorsoftheADC. (7) TotalMonitoringCycleTime includesalldiodechecks,temperatureconversionsand analoginputvoltageconversions.Fan tachometer readingsaredeterminedseparatelyand do notaffectthecompletionofthemonitoringcycle. (8) ThisisthelowestDAC code specifiedtogivea non-zeroDAC output. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com DC ElectricalCharacteristics(continued) The followingspecificationsapplyfor+2.8VDC ≤ V+ ≤ +3.8VDC ,AnalogvoltageinputsR S = 510 Ω,unlessotherwisespecified. BoldfacelimitsapplyforTA = T J = TMIN toTMAX ;allotherlimitsTA = TJ = 25 °C.(1) Typical Limits Units Symbol Parameter Conditions (2) (3) (Limits) FAN RPM-TO-DIGITAL CONVERTER Fan RPM Error −10 °C ≤ TA ≤ +100 °C ±15 % (max) Full-scaleCount 255 (max) Divisor= 1,Fan Count = 153 8800 RPM (9) Divisor= 2,Fan Count = 153 4400 RPM (9) FAN1 and FAN2 NominalInput RPM (See FAN INPUTS ) Divisor= 3,Fan Count = 153 2200 RPM (9) Divisor= 4,Fan Count = 153 1100 RPM (9) DIGITAL OUTPUTS (NTEST_OUT) IOUT = ±3.0mA at 2.4 V (min)VOUT(1) Logical“1”OutputVoltage V+ = +2.8V IOUT = ±3.0mA at 0.4 V (max)VOUT(0) Logical“0”OutputVoltage V+ = +3.8V OPEN- DRAIN DIGITAL OUTPUTS (SMBData, RESET#, CI,INT#,THERM#) VOUT(0) Logical“0”OutputVoltage(SMBData) IOUT = −755 μA 0.4 V (min) VOUT(0) Logical“0”OutputVoltage(Others) IOUT = −3 mA 0.4 V (min) IOH HighLevelOutputCurrent VOUT = V+ 5 12 μA (max) RESET# and ChassisIntrusion 45 20 ms (min) PulseWidth DIGITAL INPUTS: VID0–VID4,NTEST_IN, ADD/NTEST_OUT, Chassis Intrusion(CI) VIN(1) Logical“1”InputVoltage 2.0 V (min) VIN(0) Logical“0”InputVoltage 0.8 V (max) SMBus DIGITAL INPUTS (SMBCLK, SMBData) VIN(1) Logical“1”InputVoltage 2.1 V (min) VIN(0) Logical“0”InputVoltage 0.8 V (max) VHYST InputHysteresisVoltage 243 mV Tach Pulse Logic Inputs(FAN1, FAN2) VIN(1) Logical“1”InputVoltage 0.7× V+ V (min) VIN(0) Logical“0”InputVoltage 0.3× V+ V (max) ALL DIGITAL INPUTS IIN(1) Logical“1”InputCurrent VIN = V+ −12 μA (min) IIN(0) Logical“0”InputCurrent VIN = 0 VDC 12 μA (max) C IN DigitalInputCapacitance 20 pF (9) The totalfancountisbased on 2 pulsesperrevolutionofthefantachometeroutput.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 AC ElectricalCharacteristics The followingspecificationsapplyfor+2.8VDC ≤V+ ≤ +3.8VDC on SMBCLK and SMBData, unlessotherwisespecified. BoldfacelimitsapplyforTA = TJ = TMIN toTMAX ;allotherlimitsT A = TJ = 25°C. (1) Typical Limits Units Symbol Parameter Conditions (2) (3) (Limits) SERIAL BUS TIMING CHARACTERISTICS t1 SMBCLK (Clock)Period 2.5 μs (min) trise SMBCLK and SMBData RiseTime 1 μs (max) tfall SMBCLK and SMBData FallTime 300 ns (max) t2 Data InSetupTime toSMBCLK High 100 ns (min) 100 ns (min) t3 Data Out StableAfterSMBCLK Low 300 ns (max) t4 SMBData Low SetupTime toSMBCLK Low (start) 100 ns (min) t5 SMBData HighHoldTime AfterSMBCLK High 100 ns (min) (stop) 31 msSMBCLK lowtimerequiredtoresettheSerialBustTIMEOUT 25 ms (min)InterfacetotheIdleState 35 ms (max) C L CapacitiveLoad on SMBCLK and SMBData 80 pF (max) (1) Timingspecificationsaretestedatthespecifiedlogiclevels,VILfora fallingedge and VIH fora risingedge. (2) TypicalsareatTJ = TA = 25 °C and representmost likelyparametricnorm. (3) LimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel). Figure1. SerialBus Timing Diagram Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com Pin Name D1 D2 D3 R1 R2 R3 R4 Pin Name D1 D2 D3 R1 R2 R3 R4 INT# x(1) x x 0 ∞ 100 1M +12Vin x x R1+R2 ∞ k ≈130k CI x x x 0 ∞ ∞ 1M +5Vin x x R1+R2 ∞ ≈130k FAN1 –FAN2 x x x 0 ∞ ∞ 1M +3.3Vin,+2.5Vin,Vccp1, x x x R1+R2 ∞ 1M Vccp2 ≈130k SMBCLK x x x 0 ∞ ∞ 1M THERM x x x 0 ∞ 100 1M k SMBData x x x 0 ∞ ∞ 1M VID4–VID0 x x x 0 ∞ 100 1M k RESET# x x x 0 ∞ 100 1M DACOut/NTEST_IN x x x 0 ∞ ∞ 1M k ADD/NTEST_OUT x x x 0 ∞ ∞ 1M (1) An x indicatesthatthediodeexists. Figure2. ESD ProtectionInputStructure TestCircuit Figure3. DigitalOutput Load TestCircuitry

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 TypicalPerformance Characteristics DAC Power Supply Sensitivity Figure4. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION GENERAL DESCRIPTION The LM87 provides7 analog inputs,an internaljunctiontype temperaturesensor,two remote junction temperaturesensingchannels,a Delta-SigmaADC (Analog-to-DigitalConverter),a DAC output,2 fan speed counters,WATCHDOG registers,and a varietyof inputsand outputson a singlechip.A two wireSMBus ™ SerialBus interfaceisincluded.The LM87 performspower supply,temperature,fancontroland fanmonitoring forpersonalcomputers. The analoginputsare usefulformonitoringseveralpower suppliespresentina typicalcomputer.The LM87 includesinternalresistordividersthatscaleexternalVccp1, Vccp2, +2.5V,+5.0 V, +12 V and internal+3.3V power supplyvoltagesto a 3/4 scalenominalADC output.Two additionalinputs,+AIN1 and +AIN2 (2.5Vfull scale)areinputdirectlywithno resistivedividers.The LM87 ADC continuouslyconvertsthescaledinputsto8-bit digitalwords.Measurement ofnegativevoltages(suchas -5V and -12V power supplies)can be accommodated withan externalresistordividerappliedto the +AIN1 or +AIN2 inputs.Internaland externaltemperatureis convertedto8-bittwo's-complementdigitalwords witha 1 °C LSB. Fan inputsmeasure the periodof tachometerpulsesfrom the fans,providinga highercount forlowerfan speeds.The faninputsareSchmitt-Triggerdigitalinputswithan acceptablerangeof0 V toV+ and a transition levelofapproximatelyV+/2.Fullscalefancountsare 255 (8-bitcounter)and thisrepresentsa stoppedor very slow fan.Nominal speeds,based on a countof153,are programmable from 1100 to8800 RPM on FAN1 and FAN2. Schmitt-Triggerinputcircuitryisincludedtoaccommodate slowriseand falltimes.An 8 bitDAC with0 V to2.5V outputvoltagerangecan be used forcontroloffanspeed. The LM87 has severalinternalregisters,as shown inFigure5, Table 1 and REGISTERS AND RAM . These include:

• ConfigurationRegisters: Providecontroland configuration.
• Channel Mode Register: Controlsthefunctionalityofthedualpurposeinputpins,scalingforinternalVcc measurement,and operationofsome IRQ inputs.
• InterruptStatusRegisters: Two registerstoprovidestatusofeach WATCHDOG limitorInterruptevent. ReadingtheStatusRegistersclearsany activebits.
• InterruptStatusMirrorRegisters: Two registerstoprovidestatusofeach WATCHDOG limitorInterrupt event.ReadingtheMirrorRegistersdoes notaffectthestatusbits.
• InterruptMask Registers: Allowsmasking ofindividualInterruptsources,as wellas separatemasking for each ofthetwo hardwareInterruptoutputs.
• CI ClearRegister: Allowstransmittinga 20 ms (minimum)lowpulseon thechassisintrusionpin(CI).
• VID/Fan DivisorRegister: ThisregistercontainsthestateoftheVID0-VID3inputlinesand thedivisorbits forFAN1 and FAN2 inputs.
• VID4 Register: ContainsthestateoftheVID4 input.
• Extended Mode Register: Enableand controltheAlertResponse operation.
• Hardware High Limit Registers: Registersat 13h, 14h, 17h and 18h where Internaland External 'Hardware'WATCHDOG temperaturehighlimitsarestored.These limitshave Power On Defaultsettingsbut can be adjustedby theuser.The valuesstoredat13h and 14h can be lockeddown by settingbits1 and 2 of ConfigurationRegister2.
• Value and LimitRAM: The DAC digitaloutput,monitoringresults(temperature,voltages,fan counts), WATCHDOG limits,and Company/SteppingIDsareallcontainedintheValueRAM. The ValueRAM consists ofa totalof33 bytes,addresses19h -3Fh,containing: – byte1 ataddress19h containstheDAC Data Register – locations1Ah and 1Bh containtheWATCHDOG lowlimitsforAIN1 and AIN2 – locations1Ch -1Fh areunassignedand do nothave associatedregisters – thenext10 bytesataddresses20h -29hcontainalloftheresults – location2Ah isunassignedand does nothave an associatedregister – thenext18 bytesataddresses2Bh-3Ch aretheremainingWATCHDOG limits – the last2 bytes at addresses 3Eh and 3Fh containthe Company ID and SteppingID numbers, respectively

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 When theLM87 isstarted,itcyclesthrougheach measurement insequence,and itcontinuouslyloopsthrough the sequence approximatelyonce every 0.4 s. Each measured value is compared to values storedin WATCHDOG, or Hardware High Limitregisters.When the measured valueviolatesthe programmed limitthe LM87 willseta correspondingInterruptintheInterruptStatusRegisters.The hardwareInterruptlineINT# isfully programmable withseparatemasking of each Interruptsource.In addition,the ConfigurationRegisterhas a controlbitto enableor disablethe hardware Interrupt.Anotherhardware Interruptlineavailable,THERM# is used to signaltemperaturespecificevents.Having a dedicatedinterruptforthese conditionsallowsspecific actionstobe takenforthermalevents.Thisoutputisenabledby settingbit2 ofConfigurationRegister1. The ChassisIntrusioninputisdesignedtoacceptan activehighsignalfroman externalcircuitthatactivatesand latcheswhen thecase isremoved fromthecomputer. INTERFACE Figure5. LM87 RegisterStructure Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com InternalRegistersoftheLM87 Table1.The internalregistersand theircorrespondinginternalLM87 addresses areas follows: Register LM87 InternalHex Power on Notes Address Value InternalTemp. Hardware High 13h 0100 0110 70 °C Default-User adjustable.Lockableby settingbit1 Limit ofregister4Ah. ExternalTemp. Hardware High 14h 0101 0101 85 °C Default-User adjustable.Lockableby settingbit2 Limit ofregister4Ah. TestRegister 15h 0000 0000 ChannelMode Register 16h 0000 0000 InternalTemp. Hardware High 17h 0100 0110 70 °C Default-User adjustable. Limit ExternalTemp. Hardware High 18h 0101 0101 85 °C Default-User adjustable. Limit ValueRAM DAC Data Register 19h 1111 1111 DefaultstofullscaleDAC setting. ValueRAM 1Ah-3Fh (See ValueRAM — Address19h–3Fh)Contains:monitoring results(temperature,voltages,fancounts),WATCHDOG limits,and Company/SteppingIDs Company ID 3Eh 0000 0010 ThisdesignatestheTexas InstrumentsLM87. Revision 3Fh 0000 0110 Revisionsofthisdevicewillstartwith1 and incrementby one. ConfigurationRegister1 40h 0000 1000 InterruptStatusRegister1 41h 0000 0000 InterruptStatusRegister2 42h 0000 0000 InterruptMask Register1 43h 0000 0000 InterruptMask Register2 44h 0000 0000 CI ClearRegister 46h 0000 0000 VID0-3/FanDivisorRegister 47h 0101 XXXX The upperfourbitssetthedivisorforFan Counters1 and 2.The lowerfourbitsreflectthestateoftheVID0-VID3 inputs. VID4 Register 49h 1000 000X The lowerbitreflectsthestateofVID4 input. ConfigurationRegister2 4Ah 0000 0000 InterruptStatusRegister1 4Ch 0000 0000 Mirror InterruptStatusRegister2 4Dh 0000 0000 Mirror SMBALERT# Enable 80h 0010 0000

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 SerialBus Interface Figure6. (a)SerialBus WritetotheInternalAddress Registerfollowedby theData Byte Figure7. (b)SerialBus WritetotheInternalAddress RegisterOnly Figure8. (c)SerialBus Read from a RegisterwiththeInternalAddress RegisterPresettoDesired Location The SerialBus controllinesconsistoftheSMBData (serialdata),SMBCLK (serialclock)and ADD (address)pin. The LM87 can operateonlyas a slave.The SMBCLK lineonlycontrolsthe serialinterface,allotherclock functionswithinLM87 such as theADC and fancountersaredone witha separateasynchronousinternalclock. When usingtheSerialBus Interface,a writewillalwaysconsistoftheLM87 SerialBus InterfaceAddressbyte, followedby theInternalAddressRegisterbyte,thenthedatabyte.Therearetwo casesfora read: 1. IftheInternalAddressRegisterisknown toalreadybe atthedesiredAddress,simplyreadtheLM87 withthe SerialBus InterfaceAddressbyte,followedby thedatabytereadfromtheLM87. 2. IftheInternalAddressRegistervalueisunknown, orifitisnotthedesiredvalue,writetotheLM87 withthe SerialBus InterfaceAddress byte,followedby the InternalAddress Registerbyte.Then restartthe Serial Communicationwitha Read consistingoftheSerialBus InterfaceAddress byte,followedby thedatabyte readfromtheLM87. The SerialBus addressoftheLM87 issetto010 11(X)(Y).Allbits,exceptforX and Y, arefixedand cannotbe changed.The valuesforX and Y aresetby thestateoftheADD pinon power up.IfADD istiedtogroundthe valueforXY is10.IfADD istiedtoVcc XY willbe setto01.IfADD isnotconnected,XY willbe 00.XY = 11 is nota possiblecombination. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com AllofthesecommunicationsaredepictedintheSerialBus InterfaceTimingDiagrams as shown inFigure8.The example shown correspondstotheADD pintiedtoVcc,so XY=01 and theresultingLM87 addressis0101101. SerialBus Timeoutcan be initiatedby holdingtheSMBCLK linelow forgreaterthantTIMEOUT (35ms max).Serial Bus Timeoutresetstheserialbus interfacecircuitrytotheidlestateand readiestheLM87 fora new serialbus communication. USING THE LM87 Power On When power isfirstapplied,the LM87 performsa “power on reset” on severalof itsregisters.The power on conditionof the LM87's registersisshown inTable 1 Registerswhose power on valuesare not shown have power on conditionsthatare indeterminate(thisincludesthe value RAM ,exclusiveof the DAC data,and WATCHDOG limits).When power isfirstappliedtheADC isinactive.Inmost applications,thefirstactionafter power on istowriteWATCHDOG limitsintotheValueRAM. Resets Allregistervalues,excepttheProgrammed DAC Outputcan be returnedtotheir"power on" defaultvaluesby takingtheRESET# inputlow foratleastTBD ns orby performinga ConfigurationRegisterINITIALIZATION.The Value RAM conversionresults,and Value RAM WATCHDOG limitsare not Reset and willbe indeterminate immediatelyafterpower on.IftheValueRAM containsvalidconversionresultsand/orValueRAM WATCHDOG limitshave been previouslyset,theywillnotbe affectedby a ConfigurationRegisterINITIALIZATION.The Power On Reset,RESET# input,and ConfigurationRegisterINITIALIZATION,clearor initializethefollowingregisters (theinitializedvaluesare shown on Table I).Power On Reset alsosetsthe Programmed DAC Outputto full scale(FFh)Hardware High Limitregisters13h,and 14h willonlybe returnedtodefaultvaluesifthe"WriteOnce" bitsinConfigurationRegister2 have notbeen set:

• ConfigurationRegisters1 and 2
• ChannelMode Register
• Hardware HighLimitRegisters
• InterruptStatusRegister1
• InterruptStatusRegister2
• InterruptStatusMirrorRegister1
• InterruptStatusMirrorRegister2
• InterruptMask Register1
• InterruptMask Register2
• ChassisIntrusionClearRegister
• VID/FanDivisorRegister
• VID4 Register
• ExtendedMode Register ConfigurationRegisterINITIALIZATIONisaccomplishedby settingBit7 ofConfigurationRegister1 high.Thisbit automaticallyclearsafterbeingset. ConfigurationRegistersand Channel Mode Register The ConfigurationRegistersand Channel Mode RegistercontroltheLM87 operation.At power on,theADC is stoppedand INT_Clearisasserted,clearingtheINT# hardwireoutput.These registersstartand stoptheLM87, enable and disableinterruptoutput,configurethe operationof dual functioninputs,and providethe Reset functionsdescribedinResets. Bit0 of ConfigurationRegister1 controlsthe monitoringloopof the LM87. SettingBit0 low stopsthe LM87 monitoringloopand putstheLM87 inshutdown mode, reducingpower consumption.SerialBus communication can takeplacewithany registerintheLM87 althoughactivityon theSMBData and SMBCLK lineswillincrease shutdown current,up toas much as maximum ratedsupplycurrent,whiletheactivitytakesplace.TakingBit0 highstartsthemonitoringloop,describedinmore detailsubsequently. Bit1 ofConfigurationRegister1 enablestheINT# Interruptoutputwhen thisbitistakenhigh.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 Bit2 ofConfigurationRegister1 enablestheTHERM# Interruptoutputwhen thisbitistakenhigh. Bit3 of ConfigurationRegister1 clearsthe INT# outputwhen sethigh,withoutaffectingthe contentsof the InterruptStatusRegisters.The LM87 willstopmonitoring.Itwillresume upon clearingofthisbit. Bit4 ofConfigurationRegister1 providesan activelow 20 ms (minimum)pulseattheRESET# outputwhen set high. Bit6 ofConfigurationRegister1 clearstheTHERM# outputwhen sethigh,withoutaffectingthecontentsofthe InterruptStatusRegisters. Bit7 ofConfigurationRegister1 (theINITIALIZATIONbit)resetstheinternalregistersoftheLM87 as described inResets. Bit7 oftheCI_ClearRegisterprovidesan activelow20 ms (minimum)pulseattheCI# outputpinwhen sethigh. ThisisintendedforresettingtheChassisIntrusioncircuitry. Bit0 ofConfigurationRegister2 enablestheINT# InterruptoutputforTHERM# eventswhen setlow.When this bitissethigh,THERM# erroreventswillnotaffecttheINT# output. Bit1 ofConfigurationRegister2 locksthevaluesetintheInternalTemperaturehighlimitregisterat13h.The valuecannotbe changed untila Power On Resetisperformed. Bit2 ofConfigurationRegister2 locksthevaluesetintheExternalTemperaturehighlimitregisterat14h.The valuecannotbe changed untila Power On Resetisperformed. Bit3 ofConfigurationRegister2 setstheTHERM# outputmode. When setto0,theTHERM# outputfunctionsin defaultmode, when setto1,THERM# operatesinACPI mode. Bit6 ofConfigurationRegister2,when setto1,enablespin21 as an activehigh(IRQ3)interruptinput.When setto0,thisinputisdisabledas an IRQ interrupt. Bit7 ofConfigurationRegister2,when setto1,enablespin20 as an activehigh(IRQ4)interruptinput.When setto0,thisinputisdisabledas an IRQ interrupt. Bit0 oftheChannel Mode Register,when setto1,configurespin5 as AIN1.When setto0,pin5 isconfigured as theFAN1 input. Bit1 oftheChannel Mode Register,when setto1,configurespin6 as AIN2.When setto0,pin6 isconfigured as theFAN2 input. Bit2 oftheChannelMode Register,when setto0,configurespins18 and 19 as +2.5V and VCCP2 voltageinputs. When setto1,pins18 and 19 areconfiguredas a second remotetemperaturesensingchannel. Bit3 oftheChannel Mode Register,when setto0,setsthenominalvoltageforinternalVCC measurement to 3.3V.When setto1,thenominalVCC rangeis5V. Bit4 oftheChannel Mode Register,when setto1,enablespin24 as an activelow (IRQ0)interruptinput.When setto0,thisinputisdisabledas an IRQ interrupt. Bit5 oftheChannel Mode Register,when setto1,enablespin23 as an activelow (IRQ1)interruptinput.When setto0,thisinputisdisabledas an IRQ interrupt. Bit6 oftheChannel Mode Register,when setto1,enablespin22 as an activelow (IRQ2)interruptinput.When setto0,thisinputisdisabledas an IRQ interrupt. Bit7 oftheChannel Mode Register,when setto1,configurespins20 to24 as interruptinputs.When setto0, pins20 to24 areconfiguredas processorvoltageID pins. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com StartingConversions The monitoringfunction(Analoginputs,temperature,and fan speeds) in the LM87 is startedby writingto ConfigurationRegister1 and settingINT_Clear(Bit3) low,and Start(bit0) high.The LM87 then performsa “round-robin”monitoringofallanaloginputs,temperature,and fanspeed inputsapproximatelyonce every0.3s. The sequence ofitemsbeingmonitoredis: 1. Check D1 connections 2. Check D2 connections 3. InternalTemperature 4. ExternalD1 Temperature 5. ExternalD2 Temperature 6. +2.5V 7. +Vccp1 8. Vcc 3.3V 9. Vcc 5.0V 10. +5Vin 11. +12Vin 12. +Vccp2 13. AIN1 14. AIN2 15. Fan 1 16. Fan 2 DACOut immediatelychanges aftertheDAC Data RegisterintheValue RAM has been updated.For a zeroto fullscaletransitionDACOut willtypicallysettlewithin100 μsec ofthestopby masterinthewritetotheDAC Data RegisterSerialBus transaction.The DAC Data Registerisnot resetby the INITIALIZATIONbitfound inthe ConfigurationRegister. Reading Conversion Results The conversionresultsareavailableintheValueRAM. Conversionscan be readatany timeand willprovidethe resultofthelastconversion.Because theADC stops,and startsa new conversionwhenever itisread,readsof any singlevalueshouldnotbe done more oftenthanonce every56 ms. When readingallvalues,allowatleast 0.6seconds between readinggroupsofvalues.Reading more frequentlythanonce every0.6seconds can also preventcompleteupdatesofInterruptStatusRegistersand InterruptOutput's. A typicalsequence ofeventsupon power on oftheLM87 wouldconsistof: 1. SetWATCHDOG Limits 2. SetInterruptMasks 3. StarttheLM87 monitoringprocess

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 ANALOG INPUTS Allanalog inputvoltagesare digitizedto 8-bitsof resolution.For safetypurposes,and to providemaximum accuracy,a 510 Ω resistorshouldbe placedinserieswithallanalogvoltageinputs.The resistorswilllimitthe possiblecurrentdrawn fromthepower suppliesintheeventthatcircuitboardtracesarebridged,oraccidentally shortedduringtest.Allanalog inputs,except forAIN1 and AIN2, includeinternalresistorattenuators.The theoreticalLSB size,theoreticalvoltageinputrequiredforan ADC readingof192 (3/4scale)and 255 (fullscale) foreach analoginputisdetailedinthetablebelow: Input LSB size Vin for192 Vin for255 2.5Vin 13 mV 2.5V 3.320V 3.3Vcc 17.2mV 3.3V 4.383V 5Vin/Vcc 26 mV 5 V 6.641V 12Vin 62.5mV 12 V 15.93V Vccp1,Vccp2 14.1mV 2.7V 3.586V AIN1/AIN2 9.8mV 1.875V 2.49V Thus monitoringpower supplieswithina system can be easilyaccomplishedby tyingtheVccp,+2.5Vin,+5Vin and +12Vin analoginputstothecorrespondingsystem supply.Vcc oftheLM87 willalsobe monitored.A digital readingcan be convertedtoa voltageby simplymultiplyingthedecimalvalueofthereadingby theLSB size. For inputswith attenuatorsthe inputimpedance is greaterthan 90 kΩ. AIN inputsdo not have resistor attenuatorsand aredirectlytiedtotheADC, thereforehavinga much largerinputimpedance. A negativepower supplyvoltagecan be appliedtoa AIN inputthrougha resistordividerreferencedtoa known positiveDC voltageas shown inFigure9.The resistorvaluesshown inthetablebelow forthecircuitofFigure9 willprovideapproximately1.25V attheAIN analoginputsoftheLM87 fora nominalreadingof128. Table2. VoltageMeasurements R2 R1 V + Voltage (VS) at Analog Inputs (ADC code 128) −12V 20 kΩ 130 kΩ +3.3V +1.25V −5V 20 kΩ 61.0kΩ +3.3V +1.25V Resistorvaluesshown inTable2 provideapproximately1.25VattheVccp inputs. Figure9. InputExamples The resistorswere selectedby settingR2 = 20 kΩ and thencalculatingR1 usingthefollowingequation,(VS is themaximum negativeinputvoltage,V+ isthepositivepullupvoltage): The maximum R1 can be isrestrictedby theDC inputcurrentofan AIN input. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com Inputswithinternalresistordividers(+2.5Vin,+3.3Vinor +5Vin,+12Vin)can have voltageappliedthatexceeds inputshave a parasiticdiodetothepositivesupply,so careshouldbe takennottoforwardbiasthisdiode.All analog inputshave internaldiodesthatclamp the inputvoltagewhen going below ground thus limitingthe negativeanaloginputvoltagerangeto−50 mV. Violatingtheanaloginputvoltagerangeofany analoginputhas no detrimentaleffecton theotheranaloginputs.Externalresistorsshouldbe includedtolimitinputcurrentsto the valuesgiveninAbsoluteMaximum RatingsforInputCurrentAt Any Pin whenever exceedingthe analog inputvoltagerange,even on an un-powered LM87. Inputswithexternalattenuatornetworkswillusuallymeet theserequirements.Ifitispossibleforinputswithoutattenuators(suchas AIN1 and AIN2)tobe turnedon while LM87 ispowered off,additionalresistorsofabout10 kΩ shouldbe added inserieswiththeinputstolimitthe inputcurrent. Analog InputInterrupts A WATCHDOG window comparisonon the analoginputscan activatethe INT# interruptoutput.A converted inputvoltagethatisabove itsrespectiveHIGH limitorlessthanorequaltoitsLOW limitwillcause a flagtobe setinitsInterruptStatusRegister.ThisflagwillactivatetheINT# outputwhen itsmask bitissetlow.Mask bits are found in the InterruptMask Registers.The Interruptsystem is describedin much greaterdetailin WATCHDOG LIMITCOMPARISONS AND INTERRUPT STRUCTURE . LAYOUT AND GROUNDING A separate,low-impedanceground planeforanalogground,which providesa ground pointforthe GND pin, voltagedividersand otheranalog components,willprovidebest performance,but isnot mandatory.Analog components such as voltagedividersshouldbe locatedphysicallyas closeas possibletotheLM87. The power supplybypass,the parallelcombinationof 10 μF (electrolyticor tantalum)and 0.1 μF (ceramic) bypass capacitorsconnectedbetween pin9 and ground,shouldalsobe locatedas closeas possibleto the LM87. FAN INPUTS The FAN1 and FAN2 inputsacceptsignalsfrom fansequippedwithtachometeroutputs.These are logic-level inputswithan approximatethresholdofV+/2.SignalconditioningintheLM87 accommodates theslow riseand falltimestypicaloffantachometeroutputs.The maximum inputsignalrangeis0 toV+.Intheeventtheseinputs aresuppliedfromfanoutputswhichexceed 0 toV+,eitherresistivedivisionordiodeclampingmust be included to keep inputswithinan acceptablerange,as shown inFigure10. R2 isselectedso thatitdoes not develop excessivevoltagedue toinputleakage.R1 isselectedbased on R2 toprovidea minimum inputof2 V and a maximum ofV+.R1 shouldbe as low as possibletoprovidethemaximum possibleinputup toV+ forbestnoise immunity.Alternatively,use a shuntreferenceorzenerdiodetoclamp theinputlevel. Iffanscan be powered whilethepower totheLM87 isoff,theLM87 inputswillprovidediodeclamping.Limit inputcurrenttotheInputCurrentatAny Pin specificationshown inAbsoluteMaximum Ratings.Inmost cases, open collectoroutputswithpull-upresistorsinherentlylimitthiscurrent.Ifthismaximum currentcould be exceeded,eithera largerpullup resistorshouldbe used orresistorsconnectedinserieswiththefaninputs. The Fan Inputsgate an internal22.5 kHz oscillatorforone periodof the Fan signalintoan 8-bitcounter (maximum count= 255).The defaultdivisor,locatedintheVID/FanDivisorRegister,issetto2 (choicesare1,2, 4,and 8)providinga nominalcountof153 fora 4400 rpm fanwithtwo pulsesperrevolution.Typicalpracticeis toconsider70% ofnormalRPM a fanfailure,atwhichpointthecountwillbe 219. Determinethefancountaccordingto: (2)

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 Note thatFan 1 and Fan 2 DivisorsareprogrammableviatheVID/FanDivisorRegister. Fan tachometeroutputsthatprovideone pulseper revolutionshoulduse a divisorsettingtwicethatofoutputs thatprovidetwo pulsesper revolution.For example,a 4400 RPM fan thatprovidesone pulseper revolution shouldhave thedivisorsetto4 such thatthenominalcounteroutputis153. (b)Fan withTach Pull-Upto+12V, or Totem-Pole Output (a)Fan withTach Pull-Upto+5V and ResistorAttenuator (d)Fan withStrong Tach Pull-Upor Totem Pole Output (c)Fan withTach Pull-Upto+12V and Diode Clamp and Diode Clamp Figure10. AlternativesforFan Inputs Countsarebased on 2 pulsesperrevolutiontachometeroutputs. RPM Time per Revolution Counts for“Divideby 2” Comments (Default)inDecimal 4400 13.64ms 153 counts TypicalRPM 3080 19.48ms 219 counts 70% RPM 2640 22.73ms 255 counts 60% RPM (maximum counts) Mode Select Nominal RPM Time per Revolution Counts forthe 70% RPM Time per Revolution Given Speed inDecimal for70% RPM Divideby 1 8800 6.82ms 153 6160 9.74ms Divideby 2 4400 13.64ms 153 3080 19.48ms Divideby 4 2200 27.27ms 153 1540 38.96ms Divideby 8 1100 54.54ms 153 770 77.92ms (3) DAC OUTPUT The LM87 providesan 8-bitDAC (Digital-to-AnalogConverter)withan outputrange of0 to2.5volts(9.80mV LSB). ThisDAC can be used inany way, but inmost applicationsof the LM87 the DAC willbe used forfan control.TypicallytheDAC outputwould be amplifiedtoprovidetheup to12 voltdriverequiredby thefan.At power-ontheDAC providesfulloutput,insuringthatfullfanspeed isthedefaultcondition.Care shouldbe taken such thattheanalogcircuitrytiedtothispindoes notdrivethispinabove 2.5V. Doing so willplacetheLM87 in NAND treetestmode whichwillmake allpinsinputs.AfterthefirstSMBus communicationwiththeLM87, itwill leaveNAND treetestmode and allinputs/outputswillfunctionnormally. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com Fans do notstartreliablyatreducedvoltages,so operationata reducedvoltageshouldbe precededby a brief (typically1 second)excursiontofulloperatingvoltage,thenreducethevoltage.Most fansdo notoperateatall below5 to7 volts.Atthoselowervoltagesthefanwillsimplyconsume current,dissipatepower,and notoperate, and such conditionsshouldbe avoided. The outputof the amplifiercan be configuredto providea highor low sidepass transistor.A highsidepass transistorsimplifiesthe couplingof tachometeroutputsto the tachometerinputsof the LM87 sincethe fan remainsgrounded.Low sidedrivewillrequireAC couplingalongwithclampingat the LM87 inputto prevent negativeexcursions. A typicalcircuitforfandriveisshown inFigure16. TEMPERATURE MEASUREMENT SYSTEM The LM87 temperaturesensor(s)and ADC produce8-bittwo's-complementtemperaturedata.One internaldiode junctiontemperature,and up to two externaljunctiontemperaturescan be monitored.A digitalcomparator compares the temperaturedata to the user-programmableHigh, Low, and Hardware Limitsetpoints,and Hysteresisvalues. (Non-LinearScaleforClarity) Figure11. 8-bitTemperature-to-DigitalTransferFunction Temperature Data Format Temperaturedatacan be readfromtheTemperature,THIGH setpoint,TLOW setpoint,and Hardware Temperature limitregisters;and writtentotheTHIGH setpoint,TLOW setpoint,and Hardware Temperaturelimitregisters.THIGH setpoint,TLOW setpoint,Hardware TemperatureLimit,and Temperaturedata isrepresentedby an 8-bit,two's complement word withan LSB (LeastSignificantBit)equalto1°C: Temperature DigitalOutput Binary Hex +125°C 0111 1101 7Dh +25°C 0001 1001 19h +1.0°C 0000 0001 01h +0°C 0000 0000 00h −1.0°C 1111 1111 FFh −25°C 1110 0111 E7h −40°C 1101 1000 D8h

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 InternalTemperature Measurement The LM87 internaltemperatureismonitoredusinga junctiontypetemperaturesensor. Remote Temperature Measurement The LM87 monitorsthetemperatureofremotesemiconductordevicesusingthep-njunctiontemperaturesensing principal.Up to two remote IC, diode or bipolartransistortemperaturescan be monitored.The remote measurement channelshave been optimizedtomeasure theremotediodeofa PentiumIIprocessor.A discrete diodeor bipolartransistorcan alsobe used to sense the temperatureof externalobjectsor ambientair.The 2N3904 NPN transistorbase emitterjunctionperformswellinthistypeofapplication.When usinga 2N3904, the collectorshouldbe connectedtothebase toprovidea devicethatcloselyapproximatesthecharacteristicsofthe PentiumIIPNP monitoringdiode. When usingtwo external2N3904 sensors,theD − inputsshouldbe connectedtogether.Thisprovidesthebest possibleaccuracyby compensatingfordifferencesbetween the2N3904 and PentiumIIsensors. Duringeach conversioncycle,theremotemonitoringinputsperforman externaldiodefaultdetectionsequence. IftheD+ inputisshortedtoVCC or floatingthenthetemperaturereadingwillbe +127°C, and bit6 or bit7 of InterruptStatusRegister2 willbe set.IfD+ isshortedtoGND orD −,thetemperaturereadingwillbe 0°C and bit 6 or7 ofInterruptStatusRegister2 willnotbe set. Accuracy EffectsofDiode Non-IdealityFactor The techniqueused intoday'sremote temperaturesensorsisto measure the change inVBE at two different operatingpointsofa diode.Fora biascurrentratioofN:1,thisdifferenceisgivenas: where

• η isthenon-idealityfactoroftheprocessthediodeismanufacturedon,
• q istheelectroncharge,
• k istheBoltzmann'sconstant,
• N isthecurrentratio,
• T istheabsolutetemperaturein°K. (4) The temperaturesensorthen measures ΔVBE and convertsto digitaldata.In thisequation,k and q are well defineduniversalconstants,and N is a parameter controlledby the temperaturesensor.The only other parameterisη,whichdepends on thediodethatisused formeasurement.SinceΔVBE isproportionaltobothη and T,thevariationsinη cannotbe distinguishedfromvariationsintemperature.Sincethenon-idealityfactoris notcontrolledby thetemperaturesensor,itwilldirectlyadd totheinaccuracyofthesensor.For thePentium II Intelspecifiesa ±1% variationinη from partto part.As an example,assume a temperaturesensorhas an accuracyspecificationof±3°C atroom temperatureof25°C and theprocessused tomanufacturethediodehas a non-idealityvariationof±1%. The resultingaccuracyofthetemperaturesensoratroom temperaturewillbe: The additionalinaccuracyinthetemperaturemeasurement caused by η,can be eliminatedifeach temperature sensoriscalibratedwiththeremotediodethatitwillbe pairedwith. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com PCB Layout Recommendations forMinimizingNoise Ina noisyenvironment,such as a processormotherboard,layoutconsiderationsareverycritical.Noiseinduced on tracesrunningbetween the remote temperaturediode sensor and the LM87 can cause temperature conversionerrors.The followingguidelinesshouldbe followed: 1. Placea 0.1μF power supplybypass capacitoras closeas possibletotheVCC pinand therecommended 2.2 nF capacitoras closeas possibletotheD+ and D − pins.Make surethetracestothe2.2nF capacitorare matched. 2. Ideally,the LM87 shouldbe placedwithin10 cm of the Processordiode pinswiththe tracesbeing as straight,shortand identicalas possible. 3. Diode tracesshouldbe surroundedby a GND guard ringtoeitherside,above and below ifpossible.This GND guard shouldnotbe between theD+ and D − lines.Intheeventthatnoisedoes coupletothediode linesitwouldbe idealifitiscoupledcommon mode. ThatisequallytotheD+ and D − lines. 4. Avoidroutingdiodetracesincloseproximitytopower supplyswitchingorfilteringinductors. 5. Avoidrunningdiodetracesclosetoor paralleltohighspeed digitaland bus lines.Diode tracesshouldbe keptatleast2 cm. apartfromthehighspeed digitaltraces. 6. Ifitisnecessarytocrosshighspeed digitaltraces,thediodetracesand thehighspeed digitaltracesshould crossata 90 degreeangle. 7. The idealplacetoconnecttheLM87's GND pinisas closeas possibletotheProcessorsGND associated withthesense diode.ForthePentiumIIthiswouldbe pinA14. Figure12. Recommended Diode Trace Layout Noise on thedigitallines,overshootgreaterthanVCC and undershootlessthanGND, may preventsuccessful SMBus communicationwith the LM87. SMBus no acknowledge is the most common symptom, causing unnecessarytrafficon thebus.Although,theSMBus maximum frequencyofcommunicationisratherlow (400 kHz max) carestillneeds tobe takentoensureproperterminationwithina system withmultiplepartson thebus and longprintedcircuitboardtraces.A lowpassfilter,inserieswiththeSMBCLK and SMBData, has been added internallytotheLM87 fornoiseimmunity.The lowpassfilterhas a typicalcutofffrequencyof20MHz. Additional noiseimmunitycan be achievedby placinga resistor(4.7kto5.1kOhms) inserieswiththeSMBCLK inputas closeto the LM87 as possible.This resistance,in conjunctionwiththe IC inputcapacitance,reduces high frequencynoiseseen attheSMBCLK inputand increasesthereliabilityofcommunications.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 WATCHDOG LIMITCOMPARISONS AND INTERRUPT STRUCTURE Figure13. InterruptStructure Figure13 depictstheInterruptStructureoftheLM87. The LM87 can generateInterruptsas a resultofeach ofits internalWATCHDOG registerson theanalog,temperature,and faninputs. ExternalInterruptscan come from thefollowingsources.Whilethelabelsuggestsa specifictypeor sourceof Interrupt,thislabelisnota restrictionofitsusage,and itcouldcome fromany desiredsource:

• Chassis Intrusion:This isan activehigh interruptfrom any type of devicethatdetectsand captures chassisintrusionviolations.Thiscouldbe accomplishedmechanically,optically,or electrically,and circuitry externaltotheLM87 isexpectedtolatchtheevent.The designoftheLM87 allowsthisinputtogo higheven withno power appliedtotheLM87, and no clampingor otherinterferencewiththelinewilloccur.Thisline can alsobe pulledlow foratleast20 ms by theLM87 toreseta typicalChassisIntrusioncircuit.Thisresetis activatedby settingBit7 ofCI ClearRegister(46h)high.The bitintheRegisterisself-clearing.
• THERM# Input: Thisisan activelow interruptthatwould typicallybe generatedby an externaltemperature monitoringsystem.Ifthe THERM# outputiscurrentlyinactiveand thisinputispulledlow by an external circuit,the THERM# InterruptStatusbitwillbe set.In addition,the DAC outputwillbe forcedto fullscale operationwhileTHERM# ispulledlow by the externalsource.This allowsa separatethermalsensor to overridethe currentfan speed settinginan overtemperaturesituationnot sensed by the LM87. The DAC settingwillreturntonormalwhen theTHERM# inputisdeactivatedand theDAC settingregisterisunaffected by theTHERM# inputcondition.
• IRQ0-2: These areactivelow inputsfromany typeofexternalinterruptsource.IfenabledviatheChannel Mode Register(16h)theINT# outputwillbe activatedwhenever theseinputsarepulledlow.Sincethereare no dedicatedISR bitsthatcorrespondtotheIRQ inputs,theVID statusbitscan be readtodeterminewhich Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com IRQ inputisactive.Similarly,to mask offtheseinputsas interruptsources,theymust be disabledviathe ChannelMode Register(16h).

• IRQ3-4: These areactivehighinputsfromany typeofexternalinterruptsource.IfenabledviatheChannel Mode Register(16h)and ConfigurationRegister2 (4Ah),theINT# outputwillbe activatedwhenever these inputsare drivenhigh.Since thereare no dedicatedISR bitsthatcorrespondto the IRQ inputs,the VID statusbitscan be readtodeterminewhichIRQ inputisactive.Similarly,tomask offtheseinputsas interrupt sources,theymust be disabledviaConfigurationRegister2 (4Ah). With theexceptionoftheIRQ inputsand Hardware Temperatureerrors,allinterruptsare indicatedinthetwo InterruptStatusRegisters.The INT# outputhas two mask registers,and individualmasks foreach Interrupt.As describedin ConfigurationRegistersand Channel Mode Register, the hardware Interruptlinecan also be enabled/disabledintheConfigurationRegister. The THERM# interruptoutputisdedicatedtotemperatureand thereforeisonlyrelatedtointernaland external temperaturereadings,and theLow, Highand Hardware temperaturelimits. INT# Interrupts The INT# system combines severalgroupsoferrorsignalstogetherintoa common output.These groupsare; IRQ inputs,Voltageand Fan inputs,TemperatureValues,and theTHERM# input.Each one ofthesegroupsor channelsfunctionsa littledifferently. The IRQ inputsprovidetheleastcomplicatedINT# operation.The IRQ inputblockisenabledby settingbit7of theChannel Mode Register(16h)to0.Then theindividualinputsareenabledby settingthecorrespondingIRQ Enable bitsto1.Ifan IRQ inputisenabled,and subsequentlyan inputsignalisassertedon thatchannel,the INT# outputwillbe asserted.Duringtheinterruptserviceroutine,theINT# outputcan be deassertedina number ofways.The INT#_Clearbitcan be setduringtheISR topreventfurtherinterruptsfromoccurring.Then theIRQ enablebitfortheparticularinputcan be clearedtopreventthatchannelfrom causingfurtherinterrupts.At this pointtheINT#_Clearbitcan be clearedand no furtherinterruptswould be issuedfromthisparticularIRQ input. Once thesignalcausingtheIRQ has been removed,theenablebitforthatIRQ channelcouldbe setagain. Voltage,Fan,and TemperatureHigh/Lowerrorsareslightlymore complexintheirgenerationofINT# outputs.All of these errorbitsare storedin the InterruptStatusRegistersat 43h, 44h and the InterruptStatusMirror Registersat4Ch and 4Dh. These inputsaregatedby theInterruptMask Registersand processedby theINT# statemachine togeneratetheINT# output. Voltageand Fan errorconditionsare processed as follows.Every time a round robinconversioncycleis completed,thehigh/lowlimitcomparisonsforvoltageand fanquantitiesareupdated.Ifa quantityisoutsidethe limits,theappropriateInterruptStatusRegisterbitwillbe set.IfthecorrespondingInterruptMask Registerbitis 0,thentheStatusBitwillcause theINT# outputtobe asserted.Reading theInterruptStatusregisterwillclear theStatusBitand cause theINT# outputtobe deasserted.Iftheparameterisstilloutsidethelimitson thenext conversion,thestatusbitwillagainbe setand itwillagaincause an interrupt.If,on a subsequentconversion cycle,the parameterreturnswithinthe High/Low limitsbeforethe InterruptStatusRegistersare read,the InterruptStatusbitwillremainsetand theINT# outputwillremainasserted. TemperatureHigh/Lowerrorsaresomewhat more complicated.The internaltemperaturevalueiscompared with the InternalTemperatureHigh and Low LimitsinRegisters39h and 3Ah (and withthe InternalTemperature Hardware High Limitin Registers13h and 17h, see the next paragraphfordetails).We willbegin withthe temperaturevalue initiallywithinthe High/Low limitsand the correspondingInterruptMask Bit= 0. Ifthe temperaturevaluerisesabove thehighlimit,or below thelow limit,thecorrespondingInterruptStatusRegister bitwillbe set.Thiswillthencause an INT# tobe asserted.Reading theInterruptStatusRegisterwillclearthe statusbitand cause INT# to be deasserted.Ifthe temperaturevalue remains above the high limitduring subsequentconversioncycles,theInterruptStatusBitwillagainbe set,butno new INT# willbe generatedfrom thissource.INT# may be reassertedif:
• The temperaturethentransitionsup ordown throughtheoppositelimittothatoriginallyexceeded.
• The originallimitcrossed is programmed to a new value and on a subsequent conversioncycle,the convertedtemperatureisoutsidethenew limit.Thiswould cause thecorrespondingInterruptStatusBittobe set,causinga new INT# event.
• An interruptisgeneratedby any othersource,includingany othertemperatureerroror the THERM# pin beingpulledlowby an externalsignal.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 The thirdgroup of signalsthatwillgenerateINT# outputsare Hardware Temperature errors,caused by temperaturesexceedingthehardwarelimitsstoredat13h,14h,17h,and 18h.Theinternaltemperaturevalueis compared with the InternalTemperature Hardware High Limitsin Registers13h and 17h. The external temperaturevaluesare compared withthe ExternalTemperatureHardware High LimitsinRegisters14h and 18h.The limitsinRegister14h and 18h applyequallytothevaluesofbothD1 and D2. Both temperaturevalues areindividuallycompared withbothlimitvalues. The onlydifferencebetween thedifferentHardware Limitregistersisthatby writinga 1 intoBit1 ofregister4Ah, thecontentsofregister13h willbe lockedand cannotbe reprogrammed.Similarly,thecontentsofregister14h willbe lockedby writinga 1 intoBit2 of register4Ah. The registerscan onlybe reprogrammed ifBit7 of ConfigurationRegister1 (40h)iswrittentore-Initializethechip,orpower isremoved and reapplied.Thisfeature isprovidedtopreventsoftwarefromunintentionallyoverwritingtheseimportantlimits. Again,we willassume thatthe temperatureinitiallyis below the Hardware Temperature setpoints.Ifthe temperatureon a subsequentconversionisabove any ofthevaluesstoredintheHardware TemperatureLimit registers,theINT# outputwillbe asserted.Errorscaused by exceedingtheselimitscannotbe clearedby reading theInterruptStatusRegisters,and theINT# conditioncan onlybe clearedby clearingtheThermalINT# Enable bit,by settingtheINT#_Clearbitorby disablingINT# by clearingtheINT#_Enablebit. The finalINT# sourcetoconsideristheTHERM# input/output.THERM# can be pulledlow by an externalsource to generatean INT# output.PullingTHERM# low withexternalcircuitrysets the correspondingTHERM# InterruptStatusBit.Ifthisbitisnot masked, itwillcause INT# to be asserted.Reading the InterruptStatus Registerswillclearthestatusbitand willcause INT# tobe deasserted.Iftheexternalsignalcontinuestopull THERM# low,theInterruptStatusBitwillbe resetatthecompletionofthenextconversioncycle.Thiswillagain asserttheINT# output.Note thatiftheexternalcircuitrypullsTHERM# low,butthispinisalreadylow due tothe THERM# outputbeingactive,thisexternalsignalcannotbe sensed,and theTHERM# InterruptStatusBitwillnot be set. InterruptStatus Registers:Reading a StatusRegisterwillreturnthe contentsof the Register,and resetthe Register.A subsequentread done beforethe analog“round-robin” monitoringloopiscompletewillindicatea clearedRegister.Allowat least600 ms to allowallRegistersto be updated between reads.In summary, the InterruptStatusRegisterclearsupon beingread,and requiresatleast300 ms tobe updated.When theInterrupt StatusRegisterclears,thehardwareinterruptlinewillalsoclearuntiltheRegistersareupdatedby themonitoring loop. InterruptStatusMirrorRegisters:The InterruptStatusMirrorRegistersprovidethesame informationthatthe InterruptStatusRegistersdo.ReadingtheStatusMirrorRegisters,however,does not resetthestatusbits. InterruptMask Registers:Allsourceswhicharecombined toformtheINT# outputcan be individuallymasked viathetwo InterruptMask Registersat43h,and 44h.The bitsinthemask registerscorresponddirectlytothe bitsin the InterruptStatusRegisters.Settingan InterruptMask bitinhibitsthatInterruptStatusBitfrom generatingan INT# interrupt.Clearinga mask bitallowsthe correspondingstatusbit,ifset,to generateINT# outputs.InterruptStatusBitswillbe setand clearedregardlessofthestateofcorrespondingInterruptMask Bits, themask bitsmerelyalloworpreventthestatusbitsfromcontributingtothegenerationofINT# outputs. Enablingand ClearingINT#:The hardwareInterruptline(INT#)isenabledby settingtheINT#_EnablebitatBit 1 of ConfigurationRegister1. The INT# outputcan be clearedby settingthe INT#_Clearbitwhich isBit3 of ConfigurationRegister1.When thisbitishigh,theLM87 monitoringloopwillstop.Itwillresume when thebitis low. Thermal InterruptMask: Insome applications,theusermay want topreventallthermalerrorconditionsfrom causingINT# interrupts.The Thermal INT# Mask bit(Bit0 of ConfigurationRegister2) isprovidedforthis purpose.The THERM# outputdiscussedlaterisnotaffectedby thestatusoftheThermalINT# Mask bitand will functionnormallyinresponsetotemperatureerrorconditions.IftheThermal INT# Mask bitisset,theinterrupt statusfor internaland externaltemperature,the THERM# input,and the hardware temperatureerror comparisons,willcontinuetobe updatedeveryconversioncycle,butwillnothave any effecton theINT# output. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com SMBALERT# The INT# I/Opincan alternativelybe configuredas an SMBALERT# outputinconjunctionwiththeSMBALERT# protocol.Inthismode ofoperation,ratherthanconnectingtheINT# /ALERT# pintothesysteminterruptinputs,it willbe connectedtotheSMBALERT# inputpinon theSMBus host.When an INT#/ALERT# typeerrorcondition isdetected,thispinwillnotifytheSMBus hostthatan SMBus devicehas an SMBALERT# condition.The SMBus hostwillthen access the bus usingthe AlertResponse Address (ARA) which is0001100b. Only the device assertingtheSMBALERT# signalwillrespondtotheARA, thusprovidingautomaticidentificationofthedevice generatingtheSMBALERT#. Afteracknowledgingtheslaveaddress,theLM87 willdisengageitsSMBALERT# outputsignal.For more informationon theSMBALERT# protocol,pleaserefertotheSystem Management Bus specification.SMBALERT# isenabledby settingBit6 oftheAlertResponse Enableregisterat80h. THERM# Interrupts The THERM# I/Opinisdedicatedtotemperaturerelatederrorconditions.Itincludesa builtinpull-upresistorto minimizeexternalcomponents.The THERM# Enablebit,Bit2 ofConfigurationRegister1 isused toenablethe THERM# output.The THERM# Clearbit,Bit6 ofConfigurationRegister1,when setto1,clearstheTHERM# output.TheTHERM# outputoperatesintwo differentmodes when processingthermalerrorconditions,Default Mode and ACPI Mode ,selectedby thestateoftheTHERM# InterruptMode bitatBit3 ofConfigurationRegister 2 (0= Default,1 = ACPI). DefaultMode: The THERM# ouputoperatesusinga simplecomparisonoftemperaturewiththecorresponding limitvalues.Ifany temperaturevalueisoutsidea correspondinglimitinregisters37h,39h,2Bh, 38h,3Ah, or 2Ch, theTHERM# outputwillgo low.The outputwillremainasserteduntilitisresetby:readingInterruptStatus Register1,by settingtheTHERM#CLR bit,or ifthetemperaturefallsbelow thelow limitforthatsensor.When THERM# isclearedby readingthestatusregister,itmay be setagainafterthenexttemperaturereading,ifthe temperatureisstillabove the highlimit.When THERM# isclearedby settingTHERM#CLR, itcannotbe re- asserteduntilthisbitiscleared.IfTHERM# isactivatedbecause a temperaturevalueexceeds one of the hardwarelimitsinregisters13h,14h,17h,or 18h,or exceeds 126 degreesC, AOUT willbe forcedtothefull scalevalue.In thiscase,the THERM# outputcan onlybe clearedby settingthe THERM#CLR bitor ifthe temperaturereturnsto5 degreesbelow thehardwarelimit.Regardlessofhow THERM# iscleared,AOUT willbe maintainedatthefullscalevalueuntilthetemperaturereturnsto5 degreesbelow thehardwarelimitthatwas exceeded. ACPI Mode: In ACPI mode, THERM# isonlyactivatedwhen temperaturesexceed the highlimitsettingsin registers13h,14h,17h,18h orthesafetylimitof126 degreesC. Itwillbe de-assertedifthetemperaturereturns at least5 degrees below the limit.While THERM# isasserted,AOUT willbe drivento fullscaleto provide maximum coolingfroma variablespeed fan. THERM# alsofunctionsas an input.When an externalactivelow signalisappliedto THERM#, itwillsetthe THERM# inputInterruptStatusBitand willcause AOUT to go to fullscale,regardlessof the stateof the THERM# InputInterruptMask bit.IftheMask bitisclearedand INT# isenabled,an INT# willbe generated.The THERM# inputfunctionisnotaffectedby theTHERM# operatingmode. FaultQueue A FaultQueue isincorporatedintheexternaltemperaturemonitoringsectionsoftheLM87. Thisservesas a filter tominimizefalsetriggeringcaused by shortdurationor transienttemperatureevents.The FaultQueue adds a counterbetween thecomparisonlogicand theInterruptStatusRegisterand THERM# outputcircuitry.The Fault Queue has a depth of 3, so threeconsecutivereadingsoutsideof limitsis requiredto set an external temperatureInterruptStatusBitor generatea THERM# output.When the monitoredtemperatureisreturning withinlimits,onlyone conversionwithinlimitsisrequiredtoclearthestatusbit.Inotherwords,thefaultqueue is onlyactivewhen travellingoutsideofthelimits,notwhen returningback withinlimits.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 Figure14. LM87 InterruptStructure RESET# I/O RESET# isintendedtoprovidea masterresettodevicesconnectedtothisline.SettingBit4 inConfiguration Register1 highoutputsa 20 ms (minimum)low pulseon thisline,attheend ofwhichBit4 intheConfiguration Registerautomaticallyclears.Again,the labelforthispinisonlyitssuggesteduse.In applicationswhere the RESET# capabilityisnotneeded itcan be used forany typeofdigitalcontrolthatrequiresa 20 ms (mimimum) activelow,open-drainoutput. RESET# operatesas an inputwhen notactivatedby ConfigurationRegister1.Settingthislinelowwillresetallof theregistersintheLM87 totheirpower on defaultstate.AllValueRAM locationswillnotbe affectedexceptfor theDAC Data Register. NAND TREE TESTS A NAND treeisprovidedinthe LM87 forAutomated Test Equipment (ATE) board levelconnectivitytesting. DACOut/NTEST_IN, INT#, THERM#, V+ and GND pins are excluded from NAND tree testing.Taking DACOut/NTEST_IN highduringpower up activatestheNAND Tree testmode. AfterthefirstSMBus access to the LM87 the NAND Tree testmode isterminatedand cannotbe reactivatedwithoutrepeatingthe power up sequence.To performa NAND treetest,allpinsincludedintheNAND treeshouldbe drivento1 forcingthe ADD/NTEST_OUT high.Each individualpin startingwithSMBData and concludingwithRESET# (excluding DACOut/NTEST_IN, INT#,THERM#, V+ and GND) can be takenlow withtheresultingtoggleobservedon the ADD/NTEST_OUT pin.Allowfora typicalpropagationdelayof500 ns. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com Figure15. NAND Tree TestStructure FAN MANUFACTURERS Manufacturersofcoolingfanswithtachometeroutputsarelistedbelow: NMB Tech 9730 IndependenceAve. Chatsworth,California91311 818 341-3355 818 341-8207 Model Number Frame Size AirflowCFM 2408NL 2.36insq.X 0.79in 9-16 (60mm sq.X 20 mm) 2410ML 2.36insq.X 0.98in 14-25 (60mm sq.X 25 mm) 3108NL 3.15insq.X 0.79in 25-42 (80mm sq.X 20 mm) 3110KL 3.15insq.X 0.98in 25-40 (80mm sq.X 25 mm) MechatronicsInc. P.O.Box 20 MercerIsland,WA 98040 800 453-4569 Varioussizesavailablewithtachoutputoption. Sanyo Denki America,Inc. 468 Amapola Ave. Torrance,CA 90501 310 783-5400 Model Number Frame Size AirflowCFM 109P06XXY601 2.36insq.X 0.79in 11-15 (60mm sq.X 20 mm) 109R06XXY401 2.36insq.X 0.98in 13-28 (60mm sq.X 25 mm) 109P08XXY601 3.15insq.X 0.79in 23-30 (80mm sq.X 20 mm) 109R08XXY401 3.15insq.X 0.98in 21-42

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 Model Number Frame Size AirflowCFM (80mm sq.X 25 mm) REGISTERS AND RAM 13.1Address PointerRegister The main registeristheAddressPointerRegister.The bitdesignationsareas follows: Bit Name Read/Write Description 7-0 AddressPointer Write AddressofRAM and Registers.See thetablesbelowfordetail. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 AddressPointer(PowerOn default00h) A7 A6 A5 A4 A3 A2 A1 A0 Address PointerIndex(A7–A0) Registersand RAM A6 –A0 inHex Power On Value ofRegisters: Notes <7:0> inBinary InternalTemp. Hardware High 13h 0100 0110 70 °C Default-<7:0>=0100 0110 -User Limit adjustable.Lockableby settingbit1 ofregister 4Ah. ExternalTemp. Hardware High 14h 0101 0101 85 °C Default-<7:0>=0101 0101 -User Limit adjustable.Lockableby settingbit2 ofregister 4Ah. TestRegister 15h 0000 0000 Alwayssetto00h ChannelMode Register 16h 0000 0000 InternalTemp. Hardware High 17h 0100 0110 70 °C Default-<7:0>=0100 0110 -User Limit adjustable ExternalTemp. Hardware High 18h 0101 0101 85 °C Default-<7:0>=0101 0101 -User Limit adjustable ValueRAM 19h–3Dh See ValueRAM — Address19h–3Fh fordetails. Address19h default=11111111 Company ID 3Eh 0000 0010 ThisdesignatestheTexas InstrumentsLM87. Revision 3Fh 0000 0110 Revisionsofthisdevicewillstartwith1 and incrementby one. ConfigurationRegister1 40h 0000 1000 InterruptStatusRegister1 41h 0000 0000 InterruptStatusRegister2 42h 0000 0000 InterruptMask Register1 43h 0000 0000 InterruptMask Register2 44h 0000 0000 CI ClearRegister 46h 0000 0000 VID0-3/FanDivisor 47h <7:4> = 0101; Register <3:0> = VID3–VID0 VID4 Register 49h <7:1> =1000 000;<0>=VID4 ConfigurationRegister2 4Ah 0000 0000 InterruptStatusRegister1 Mirror 4Ch 0000 0000 InterruptStatusRegister2 Mirror 4Dh 0000 0000 SMBALERT# Enable 80h 0010 0000 Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com TestRegister— Address 15h Power on default– <7:0> = 00000000 binary Bit Name Read/Write Description 0 Shutdown Read/Write A one placestheLM87 ina lowerpower "Shutdown"mode.

1 Reserved Read/Write

2 Reserved Read/Write

3 Reserved Read/Write

4 Reserved Read/Write

5 Reserved Read/Write

6 Reserved Read/Write

7 Reserved Read/Write

Channel Mode Register— Address 16h Power on default– <7:0> = 00000000 binary Bit Name Read/Write Description 0 FAN1/AIN1 Read/Write A one enablestheinputas AIN1,a zeroenablestheinputas FAN1. 1 FAN2/AIN2 Read/Write A one enablestheinputas AIN2,a zeroenablestheinputas FAN2. 2 2.5V,VCCP2 /D2 Read/Write A one enablesthe2.5V,VCCP2 /D2 inputsas a second remotediodetemperatureinput. 3 Int.VCC Range Read/Write A one configurestheLM87 for5.0VVCC measurement.A zeroconfiguresitfor3.3VVCC measurement. 4 IRQ0 EN Read/Write A one enablespin24 as an activelowinterruptinput.Bit7 must alsobe settoconfigurethe VID/IRQinputstoIRQ mode. 5 IRQ1 EN Read/Write A one enablespin23 as an activelowinterruptinput.Bit7 must alsobe settoconfigurethe VID/IRQinputstoIRQ mode. 6 IRQ2 EN Read/Write A one enablespin22 as an activelowinterruptinput.Bit7 must alsobe settoconfigurethe VID/IRQinputstoIRQ mode. 7 VID/IRQ Read/Write A one configurestheVID/IRQinputsas InterruptInputs.A zeroconfigurestheVID/IRQinputsas VID inputsonly.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 ConfigurationRegister1— Address 40h Power on default– <7:0> = 00001000 binary Bit Name Read/Write Description 0 Start Read/Write A one enablesstartupofmonitoringoperations,a zeroputsthepartinstandbymode. Note:The outputsofInterruptpinswillnotbe clearediftheuserwritesa zerotothislocationafter an interrupthas occurred,unlikethe“INT_Clear”bit. Atstartup,limitcheckingfunctionsand scanningbegin.Note,alllimitsshouldbe setintheValue RAM beforesettingthisbitHIGH. 1 INT# Enable Read/Write A one enablestheINT# Interruptoutput. 2 THERM# Enable Read/Write A one enablestheTHERM# Interruptoutput. 3 INT#_Clear Read/Write A one disablestheINT# outputwithoutaffectingthecontentsofInterruptStatusRegisters.The devicewillstopmonitoring.Itwillresume upon clearingofthisbit. 4 RESET# Read/Write A one outputsa 20 ms minimum activelowresetsignalatRESET#. Thisbitisclearedonce the pulsehas gone inactive. 6 THERM#_Clear Read/Write A one disablestheTHERM# outputwithoutaffectingthecontentsofInterruptStatusRegisters. 7 INITIALIZATION Read/Write A one restorespower on defaultvaluestotheConfigurationRegister,InterruptStatusRegisters, InterruptMask Registers,CI ClearRegister,VID/FanDivisorRegister,VID4,Temperature ConfigurationRegister,and theExtendedMode Registers.Thisbitclearsitselfsincethepower on defaultiszero. InterruptStatusRegister1— Address 41h Power on default– <7:0> = 0000 0000 binary Bit Name Read/Write Description 0 +2.5Vin Read Only A one indicatesa HighorLow limithas been exceeded. 1 Vccp1 Read Only A one indicatesa HighorLow limithas been exceeded. 2 Vcc Read Only A one indicatesa HighorLow limithas been exceeded. 3 +5Vin Read Only A one indicatesa HighorLow limithas been exceeded. 4 Int.Temp. Read Only A one indicatesa HighorLow limithas been exceeded. 5 Ext.Temp. Read Only A one indicatesa HighorLow limithas been exceeded. 6 FAN1/AIN1 Read Only A one indicatesthefancountlimithas been exceeded oran AIN1 HighorLow limithas been exceeded. 7 FAN2/AIN2 Read Only A one indicatesthefancountlimithas been exceeded oran AIN2 HighorLow limithas been exceeded. InterruptStatusRegister2— Address 42h Power on default– <7:0> = 0000 0000 binary Bit Name Read/Write Description 0 +12Vin Read Only A one indicatesa HighorLow limithas been exceeded. 1 Vccp2 Read Only A one indicatesa HighorLow limithas been exceeded.

2 Reserved Read Only

3 Reserved Read Only

4 CI Read Only A one indicatestheCI (ChassisIntrusion)inputhas gone high. 5 THERM# Read Only A one indicatestheTHERM# inputhas been pulledlowby externalcircuitry. 6 D1 Fault Read Only A one indicatestheD1 inputsareshortedtoVcc oropen circuit. 7 D2 Fault Read Only A one indicatestheD2 inputsareshortedtoVcc oropen circuit. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com InterruptMask Register1— Address 43h Power on default– <7:0> = 0000 0000 binary Bit Name Read/Write Description 0 +2.5Vin/D2+ Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 1 Vccp1 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 2 Vcc Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 3 +5Vin Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 4 Int.Temp. Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 5 Ext.Temp. Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 6 FAN1/AIN1 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 7 FAN2/AIN2 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. InterruptMask Register2— Address 44h Power on default– <7:0> = 0000 0000 binary Bit Name Read/Write Description 0 +12Vin Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 1 Vccp2 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 4 ChassisIntrusion Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 5 THERM# Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 6 D1 Fault Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. 7 D2 Fault Read/Write A one disablesthecorrespondinginterruptstatusbitforINT# interrupt. Reserved Register— Address 45h Power on default– <7:0> = 00h.Read/Writeforbackwardscompatibility. CI ClearRegister— Address 46h Power on default– <7:0> = 0000 0000 binary Bit Name Read/Write Description 0-6 Reserved Read/Write 7 CI Clear Read/Write A one outputsa minimum 20 ms (minimum)activelowpulseon theChassisIntrusionpin.The registerbitselfclearsafterthepulsehas been output.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 VID0-3/FanDivisorRegister— Address 47h Power on default– <7:4> is0101,and <3:0>ismapped toVID <3:0> Bit Name Read/Write Description 0-3 VID <3:0> Read Only The VID <3:0> inputsfromthePentium/PRO power suppliesthatindicatetheoperatingvoltage 4-5 FAN1 RPM Control Read/Write FAN1 Speed Control. <5:4> = 00 -divideby 1; <5:4> = 01 -divideby 2; <5:4> = 10 -divideby 4; <5:4> = 11 -divideby 8. 6-7 FAN2 RPM Control Read/Write FAN2 Speed Control. <7:6> = 00 -divideby 1; <7:6> = 01 -divideby 2; <7:6> = 10 -divideby 4; <7:6> = 11 -divideby 8. VID4 Register— Address 49h Power on default– <7:1> = 100 000,<0> = VID4. Bit Name Read/Write Description 0 VID4 Read Only Bit4 ofVID datafromtheCPU orpower supplythatindicatestheoperatingvoltage(e.g.1.5 V to2.9V). 1-7 Reserved Read/Write ConfigurationRegister2— Address 4Ah Power on default– <7:0> = 0000 0000 binary Bit Name Read/Write Description 0 ThermalINT# Mask Read/Write When thisbitissetto1,thermalerroreventswillnotaffecttheINT# interruptoutput. THERM# outputswillstillfunctionnormally. 1 LocalTemp. Register Read/Write When setto1,thisbitlocksinthevaluesetintheInternalTemp. highlimitregisterat0x13h. WriteOnce Bit Once The valuecannotbe changed untila power on resetisperformed,orthechipisre-Initialized by writinga 1 toBit7 ofConfigurationRegister1 (Register40h). 2 Remote Temp. Read/Write When setto1,thisbitlocksinthevaluesetintheExternalTemp. highlimitregisterat RegisterWriteOnce Once 0x14h.The valuecannotbe changed untila power on resetisperformed,orthechipisre- Bit Initializedby writinga 1 toBit7 ofConfigurationRegister1 (Register40h). 3 THERM# Interrupt Read/Write When setto0,theTHERM# outputfunctionsinDefaultmode. When setto1,theTHERM# Mode outputfunctionsinACPI mode. 4-5 Reserved 6 IRQ3 Enable Read/Write When setto1,VID3/IRQ3isenabledas an activehighinterruptinput(iftheIRQEN bitisset inbit7 oftheChannelMode Register). 7 IRQ4 Enable Read/Write When setto1,VID4/IRQ4isenabledas an activehighinterruptinput(iftheIRQEN bitisset inbit7 oftheChannelMode Register). Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com InterruptStatusRegister1 Mirror— Address 4Ch Power on default– <7:0> = 0000 0000 binary Bit Name Read Only Description 0 +2.5Vin Read Only A one indicatesa HighorLow limithas been exceeded. 1 Vccp1 Read Only A one indicatesa HighorLow limithas been exceeded. 2 Vcc Read Only A one indicatesa HighorLow limithas been exceeded. 3 +5Vin Read Only A one indicatesa HighorLow limithas been exceeded. 4 Int.Temp. Read Only A one indicatesa HighorLow limithas been exceeded. 5 Ext.Temp. Read Only A one indicatesa HighorLow limithas been exceeded. 6 FAN1/AIN1 Read Only A one indicatesthefancountlimithas been exceeded oran AIN1 HighorLow limithas been exceeded. 7 FAN2/AIN2 Read Only A one indicatesthefancountlimithas been exceeded oran AIN2 HighorLow limithas been exceeded. nterruptStatusRegister2 Mirror— Address 4Dh Power on default– <7:0> = 0000 0000 binary Bit Name Read Only Description 0 +12Vin Read Only A one indicatesa HighorLow limithas been exceeded. 1 Vccp2 Read Only A one indicatesa HighorLow limithas been exceeded. 4 CI Read Only A one indicatestheCI (ChassisIntrusion)inputhas gone high. 5 THERM# Read Only A one indicatestheTHERM# inputhas been pulledlowby externalcircuitry. 6 D1 Fault Read Only A one indicatestheD1 inputsareshortedtoVcc oropen circuit. 7 D2 Fault Read Only A one indicatestheD2 inputsareshortedtoVcc oropen circuit. SMBALERT# Enable— Address 80h Power on default– <7:0> = 0010 0000 binary Bit Name Read/Write Description

0 Reserved Read Only

1 Reserved Read Only

4 Reserved Read Only

5 Reserved Read Only

6 SMBALERT# Read/Write A one enablestheSMBALERT# mode ofoperation. Enable

7 Reserved Read Only

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013 Value RAM — Address 19h–3Fh Address A6 –A0 Description 19h DAC dataregister;power on default<7:0>=1111 1111 binary 1Ah AIN1 Low Limit 1Bh AIN2 Low Limit 20h +2.5V/ExternalTemperature2 reading 21h Vccp1 reading 22h +Vcc reading 23h +5V reading 24h +12V reading 25h Vccp2 reading 26h ExternalTemperature1 reading 27h InternalTemperaturereading 28h FAN1/AIN1 reading Note:FortheFAN reading,thislocationstoresthenumber ofcountsoftheinternalclockperrevolution. 29h FAN2/AIN2 reading Note:FortheFAN reading,thislocationstoresthenumber ofcountsoftheinternalclockperrevolution. 2Ah Reserved 2Bh +2.5V HighLimit/ExternalTemperature2 HighLimit 2Ch +2.5V Low Limit/ExternalTemperature2 Low Limit 2Dh Vccp1 HighLimit 2Eh Vccp1 Low Limit 2Fh +3.3V HighLimit 30h +3.3V Low Limit 31h +5V HighLimit 32h +5V Low Limit 33h +12V HighLimit 34h +12V Low Limit 35h Vccp2 HighLimit 36h Vccp2 Low Limit 37h ExternalTemperature1 HighLimit 38h ExternalTemperature1 Low Limit 39h InternalTemperatureHighLimit 3Ah InternalTemperatureLow Limit FAN1Count Limit/AIN1HighLimit 3Bh Note:Itisthenumber ofcountsoftheinternalclockfortheLow Limitofthefanspeed. FAN2 Fan Count Limit/AIN2HighLimit 3Ch Note:Itisthenumber ofcountsoftheinternalclockfortheLow Limitofthefanspeed. 3Dh Reserved 3Eh Company Identification.The number inthisregisteridentifiesTexas InstrumentsLM87 (00000010) 3Fh SteppingRegisterLM87 revisionnumber 06h(00000110) Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:LM87

SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com Note: Settingallones to the high limitsforvoltagesand fans (0111 1111 binaryfortemperature)means interruptswillnever be generatedexceptthecase when voltagesgo belowthelowlimits. For voltageinputhighlimits,thedeviceisdoinga greaterthancomparison.For low limits,however,itisdoinga lessthanorequaltocomparison. TypicalApplication InthisPC applicationtheLM87 monitorstemperature,fanspeed for2 fans,and 6 power supplyvoltages.Italsomonitorsan opticalchassisintrusiondetector. The LM87 providesa DAC outputthatcan be used tocontrolfanspeed. Figure16.

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www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013

REVISION HISTORY

Changes from RevisionI(March 2013)toRevisionJ Page Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:LM87

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM87CIMT NRND Production TSSOP (PW) | 24 61 | TUBE No Call TI Level-1-260C-UNLIM -40 to 125 LM87CIMT LM87CIMT.A NRND Production TSSOP (PW) | 24 61 | TUBE No Call TI Call TI -40 to 125 LM87CIMT LM87CIMT/NOPB Obsolete Production TSSOP (PW) | 24 - - Call TI Call TI -40 to 125 LM87CIMT LM87CIMTX/NOPB Active Production TSSOP (PW) | 24 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM87CIMT LM87CIMTX/NOPB.A Active Production TSSOP (PW) | 24 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM87CIMT (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM87CIMTX/NOPB TSSOP PW 24 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM87CIMT PW TSSOP 24 61 495 8 2514.6 4.06 LM87CIMT PW TSSOP 24 61 495 8 2514.6 4.06 LM87CIMT.A PW TSSOP 24 61 495 8 2514.6 4.06 LM87CIMT.A PW TSSOP 24 61 495 8 2514.6 4.06 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 22X 0.65 7.15 24X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 7.9 7.7 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 12 13 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 12 13

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