LM85

LM85 NSC | Alldatasheet

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Technical content

Features

n 2-wire, SMBus 2.0 compliant, serial digital interface n 8-bit Σ∆ ADC n Monitors VCCP, 2.5V, 3.3 VSBY, 5.0V, and 12V motherboard/processor supplies n Monitors 2 remote thermal diodes n Programmable autonomous fan control based on temperature readings n Noise filtering of temperature reading for fan control n 1.0˚C digital temperature sensor resolution n 3 PWM fan speed control outputs n 4 fan tachometer inputs n Monitors 5 VID control lines n 24-pin QSOP package n XOR-tree test mode Key Specifications n Voltage Measurement Accuracy ±2% FS (max) n Resolution 8-bits, 1˚C n Temperature Sensor Accuracy ±3˚C (max) n Temperature Range — LM85 Operational 0˚C to +85˚C — Remote Temp Accuracy 0˚C to +125˚C n Power Supply Voltage +3.0V to +3.6V n Power Supply Current 0.53 mA

Applications

n Microprocessor based equipment (e.g. Base-stations, Routers, ATMs, Point of Sales) Block Diagram 20035301 March 2003 LM85 Hardware Monitor with Integrated Fan Control © 2003 National Semiconductor Corporation DS200353 www.national.com

24 Pin QSOP

LM85BIMQ or LM85CIMQ (55 units per rail), or LM85BIMQX or LM85CIMQX (2500 units per tape and reel) Information on the differences between the LM85BIMQ and LM85CIMQ can be found in Section 6.0. It is highly recommended that all new designs use the LM85BIMQ . Pin Descriptions Symbol Pin Typ Name and Function/Connection SMBus SMBDAT 1 Digital I/O (Open-Drain) System Management Bus Data. Open-drain output. 5V tolerant, SMBus 2.0 compliant. SMBCLK 2 Digital Input System Management Bus Clock. Tied to Open-drain output. 5V tolerant, SMBus 2.0 compliant. Processor VID Lines VID0 5 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. VID1 6 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. VID2 7 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. VID3 8 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. VID4 19 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. Power 3.3V 4 POWER +3.3V pin. Can be powered by +3.3V Standby power if monitoring in low power states is required. This pin also serves as the analog input to monitor the 3.3V supply. This pin should be bypassed with a 0.1µf capacitor in parallel with 100pf. A bulk capacitance of approximately 10µf needs to be in the near vicinity of the LM85. GND 3 GROUND Ground for all analog and digital circuitry. Voltage Inputs 5V 20 Analog Input Analog input for +5V monitoring. 12V 21 Analog Input Analog input for +12V monitoring. 2.5V 22 Analog Input Analog input for +2.5V monitoring. VCCP 23 Analog Input Analog input for +V CCP (processor voltage) monitoring. LM85 www.national.com 2

Pin Descriptions (Continued) Symbol Pin Typ Name and Function/Connection Remote Remote1+ 18 Remote Thermal Diode Positive Input Positive input (current source) from the first remote thermal diode. Serves as the positive input into the A/D. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor. Remote1− 17 Remote Thermal Diode Negative Input Negative input (current sink) from the first remote thermal diode. Serves as the negative input into the A/D. Connected to THERMDC pin of Pentium processor or the emmiter of a diode connected MMBT3904 NPN transistor. Remote2+ 16 Remote Thermal Diode Positive Output Positive input (current source) from the first remote thermal diode. Serves as the positive input into the A/D. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor. Remote2− 15 Remote Thermal Diode Negative Input Negative input (current sink) from the first remote thermal diode. Serves as the negative input into the A/D. Connected to THERMDC pin of Pentium processor or the emmiter of a diode connected MMBT3904 NPN transistor. Fan Tachometer Inputs TACH1 11 Digital Input Input for monitoring tachometer output of fan 1. TACH2 12 Digital Input Input for monitoring tachometer output of fan 2. TACH3 9 Digital Input Input for monitoring tachometer output of fan 3. TACH4/Address Select 14 Digital Input Input for monitoring tachometer output of fan 4. If in Address Select Mode, determines the SMBus address of the LM85. Fan Control PWM1/xTest Out

24 Digital Open-Drain

Fan speed control 1. When in XOR tree test mode, functions as XOR Tree output. PWM2 10 Digital Open-Drain Output Fan speed control 2. PWM3/Address Enable

13 Digital Open-Drain

Fan speed control 3. Pull to ground at power on to enable Address Select Mode (Address Select pin controls SMBus address of the device). LM85 www.national.com3

Absolute Maximum Ratings (Notes 1, If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, V+ −0.5V to 6.0V Voltage on Any Digital Input or Output Pin −0.5V to 6.0V Voltage on 12V Analog Input −0.5V to 16V Voltage on 5V Analog Input −0.5V to 6.66V Voltage on Remote1+, Remote2+, −0.5V to (V+ + 0.05V) Current on Remote1−, Remote2− ±1m A Voltage on Other Analog Inputs −0.5V to 6.0V Input Current on Any Pin (Note 3) ±5m A Package Input Current (Note 3) ±20 mA Package Dissipation at T A = 25˚C See (Note 5) ESD Susceptibility (Note 4) Human Body Model 2500V Machine Model 250V Soldering Temperature, Infrared, 10 seconds (Note 6) 235˚C Storage Temperature −65˚C to +150˚C Operating Ratings (Notes 1, 2) LM85 Operating Temperature Range 0˚C ≤ TA ≤ +85˚C Remote Diode Temperature Range 0˚C ≤ TD ≤ +125˚C Supply Voltage (3.3V nominal) +3.0V to +3.6V V IN Voltage Range +12V VIN −0.05V to 16V +5V VIN −0.05V to 6.66V +3.3V VIN 3.0V to 4.4V VCCP and All Other Inputs −0.05V to (V+ + 0.05V) VID0–VID4 −0.05V to 5.5V Typical Supply Current 0.53 mA The following specifications apply for V+ = 3.0V to 3.6V, and all analog input source impedance R S =5 0Ω unless otherwise specified in conditions. Boldface limits apply for T A =T MIN to TMAX; all other limits T A = 25˚C. Symbol Parameter Conditions Typical (Note 7) Limits (Note 8) Units (Limits) POWER SUPPLY CHARACTERISTICS Supply Current (Note 9) Converting, Interface and Fans Inactive, Peak Current 1.8 3.5 mA (max) Converting, Interface and Fans Inactive, Average Current 0.53 mA Power-On Reset Threshold Voltage 1.6 V (min)

2.8 V (max)

TEMPERATURE TO DIGITAL CONVERTER CHARACTERISTICS Resolution 1 Bits Temperature Accuracy (See (Note 10) for Thermal Diode Processor Type) At 25˚C ±2.5 ˚C (max) 0˚C to 100˚C ±3 ˚C (max) 100˚C to 125˚C ±4 ˚C (max) Temperature Accuracy using Internal Diode (Note 11) 0˚C to 85˚C ±3 ˚C (max) IDS External Diode Current Source High Level 188 280 µA (max) Low Level 11.75 µA External Diode Current Ratio 16 ANALOG TO DIGITAL CONVERTER CHARACTERISTICS TUE Total Unadjusted Error(Note 12) LM85CIMQ -0.5/+3.5 %FS (max) LM85BIMQ ±2 %FS (max) DNL Differential Non-linearity 1 LSB Power Supply Sensitivity ±1 %/V Total Monitoring Cycle Time (Note 13) All Voltage and Temperature readings 182 200 ms (max) LM85 www.national.com 4

The following specifications apply for V+ = 3.0V to 3.6V, and all analog input source impedance R S =5 0Ω unless otherwise specified in conditions. Boldface limits apply for T A =T MIN to TMAX; all other limits T A = 25˚C. Symbol Parameter Conditions Typical (Note 7) Limits (Note 8) Units (Limits) Input Resistance, all analog inputs 210 140 kΩ (min) 400 kΩ (max) DIGITAL OUTPUT: PWM1, PWM2, PWM3, XTESTOUT I OL Logic Low Sink Current LM85CIMQ V OL=0.55V 8 mA (min) LM85BIMQ V OL=0.4V 8 mA (min) VOL Logic Low Level LM85CIMQ I OUT =+ 3m A 0.4 V (max) IOUT =+ 8m A 0.55 V (max) LM85BIMQ I OUT =+ 8m A 0.4 V (max) SMBUS OPEN-DRAIN OUTPUT: SMBDAT V OL Logic Low Output Voltage I OUT =+ 4m A 0.4V V (max) IOH High Level Output Current V OUT = V+ 0.1 10 µA (max) SMBUS INPUTS: SMBCLK. SMBDAT V IH Logic Input High Voltage 2.1 V (min) VIL Logic Input Low Voltage 0.8 V (max) VHYST Logic Input Hysteresis Voltage 300 mV DIGITAL INPUTS: ALL V IH Logic Input High Voltage 2.1 V (min) VIL Logic Input Low Voltage 0.8 V (max) VTH Logic Input Threshold Voltage 1.5 V IIH Logic High Input Current V IN = V+ 0.005 10 µA (max) IIL Logic Low Input Current V IN = GND −0.005 −10 µA (max) CIN Digital Input Capacitance 20 pF The following specifications apply for V+ = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for T A =T MIN to TMAX; all other limits T A = 25˚C. Symbol Parameter Conditions Typical (Note 7) Limits (Note 8) Units (Limits) TACHOMETER ACCURACY Fan Count Accuracy ±10 % (max) Fan Full-Scale Count 65536 (max) Fan Counter Clock Frequency 90 kHz Fan Count Conversion Time 0.7 1.4 sec (max) FAN PWM OUTPUT Frequency Setting Accuracy ±10 % (max) Frequency Range 10 Hz Hz Duty-Cycle Range 0t o1 0 0 % (max) Duty-Cycle Resolution (8-bits) 0.390625 % Spin-Up Time Interval Range 100 4000 ms ms Spin-Up Time Interval Accuracy ±10 % (max) SPIKE SMOOTHING FILTER Time Interval Deviation ±10 % (max) Time Interval Range 35 0.8 sec sec LM85 www.national.com5

The following specifications apply for V+ = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for T A =T MIN to TMAX; all other limits T A = 25˚C. Symbol Parameter Conditions Typical (Note 7) Limits (Note 8) Units (Limits) SMBUS TIMING CHARACTERISTICS f SMB SMBus Operating Frequency 10 100 kHz (min) kHz (max) fBUF SMBus Free Time Between Stop And Start Condition 4.7 µs (min) tHD_STA Hold Time After (Repeated) Start Condition (after this period, the first clock is generated) 4.0 µs (min) t SU:STA Repeated Start Condition Setup Time 4.7 µs (min) tSU:STO Stop Condition Setup Time 4.0 µs (min) tHD:DAT Data Output Hold Time 300 ns (min) 930 ns (max) tSU:DAT Data Input Setup Time 250 ns (min) tTIMEOUT Data And Clock Low Time To Reset Of SMBus Interface Logic(Note 14) ms (min) ms (max) tLOW Clock Low Period 4.7 µs (min) tHIGH Clock High Period 4.0 µs (min) µs (max) tF Clock/Data Fall Time 300 ns (max) tR Clock/Data Rise Time 1000 ns (max) tPOR Time from Power-On-Reset to LM85 Reset and Operational V+ > 2.8V 500 ms (max) 20035303 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characterist ics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the lis ted test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise noted. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN >V+ ), the current at that pin should be limited to 5mA. The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5mA to four. Note 4: Human body model, 100pF discharged through a 1.5k Ω resistor. Machine model, 200pF discharged directly into each pin. Note 5: Thermal resistance junction-to-ambient when attached to a printed circuit board with 2 oz. foil is 125˚C/W. Note 6: See the URL ”http://www.national.com/packaging/“ for other recommendations and methods of soldering surface mount devices. Note 7: Typicals are at TA = 25˚C and represent most likely parametric norm. Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 9: The average current can be calculated from the peak current using the following equation: Quiescent current will not increase substantially with an SMBus transaction. Note 10: The accuracy of the LM85CIMQA is guaranteed when using the thermal diode of Intel Pentium 4 processors in 423 pin or 478 pin packages or any thermal diode with a typical non-ideality factor of 1.0045. The accuracy of the LM85BIMQA is guaranteed when using the thermal diode of an Intel Pentium 4 proce ssors or any thermal diode with a typical non-ideality of 1.0021 and series resistance of 3.64 Ω or 3.86Ω. When using a 2N3904 type transistor as a thermal diode the error band will be typically shifted by -1˚C. Note 11: Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the internal po wer dissipation of the LM85 and the thermal resistance. See (Note 5) for the thermal resistance to be used in the self-heating calculation. LM85 www.national.com 6

Note 12: TUE , total unadjusted error, includes ADC gain, offset, linearity and reference errors. TUE is defined as the "actual Vin" to achieve a given code transition minus the "theoretical Vin" for the same code. Therefore, a positive error indicates that the input voltage is greater than the theoretical input voltage for a given code. If the theoretical input voltage was applied to an LM85 that has positive error, the LM85’s reading would be less than the theoretical. Note 13: This specification is provided only to indicate how often temperature and voltage data is updated. The LM85 can be read at any time without regard to conversion state (and will yield last conversion result). Note 14: Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM85’s SMBus state machine, therefore setting the SMBDAT pin to a high impedance state. Functional Description

1.0 SMBUS

The LM85 is compatible with devices that are compliant to the SMBus 2.0 specification. More information on this bus can be found

1.1 Addressing

LM85 is designed to be used primarily in desktop systems that require only one monitoring device. If only one LM85 is used on the motherboard, the designer should be sure that the Address Enable/PWM3 pin is High during the first SMBus communication addressing the LM85. Address Enable/PWM3 is an open drain I/O pin that at power-on defaults to the input state. A maximum of 10k pull-up resistance is required to assure that the SMBus address of the device will be locked at 010 1110b, which is the default address of the LM85. During the first SMBus communication TACH4 and PWM3 can be used to change the SMBus address of the LM85. to 0101101b or 0101100b. LM85 address selection procedure: A1 0k Ω pull-down resistor to ground on the Address Enable/PWM3 pin is required. Upon power up, the LM85 will be placed into Address Enable mode and assign itself an SMBus address according to the state of the Address Select input. The LM85 will latch the address during the first valid SMBus transaction in which the first five bits of the targeted address match those of the LM85 address, 0 1011b. This feature eliminates the possibility of a glitch on the SMBus interfering with address selection. When the PWM3/Address Enable pin is not used to change the SMBus address of the LM85, it will remain in a high state until the first communication with the LM85. After the first SMBus transaction is completed PWM3 and TACH4 will return to normal operation. Address Enable Address Select Board Implementation SMBus Address 0 0 Pulled to ground through a 10 k Ω resistor 010 1100b, 2Ch 0 1 Pulled to 3.3V or ground through a 10 k Ω resistor 010 1101b, 2Dh 1 X Pulled to 3.3V through a 10k Ω resistor 010 1110b, 2Eh In this way, up to three LM85 devices can exists on an SMBus at any time. Multiple LM85 devices can be used to monitor additional processors and temperature zones. 20035304

2.0 FAN REGISTER DEVICE SET-UP

The BIOS will follow the following steps to configure the fan registers on the LM85. The registers corresponding to each function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by the BIOS to the fan limit and parameter registers during configuration, the LM85 will continue to operate based on default values until the START bit (bit 0), in the Ready/Lock/Start/Override register (address 40h), is set. Once the fan mode is updated, by setting the START bit to 1, the LM85 will operate using the values that were set by the BIOS in the fan control limit and parameter registers (adress 5Ch through 6Eh). LM85 www.national.com7

Functional Description (Continued) 1. Set limits and parameters (not necessarily in this order): – [5F-61h] Set PWM frequencies and auto fan control range. – [62-63h] Set spike smoothing and min/off. – [5C-5Eh] Set the fan spin-up delays. – [5C-5Eh] Match each fan with a corresponding thermal zone. – [67-69h] Set the fan temperature limits. – [6A-6Ch] Set the temperature absolute limits. – [64-66h] Set the PWM minimum duty cycle. – [6D-6Eh] Set the temperature Hysteresis values. 2. [40h] Set bit 0 (START) to update fan control and limit register values and start fan control based on these new values. 3. [40h] Set bit 1 (LOCK) to lock the fan limit and parameter registers (optional).

3.0 AUTO FAN CONTROL OPERATING MODE

The LM85 includes the circuitry for automatic fan control. In Auto Fan Mode, the LM85 will automatically adjust the PWM duty cycle of the PWM outputs. PWM outputs are assigned to a thermal zone based on the fan configuration registers. It is possible to have more than one PWM output assigned to a thermal zone. For example, PWM outputs 2 and 3, connected to two chassis fans, may both be controlled by thermal zone 2. At any time, the temperature of a zone exceeds its absolute limit, all PWM outputs will go to 100% duty cycle to provide maximum cooling to the system.

4.0 REGISTER SET

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value Lock? 20h R 2.5V 7 6 5 4 3 2 1 0 N/A 21h R V CCP 7 6 5 4 3 2 1 0 N/A 22h R 3.3V 7 6 5 4 3 2 1 0 N/A 23h R 5V 7 6 5 4 3 2 1 0 N/A 24h R 12V 7 6 5 4 3 2 1 0 N/A 25h R Processor (Zone1) Temp 7 6 5 4 3 2 1 0 N/A 26h R Internal (Zone2) Temp 7 6 5 4 3 2 1 0 N/A 27h R Remote (Zone3) Temp 7 6 5 4 3 2 1 0 N/A 28h R Tach1 LSB 7 6 5 4 3 2 LEVEL1 LEVEL0 N/A 29h R Tach1 MSB 15 14 13 12 11 10 9 8 N/A 2Ah R Tach2 LSB 7 6 5 4 3 2 LEVEL1 LEVEL0 N/A 2Bh R Tach2 MSB 15 14 13 12 11 10 9 8 N/A 2Ch R Tach3 LSB 7 6 5 4 3 2 LEVEL1 LEVEL0 N/A 2Dh R Tach3 MSB 15 14 13 12 11 10 9 8 N/A 2Eh R Tach4 LSB 7 6 5 4 3 2 LEVEL1 LEVEL0 N/A 2Fh R Tach4 MSB 15 14 13 12 11 10 9 8 N/A 30h R/W Fan1 Current PWM Duty 7 6 5 4 3 2 1 0 N/A 31h R/W Fan2 Current PWM Duty 7 6 5 4 3 2 1 0 N/A 32h R/W Fan3 Current PWM Duty 7 6 5 4 3 2 1 0 N/A 3Eh R Company ID 7 6 5 4 3 2 1 0 01h 3Fh R Version/Stepping VER3 VER2 VER1 VER0 STP3 STP2 STP1 STP0 60h 40h R/W Ready/Lock/Start/Override RES RES RES RES OVRID READY LOCK START 00h 41h R Interrupt Status Register 1 ERR ZN3 ZN2 ZN1 5V 3.3V V CCP 2.5V 00h 42h R Interrupt Status Register 2 ERR2 ERR1 FAN4 FAN3 FAN2 FAN1 RES 12V 00h 43h R VID0–4 RES RES RES VID4 VID3 VID2 VID1 VID0 N/A 44h R/W 2.5V Low Limit 7 6 5 4 3 2 1 0 00h 45h R/W 2.5V High Limit 7 6 5 4 3 2 1 0 FFh 46h R/W V CCP Low Limit 7 6 5 4 3 2 1 0 00h 47h R/W V CCP High Limit 7 6 5 4 3 2 1 0 FFh 48h R/W 3.3V Low Limit 7 6 5 4 3 2 1 0 00h LM85 www.national.com 8

Functional Description (Continued) Register Address Read/ Write Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value Lock? 49h R/W 3.3V High Limit 7 6 5 4 3 2 1 0 FFh 4Ah R/W 5V Low Limit 7 6 5 4 3 2 1 0 00h 4Bh R/W 5V High Limit 7 6 5 4 3 2 1 0 FFh 4Ch R/W 12V Low Limit 7 6 5 4 3 2 1 0 00h 4Dh R/W 12V High Limit 7 6 5 4 3 2 1 0 FFh 4Eh R/W Processor (Zone1) Low Temp 7 6 5 4 3 2 1 0 81h 4Fh R/W Processor (Zone1) High Temp 7 6 5 4 3 2 1 0 7Fh 50h R/W Internal (Zone2) Low Temp 7 6 5 4 3 2 1 0 81h 51h R/W Internal (Zone2) High Temp 7 6 5 4 3 2 1 0 7Fh 52h R/W Remote (Zone3) Low Temp 7 6 5 4 3 2 1 0 81h 53h R/W Remote (Zone3) High Temp 7 6 5 4 3 2 1 0 7Fh 54h R/W Tach1 Minimum LSB 7 6 5 4 3 2 1 0 FFh 55h R/W Tach1 Minimum MSB 15 14 13 12 11 10 9 8 FFh 56h R/W Tach2 Minimum LSB 7 6 5 4 3 2 1 0 FFh 57h R/W Tach2 Minimum MSB 15 14 13 12 11 10 9 8 FFh 58h R/W Tach3 Minimum LSB 7 6 5 4 3 2 1 0 FFh 59h R/W Tach3 Minimum MSB 15 14 13 12 11 10 9 8 FFh 5Ah R/W Tach4 Minimum LSB 7 6 5 4 3 2 1 0 FFh 5Bh R/W Tach4 Minimum MSB 15 14 13 12 11 10 9 8 FFh 5Ch R/W Fan1 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U 5Dh R/W Fan2 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U 5Eh R/W Fan3 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U 5Fh R/W Fan1 Range/Frequency RAN3 RAN2 RAN1 RAN0 RES FRQ2 FRQ1 FRQ0 C4h U 60h R/W Fan2 Range/Frequency RAN3 RAN2 RAN1 RAN0 RES FRQ2 FRQ1 FRQ0 C4h U 61h R/W Fan3 Range/Frequency RAN3 RAN2 RAN1 RAN0 RES FRQ2 FRQ1 FRQ0 C4h U 62h R/W Min/Off, Zone1 Spike Smoothing OFF3 OFF2 OFF1 RES ZN1E ZN1-2 ZN1-1 ZN1-0 00H U 63h R/W Zone2, Zone3 Spike Smoothing ZN2E ZN2-2 ZN2-1 ZN2-0 ZN3E ZN3-2 ZN3-1 ZN3-0 00h U 64h R/W Fan1 PWM Minimum 7 6 5 4 3 2 1 0 80h U 65h R/W Fan2 PWM Minimum 7 6 5 4 3 2 1 0 80h U 66h R/W Fan3 PWM Minimum 7 6 5 4 3 2 1 0 80h U 67h R/W Zone1 Fan Temp Limit 7 6 5 4 3 2 1 0 5Ah U 68h R/W Zone2 Fan Temp Limit 7 6 5 4 3 2 1 0 5Ah U 69h R/W Zone3 Fan Temp Limit 7 6 5 4 3 2 1 0 5Ah U 6Ah R/W Zone1 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h U 6Bh R/W Zone2 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h U 6Ch R/W Zone3 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h U 6Dh R/W Zone1, Zone2 Hysteresis H1-3 H1-2 H1-1 H1-0 H2-3 H2-2 H2-1 H2-0 44h U 6Eh R/W Zone3 Hysteresis H3-3 H3-2 H3-1 H3-0 RES RES RES RES 40h U LM85 www.national.com9

Note: Reserved bits will always return 0 when read.

4.1 Register 20-24h: Voltage Reading

only — a write to these registers has no effect.

4.2 Register 25-27h: Temperature Reading

pins, and the Internal (Zone2) Temp register reports the temperature measured by the internal (junction) temperature sensor. TABLE 1. Temperature vs Register Reading

TABLE 1. Temperature vs Register Reading (Continued)

4.3 Register 28-2Fh: Fan Tachometer Reading

registers will be updated at least once every second. The value, for each fan, is represented by a 16-bit unsigned number. [LEVEL1:LEVEL2]=01 indicates the least accurate value and [LEVEL1:LEVEL2]=00 is reserved for future use. read only — a write to these registers has no effect. the start of an LSByte read. Therefore, reading the MSByte register twice in a row will yield the same data. the end of the MSByte read the Fan Tachometer Reading registers are updated. During spin-up, the PWM duty cycle reported is 0%.

4.4 Register 30-32h: Current PWM Duty

and the PWM signals will be updated based on the algorithm described in the Auto Fan Control Operating Mode section. duty cycle is represented as shown in the following table.

Functional Description (Continued) Current Duty Value (Decimal) Value (Hex) 50.196% 128 80h 100% 255 FFh

4.5 Register 3Eh: Company ID

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value 3Eh R Company ID 7 6543210 0 1 h The company ID register contains the company identification number. For National Semiconductor this is 01h. This number is assigned by Intel and is a method for uniquely identifying the part manufacturer. This register is read only — a write to this register has no effect.

4.6 Register 3Fh: Version/Stepping

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value 3Fh R Version/Stepping VER3 VER2 VER1 VER0 STP3 STP2 STP1 STP0 60h The four least significant bits of the Version/Stepping register [3.0] contain the current stepping of the LM85 silicon. The four most significant bits [7.4] reflect the LM85 base device number when set to a value of 0110b. All LM85 revisions will have a base number of 6. For the LM85C, this register will read 01100000b (60h). The LM85B will read 01100010b (62h).If new revisions of the LM85C or LM85B are released the last 4 bits of this register will change. The register is used by application software to identify which device in the hardware monitor family of ASICs has been implemented in the given system. Based on this information, software can determine which registers to read from and write to. Further, application software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping. This register is read only — a write to this register has no effect.

4.7 Register 40h: Ready/Lock/Start/Override

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value 40h R/W Ready/Lock/Start/Override RES RES RES RES OVRID READY LOCK START 00h Bit Name R/W Default Description

0 START R/W 0 When software write sa1t o this bit, the LM85 fan monitoring and PWM output

control functions will use the values set in the fan control limit and parameter registers (address 5Ch through 6Eh). Before this bit is set, the LM85 will not update the used register values, the default values will remain in effect. Whenever this bit is set to 0, the LM85 fan monitoring and PWM output control functions use the default fan limits and parameters, regardless of the current values in the limit and parameter registers (5C through 6Eh). The LM85 will preserve the values currently stored in the limit and parameter registers when this bit is set or cleared. This bit becomes read only when the Ready/Lock/Start/Override register Lock bit is set. It is expected that all limit and parameter registers will be set by BIOS or application software prior to setting this bit. LM85 www.national.com 12

Functional Description (Continued) Bit Name R/W Default Description 1 LOCK R/W 0 Setting this bit to 1 locks specified limit and parameter registers. Once this bit is set, limit and parameter registers become read only and will remain locked until the device is powered off. This register bit becomes read only once it is set.

2 READY R 0 The LM85 sets this bit automatically after the part is fully powered up, has

completed the power-up-reset process, and after all A/D converters are properly functioning.

3 OVRID R/W If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of

whether or not the lock bit is set. For the LM85C only, when a PWM is programmed in the disabled mode (Fan Configuration registers 5C-5Eh, bits fan_config[7:5] = ZON[2:0]=100) the PWM stays in the disabled mode for this LM85B the OVRID bit has precedence over the disabled mode. Therefore, when OVRID is set the PWM will go to 100% even if the PWM is in the disabled mode. 4–7 Reserved R 0 Reserved

4.8 Register 41h: Interrupt Status Register 1

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value 41h R Interrupt Status 1 ERR ZN3 ZN2 ZN1 5V 3.3V V CCP 2.5V 00h The Interrupt Status Register 1 bits will be automatically set, by the LM85, whenever a fault condition is detected. A fault condition is detected whenever a measured value is outside the window set by its limit registers. ZN3 and ZN1 bits will be set when a diode fault condition, such as a disconect or short, is detected. More than one fault may be indicated in the interrupt register when read. This register will hold a set bit(s) until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the LM85 after it is read by software, if the fault condition is no longer exists. Once set, the Interrupt Status Register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists This register is read only — a write to this register has no effect. Bit Name R/W Default Description 0 2.5V_Error R 0 The LM85 automatically sets this bit to 1 when the 2.5V input voltage is less than or equal to the limit set in the 2.5V Low Limit register or greater than the limit set in the 2.5V High Limit register. CCP_Error R 0 The LM85 automatically sets this bit to 1 when the V CCP input voltage is less than or equal to the limit set in the V CCP Low Limit register or greater than the limit set in the V CCP High Limit register. 2 3.3V_Error R 0 The LM85 automatically sets this bit to 1 when the 3.3V input voltage is less than or equal to the limit set in the 3.3V Low Limit register or greater than the limit set in the 3.3V High Limit register. 3 5V_Error R 0 The LM85 automatically sets this bit to 1 when the 5V input voltage is less than or equal to the limit set in the 5V Low Limit register or greater than the limit set in the 5V High Limit register.

4 Zone 1 Limit

R 0 The LM85 automatically sets this bit to 1 when the temperature input measured by the Remote1− and Remote1+ inputs is less than or equal to the limit set in the Processor (Zone1) Low Temp register or more than the limit set in the Processor (Zone1) High Temp register. This bit will be set when a diode fault is detected.

5 Zone 2 Limit

R 0 The LM85 automatically sets this bit to 1 when the temperature input measured by the internal temperature sensor is less than or equal to the limit set in the Internal (Zone2) Low Temp register or greater than the limit set in the Internal (Zone2) High Temp register. LM85 www.national.com13

Functional Description (Continued) Bit Name R/W Default Description

6 Zone 3 Limit

R 0 The LM85 automatically sets this bit to 1 when the temperature input measured by the Remote2− and Remote2+ inputs is less than or equal to the limit set in the Internal (Zone2) Low Temp register or greater than the limit set in the Remote (Zone3) High Temp register. This bit will be set when a diode fault is detected.

7 Error in Status

R 0 If there is a set bit in Status Register 2, this bit will be set to 1.

4.9 Register 42h: Interrupt Status Register 2

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value 42h R Interrupt Status Register 2 ERR2 ERR1 FAN4 FAN3 FAN2 FAN1 RES 12V 00h The Interrupt Status Register 2 bits will be automatically set, by the LM85, whenever a fault condition is detected. Interrupt Status Register 2 identifies faults caused by temperature sensor error, fan speed droping below minimum set by the tachometer minimum register, the 12V input voltage going outside the window set by its limit registers. Interrupt Status Register 2 will hold a set bit until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the LM85 after it is ready by software, if fault condition no longer exists. Once set, the Interrupt Status Register 2 bits will remain set until a read event occurs, even if the fault no longer exists This register is read only — a write to this register has no effect. Bit Name R/W Default Description 0 +12V_Error R 0 The LM85 automatically sets this bit to 1 when the 12V input voltage either falls below the limit set in the 12V Low Limit register or exceeds the limit set in the 12V High Limit register.

1 Reserved R 0 Reserved

2 Fan1 Stalled R 0 The LM85 automatically sets this bit to 1 when the TACH1 input reading is

above the value set in the Tach1 Minimum MSB and LSB registers.

3 Fan2 Stalled R 0 The LM85 automatically sets this bit to 1 when the TACH2 input reading is

above the value set in the Tach2 Minimum MSB and LSB registers.

4 Fan3 Stalled R 0 The LM85 automatically sets this bit to 1 when the TACH3 input reading is

above the value set in the Tach3 Minimum MSB and LSB registers.

5 Fan4 Stalled R 0 The LM85 automatically sets this bit to 1 when the TACH4 input reading is

above the value set in the Tach4 Minimum MSB and LSB registers.

6 Remote Diode

1 Fault

R 0 The LM85 automatically sets this bit to 1 when there is either a short or open circuit fault on the Remote1+ or Remote1− thermal diode input pins. A diode fault will also set bit 4, Diode 1 Zone Limit bit, of Interrupt Status Register 1.

7 Remote Diode

2 Fault

R 0 The LM85 automatically sets this bit to 1 when there is either a short or open circuit fault on the Remote2+ or Remote2− thermal diode input pins. A diode fault will also set bit 6, Diode 2 Zone Limit bit, of Interrupt Status Register 1.

4.10 Register 43h: VID

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value 43h R VID0–4 RES RES RES VID4 VID3 VID2 VID1 VID0 The VID register contains the values of LM85 VID0–VID4 input pins. This register indicates the status of the VID lines that interconnect the processor to the Voltage Regulator Module (VRM). Software uses the information in this register to determine the voltage that the processor is designed to operate at. With this information, software can then dynamically determine the correct values to place in the V CCP Low Limit and V CCP High Limit registers. This register is read only — a write to this register has no effect. LM85 www.national.com 14

4.11 Registers 44-4Dh: Voltage Limit Registers

Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers. TABLE 2. Voltage Limits vs Register Setting

4.12 Registers 4E-53h: Temperature Limit Registers

limits in these registers are represented as 8 bit, 2’s complement, signed numbers in Celsius, as shown below in Table 3. Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.

TABLE 3. Temperature Limits vs Register Settings

4.13 Registers 54-5Bh: Fan Tachometer Low Limit

Register. Interrupts will never be generated for a fan if its minimum is set to FF FFh. Given the insignificance of Bit 0 and Bit 1, these bits could be programmed to remember which fan is which, as follows. Setting the Ready/Lock/Start/Override register Lock bit has no effect these registers.

4.14 Registers 5C-5Eh: Fan Configuration

is cleared even though modifications to this register are possible. TABLE 4. Fan Zone Setting

000 Fan on zone 1 auto

001 Fan on zone 2 auto

010 Fan on zone 3 auto

011 Fan always on full

100 Fan disabled

101 Fan controlled by hottest of zones 2, 3

110 Fan controlled by hottest of zones 1, 2, 3

111 Fan manually controlled (Test Mode)

will yield an output that is always low. duty cycle for the time specified in the table below before scaling to a lower speed. TABLE 5. Fan Spin-Up Register

4.15 Registers 5F-61h: Auto Fan Speed Range, PWM Frequency

Temperature Limit (Registers 6A-6Ch), the speed of a fan assigned to that zone is determined as follows. When the temperature reaches the Fan Temp Limit for a zone, the PWM output assigned to that zone will be Fan PWM Minimum. as shown in the figure below. The PWM duty cycle will be 100% at (Fan Temp Limit + Range). – Zone 1 Fan Temp Limit (Register 67h) is set to 50˚C (32h). – Range (Register 5Fh) is set to 8˚C (6xh). – Fan 1 PWM Minimum (Register 64h) is set to 50% (32h). In this case, the PWM1 duty cycle will be 50% at 50˚C. of the Zone 1 sensor reaches 58˚C. 100%), PWM1 duty cycle would be 75% at 54˚C. Above (Zone 1 Fan Temp Limit) + (Zone 1 Range), the duty cycle will be 100%. The PWM frequency bits [3:0] determine the PWM frequency for the fan. TABLE 6. Register Setting vs PWM Frequency FIGURE 1. Fan Activity above Fan Temp Limit

Functional Description (Continued) RAN [3:0] Range (˚C) 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 1101 40 1110 53.33 1111 80 This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.

4.16 Registers 62, 63h: Min/Off, Spike Smoothing

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value Lock? 62h R/W Min/Off, Zone1 Spike Smoothing OFF3 OFF2 OFF1 RES ZN1E ZN1-2 ZN1-1 ZN1-0 00h U 63h R/W Zone2, Zone3 Spike Smoothing ZN2E ZN2-2 ZN2-1 ZN2-0 ZN3E ZN3-2 ZN3-1 ZN3-0 00h U The Off/Min Bits [7:5] specify whether the duty cycle will be 0% or Minimum Fan Duty when the measured temperature falls below the Temperature LIMIT register setting (see table below). OFF1 applies to fan 1, OFF2 applies to fan 2, and OFF3 applies to fan If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the LM85. If these spikes are not ignored, the CPU fan (if connected to LM85) may turn on prematurely and produce unpleasant noise. For this reason, any zone that is connected to a chipset or processor should have spike smoothing enabled. When spike smoothing is enabled, the temperature reading registers will still reflect the current value of the temperature — not the ‘smoothed out’ value. ZN1E, ZN2E, and ZN3E enable temperature smoothing for zones 1, 2, and 3 respectively. ZN1-2, ZN1-1, and ZN1-0 control smoothing time for Zone 1. ZN2-2, ZN2-1, and ZN2-0 control smoothing time for Zone 2. ZN3-2, ZN3-1, and ZN3-0 control smoothing time for Zone 3. These registers become ready only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect. LM85 www.national.com19

TABLE 7. Spike Smoothing TABLE 8. PWM Output Below Limit Depending on Value of Off/Min

0 At 0% duty below LIMIT

1 At Min PWM Duty below LIMIT

4.17 Registers 64-66h: Minimum PWM Duty Cycle

Temperature LIMIT register setting. is cleared even though modifications to this register are possible. FIGURE 2. What LM85 Auto Fan Control Sees With and Without Spike Smoothing

TABLE 9. PWM Duty vs Register Setting

4.18 Registers 67-69h: Temperature Limit

is cleared even though modifications to this register are possible. TABLE 10. Temperature Limit vs Register Setting

4.19 Registers 6A-6Ch: Absolute Temperature Limit

PWM output associated with the Absolute Temperature Limit will go to 100%. Start bit is cleared even though modifications to these registers are possible. TABLE 11. Absolute Limit vs Register Setting

4.20 Registers 6D-6Eh: Zone Hysteresis Registers

– The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit. – The Hysteresis registers control this amount. See below table for details. Start bit is cleared even though modifications to this register are possible. TABLE 12. Hysteresis Settings

TABLE 12. Hysteresis Settings (Continued)

4.21 Register 6Fh: Test Register

part out of XOR tree test mode. is cleared even though modifications to this register are possible.

4.22 Registers 70-7Fh: Vendor Specific Registers

These registers are for vendor specific features, including test registers. They will not default to a specific value on power up.

4.22.1 Register 74h: Tachometer Monitor Mode

PWM1 output must control the fan that has it’s tachometer output connected to the TACH1 LM85 input. PWM2 output must control the fan that has it’s tachometer output connected to the TACH2 LM85 input. PWM3 output must control the fans that have their tachometer outputs connected to the TACH3 or TACH4 LM85 inputs. report a false RPM reading when under minimum detectable RPM as shown in the follwing table. reading as shown in the following table. reading as shown in the following table.

Functional Description (Continued) 23.14 1944 420 30.04 2523 420 38.16 3205 420 47.06 3953 420 61.38 5156 420 94.12 7906 420 This register is not effected when the Ready/Lock/Start/Override register Lock bit is set. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.

4.22.2 Register 75h: Fan Spin-up Mode

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value Lock? 75h R/W Fan Spin-up Mode RES RES RES RES RES PWM3 SU PWM2 SU PWM1 SU 7h U The PWM SU bit configures the PWM spin-up mode. If PWM SU is cleared the spin-up time will terminate after time programmed by the Fan Configuration register has elapsed. When set to a 1, the spin-up time will terminate early if the TACH reading exceeds the Tach Minimum value or after the time programmed by the Fan Configuration register has elapsed, whichever occurs first. This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.

4.23 Undefined Registers

Any reads to undefined registers will always return 00h. Writes to undefined registers will have no effect and will not return an error.

5.0 XOR TEST MODE

The LM85 incorporates a XOR tree test mode. When the test mode is enabled by setting the “XEN” bit high in the Test Register at address 6Fh via the SMBus, the part will enter XOR test mode. Since the test mode an XOR tree, the order of the signals in the tree is not important. SMBDAT and SMBCLK are not to be included in the test tree. 20035308

6.0 DIFFERENCES BETWEEN THE LM85BIMQ AND LM85CIMQ

It is highly recommended that new designs use the LM85BIMQ . Item No. Description LM85CIMQ LM85BIMQ 1 Voltage Monitoring Accuracy +3.5% to −0.5% of Full Scale ±2% of Full Scale 2 PWM Output logic LOW loading 3mA at 0.4V 8mA at 0.4V

3 LSB and MSB Fan TACH value

registers (registers 28h, 29h; 2Ah, 2Bh; 2Ch, 2Dh; 2Eh, 2Fh) Tach value registers must be read LSB followed by MSB. Reading the LSB latches the MSB. For example: if you read the LSB then the MSB, subsequent reads of just the MSB register will yield the old result. Internally, the TACH result is being updated but there is no read access unless the LSB register is read before an MSB. Tach value registers must be read LSB followed by MSB. Reading the LSB latches the MSB until read. After the MSB is read it will be updated with a new value, without requiring a read of the LSB register. LM85 www.national.com 24

Functional Description (Continued) Item No. Description LM85CIMQ LM85BIMQ

4 Overide bit (register 40h bit 3)

function with disabled PWM output (Fan configuration registers 5Ch-5Eh, bits fan_config[7:5]=ZON[2:0]=100 The override bit has no effect when the PWM output is disabled. The overide bit has precedance over all of the PWM output dissable bits. Therefore, if a PWM output is dissabled, setting the override bit will set the PWM output to 100%.

5 Auto Fan mode and Absolute

Temperature Limit function Only the PWM output associated with the zone that has exceeded its Absolute Limit will increase to 100%. When one zone exceeds its Absolute Limit all PWM outputs wil increase to 100%.

6 Register 3Fh Device ID default 60h 62h

Revision History

8/2002 Added LM85BIMQ functional differences and specifications. 3/2003 Updated Register 74h, Tachometer Monitor Mode description. LM85 www.national.com25

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Molded QSOP Package, Order Number LM85BIMQ, LM86BIMQX, LM85CIMQ or LM85CIMQX LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Fax: +65-6250 4466 Email: ap.support@nsc.com Tel: +65-6254 4466 National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LM85 Hardware Monitor with Integrated Fan Control National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.