LM833 TI | Alldatasheet
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Technical content
12 V / 1 W/cb1VEE
47 µF0.1 µF 750 /c0d +V CC 0.1 µF47 µF 1000 /c0d 10 k/c0d 0.0022 µF 2.7 k/c0d 0.001 µF 2.7 k/c0d VCC+OUT1 IN1/cb1OUT2 IN2/cb1 IN2+ IN1+ VCC /cb1 47 k/c0d 1 µF Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LM833 SLOS481B –JULY 2010–REVISED OCTOBER 2014 LM833DualHigh-SpeedAudioOperationalAmplifier
1 Features 3 Description
The LM833 device is a dual operational amplifier with 1• Dual-Supply Operation: ±5 V to ±18 V high-performance specifications for use in quality• Low Noise Voltage: 4.5 nV/√Hz audio and data-signal applications. Dual amplifiers
- Low Input Offset Voltage: 0.15 mV are utilized widely in audio circuits optimized for all preamp and high level stages in PCM and HiFi• Low Total Harmonic Distortion: 0.002% systems. The LM833 device is pin-for-pin compatible• High Slew Rate: 7 V/μs with industry-standard dual operation amplifiers. With• High-Gain Bandwidth Product: 16 MHz addition of a preamplifier, the gain of the power stage can be greatly reduced to improve performance.• High Open-Loop AC Gain: 800 at 20 kHz
- Large Output-Voltage Swing: –14.6 V to 14.1 V Device Information• Excellent Gain and Phase Margins PART NUMBER PACKAGE BODY SIZE (NOM)
- Available in 8-Terminal MSOP Package SOIC (8) 4.90 mm × 3.91 mm (3.0 mm x 4.9 mm x 0.65 mm) LM833 VSSOP (8) 3.00 mm × 3.00 mm PDIP (8) 9.81 mm × 6.35 mm2 Applications
- HiFi Audio System Equipment
- Preamplification and Filtering
- Set-Top Box
- Microphone Preamplifier Circuit
- General-Purpose Amplifier Applications
4 Typical Design Example Audio Pre-Amplifier
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLOS481B –JULY 2010–REVISED OCTOBER 2014 www.ti.com Table of Contents
5 Revision History
Changes from Revision A (August 2010) to Revision B Page
- Added Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, Changes from Original (July 2010) to Revision A Page
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IN2– OUT2 VCC+ VCC– IN1+ IN1– OUT1 D (SOIC), DGK (MSOP), OR P (PDIP) PACKAGE (TOP VIEW) LM833 www.ti.com SLOS481B –JULY 2010–REVISED OCTOBER 2014
6 Pin Configuration and Functions
NAME NO. IN1+ 3 Input Noninverting input IN1– 2 Input Inverting Input IN2+ 5 Input Noninverting input IN2- 6 Input Inverting Input OUT1 1 Output Output 1 OUT2 7 Output Output 2 VCC+ 8 — Positive Supply VCC– 4 — Negative Supply Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM833
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC+ Supply voltage(2) 18 V VCC– Supply voltage(2) –18 V VCC+ – VCC– Supply voltage 36 V Input voltage, either input(2)(3) VCC– VCC+ V Input current(4) ±10 mA Duration of output short circuit(5) Unlimited TJ Operating virtual junction temperature 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. (3) The magnitude of the input voltage must never exceed the magnitude of the supply voltage. (4) Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless some limiting resistance is used. (5) The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the maximum dissipation rating is not exceeded.
7.2 Handling Ratings
PARAMETER DEFINITION MIN MAX UNIT Tstg Storage temperature range –65 150 °C Human-Body Model (HBM)(1) 0 2.5 V(ESD) kV Charged-Device Model (CDM)(2) 0 1.5 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC– –5 –18 Supply voltage V VCC+ 5 18 TA Operating free-air temperature range –40 85 °C
7.4 Thermal Information
THERMAL METRIC(1) D DGK P UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance(2)(3) 97 172 85 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). (2) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (3) The package thermal impedance is calculated in accordance with JESD 51-7.
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7.5 Electrical Characteristics
VCC– = –15 V, VCC+ = 15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25°C 0.15 2 VIO Input offset voltage VO = 0, RS = 10 Ω, VCM = 0 mV TA = –40°C to 85°C 3 Input offset voltageαVIO VO = 0, RS = 10 Ω, VCM = 0 TA = –40°C to 85°C 2 μV/°Ctemperature coefficient TA = 25°C 300 750 IIB Input bias current VO = 0, VCM = 0 nA TA = –40°C to 85°C 800 TA = 25°C 25 150 IIO Input offset current VO = 0, VCM = 0 nA TA = –40°C to 85°C 175 Common-mode input voltageVICR ΔVIO = 5 mV, VO = 0 ±13 ±14 Vrange TA = 25°C 90 110Large-signal differentialAVD RL ≥ 2 kΩ, VO = ±10 V dBvoltage amplification TA = –40°C to 85°C 85 VOM+ 10.7 RL = 600 Ω VOM– –11.9 VOM+ 13.2 13.8Maximum output voltageVOM VID = ±1 V RL = 2000 Ω Vswing VOM– –13.2 –13.7 VOM+ 13.5 14.1 RL = 10,000 Ω VOM– –14 –14.6 CMMR Common-mode rejection ratio VIN = ±13 V 80 100 dB kSVR (1) Supply-voltage rejection ratio VCC+ = 5 V to 15 V, VCC– = –5 V to –15 V 80 105 dB Source current 15 29 IOS Output short-circuit current |VID| = 1 V, Output to GND mA Sink current –20 –37 TA = 25°C 2.05 2.5 ICC Supply current (per channel) VO = 0 mA TA = –40°C to 85°C 2.75 (1) Measured with VCC± differentially varied at the same time
7.6 Operating Characteristics
VCC– = –15 V, VCC+ = 15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate at unity gain AVD = 1, VIN = –10 V to 10 V, RL = 2 kΩ, CL = 100 pF 5 7 V/μs GBW Gain bandwidth product f = 100 kHz 10 16 MHz B1 Unity gain frequency Open loop 9 MHz CL = 0 pF –11 Gm Gain margin RL = 2 kΩ dB CL = 100 pF –6 CL = 0 pF 55 Φm Phase margin RL = 2 kΩ degrees CL = 100 pF 40 Amp-to-amp isolation f = 20 Hz to 20 kHz –120 dB Power bandwidth VO = 27 V(PP), RL = 2 kΩ, THD ≤ 1% 120 kHz THD Total harmonic distortion VO = 3 Vrms, AVD = 1, RL = 2 kΩ, f = 20 Hz to 20 kHz 0.002% zo Open-loop output impedance VO = 0, f = 9 MHz 37 Ω rid Differential input resistance VCM = 0 175 kΩ Cid Differential input capacitance VCM = 0 12 pF Vn Equivalent input noise voltage f = 1 kHz, RS = 100 Ω 4.5 nV/√Hz In Equivalent input noise current f = 1 kHz 0.5 pA/√Hz Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM833
NOTE: All capacitors are non-polarized.
7.7 Typical Characteristics
Figure 1. Voltage Noise Test Circuit (0.1 Hz to 10 Hz) Figure 2. Input Bias Current vs Common-Mode Voltage Figure 3. Input Bias Current vs Supply Voltage
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Figure 10. Output Short-Circuit Current vs Temperature Figure 11. Supply Current vs Temperature Figure 12. CMRR vs Frequency Figure 13. PSSR vs Frequency Figure 14. Gain Bandwidth Product vs Supply Voltage Figure 15. Gain Bandwidth Product vs Temperature
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Figure 22. Total Harmonic Distortion vs Frequency Figure 23. Total Harmonic Distortion vs Output Voltage Figure 24. Slew Rate vs Supply Voltage Figure 25. Slew Rate vs Temperature Figure 26. Gain and Phase vs Frequency Figure 27. Gain and Phase Margin
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Figure 35. Low-Frequency NoiseFigure 34. Small Signal Transient Response
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8 Detailed Description
8.1 Overview
The LM833 device is a dual operational amplifier with high-performance specifications for use in quality audio and data-signal applications. This device operates over a wide range of single- and dual-supply voltage with low noise, high-gain bandwidth, and high slew rate. Additional features include low total harmonic distortion, excellent phase and gain margins, large output voltage swing with no deadband crossover distortions, and symmetrical sink/source performance. The dual amplifiers are utilized widely in circuit of audio optimized for all preamp and high-level stages in PCM and HiFi systems. The LM833 device is pin-for-pin compatible with industry-standard dual operation amplifiers' pin assignments. With addition of a preamplifier, the gain of the power stage can be greatly reduced to improve performance.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Operating Voltage
The LM833 operational amplifier is fully specified and ensured for operation from ±5 V to ±18 V. In addition, many specifications apply from –40°C to 85°C. Parameters that vary significantly with operating voltages or temperature are shown in Absolute Maximum Ratings .
8.3.2 High Gain Bandwidth Product
Gain bandwidth product is found by multiplying the measured bandwidth of an amplifier by the gain at which that bandwidth was measured. The LM833 has a high gain bandwidth of 16 MHz which stays relatively stable over a wide range of supply voltages. Parameters that vary significantly with temperature are shown in Figure 14.
8.3.3 Low Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. The LM833 has a very low THD of 0.002% meaning that the LM833 will add little harmonic distortion when used in audio signal applications. More specific characteristics are shown in Figure 22.
8.4 Device Functional Modes
The LM833 is powered on when the supply is connected. It can be operated as a single supply operational amplifier or dual supply amplifier depending on the application.
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15 V½ LM833
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 36. RIAA Phono Preamplifier
9.2.1 Design Requirements
- Supply Voltage = ±15 V
- Low-Frequency −3 dB corner of the first amplifier (f0) > 20 Hz (below audible range)
- Low-Frequency −3 dB corner of the second stage (fL) = 20.2 Hz
9.2.2 Detailed Design Procedure
9.2.2.1 Introduction to Design Method
Equation 1 through Equation 5 show the design equations for the preamplifier.
- A1 is the 1 kHz voltage gain of the first amplifier (1) Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LM833
3.18 10Example : C 0.03946 F 8.058 10 /c45/c180/c61 /c61 /c109 /c180 3.18 10Calculate C R /c45/c180/c61 0 0 1C 2 f R/c187 /c112 V 2 RA 1 R/c61 /c43 /c40 /c414 L 1C 2 f R3 R6/c61 /c112 /c43 5 3 6 3 6 P (R R ) 7.5 10C 7.5 10 R R R /c45 /c45 /c43 /c180/c61 /c180 /c61 2 0 RR R 9/c61 /c45 3.18 10C R /c45/c180/c61 LM833 SLOS481B –JULY 2010–REVISED OCTOBER 2014 www.ti.com Typical Application (continued) (2) (3) (4) where
- fL is the low-frequency −3 dB corner of the second stage (5) For standard RIAA preamplifiers, fL should be kept well below the audible frequency range. If the preamplifier is to follow the IEC recommendation (IEC Publication 98, Amendment #4), fL should equal 20.2 Hz. where
- AV2 is the voltage gain of the second amplifier (6) where
- f0 is the low-frequency −3 dB corner of the first amplifier (7) This should be kept well below the audible frequency range. A design procedure is shown below with an illustrative example using 1% tolerance E96 components for close conformance to the ideal RIAA curve. Because 1% tolerance capacitors are often difficult to find except in 5% or 10% standard values, the design procedure calls for re-calculation of a few component values so that standard capacitor values can be used.
9.2.2.2 RIAA Phono Preamplifier Design Procedure
A design procedure is shown below with an illustrative example using 1% tolerance E96 components for close conformance to the ideal RIAA curve. Since 1% tolerance capacitors are often difficult to find except in 5% or 10% standard values, the design procedure calls for re-calculation of a few component values so that standard capacitor values can be used. Choose R0. R0 should be small for minimum noise contribution, but not so small that the feedback network excessively loads the amplifier. Example: Choose R0 = 500 Choose 1 kHz gain, AV1 of first amplifier. This will typically be around 20 dB to 30 dB. Example: Choose AV1 = 26 dB = 20 Calculate R1 = 8.058 R0AV1 Example: R1 = 8.058 × 500 × 20 = 80.58 k (8) (9) If C1 is not a convenient value, choose the nearest convenient value and calculate a new R1 from Equation 10.
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P P 8 7.5 10Calculate R C 7.5 10Example: R 2.273 k 3.3 10 /c45 /c45 /c45 /c180/c61 /c180/c61 /c61 /c180 2 0 RCalculate R R 9 8.06 10Example : R 499 8456.569 /c61 /c45 /c180/c61 /c45 /c61 8.06 10Example: New R 498.88.058 20 /c180/c61 /c61 /c180 RR 8.058 A/c61 1 8 3.18 10New R 81.54 k 3.9 10 Use R 80.6 k /c45 /c45 /c180/c61 /c61 /c180 /c61 3.18 10R C /c45/c180/c61 LM833 www.ti.com SLOS481B –JULY 2010–REVISED OCTOBER 2014 Typical Application (continued) (10) Example: New C1 = 0.039 μF. (11) Calculate a new value for R0 from Equation 12. (12) (13) Use R0 = 499. (14) Use R2 = 8.45 K. Choose a convenient value for C3 in the range from 0.01 μF to 0.05 μF. Example: C3 = 0.033 μF (15) Choose a standard value for R3 that is slightly larger than RP. Example: R3 = 2.37 k Calculate R6 from 1 / R6 = 1 / RP − 1 / R3 Example: R6 = 55.36 k Use 54.9 k Calculate C4 for low-frequency rolloff below 1 Hz from design Equation 5. Example: C4 = 2 μF. Use a good quality mylar, polystyrene, or polypropylene. Choose gain of second amplifier. Example: The 1 kHz gain up to the input of the second amplifier is about 26 dB for this example. For an overall 1 kHz gain equal to about 36 dB we choose: AV2 = 10 dB = 3.16 Choose value for R4. Example: R4 = 2 k Calculate R5 = (AV2 − 1) R4 Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LM833
Calculate C0 for low-frequency rolloff below 1 Hz from design Equation 7.
9.2.3 Application Curves for Output Characteristics
The maximum observed error for the prototype was 0.1 dB. Figure 37. Deviation from Ideal RIAA Response for The lower curve is for an output level of 300 mVrms and the upper curve is for an output level of 1 Vrms. Figure 38. THD of Circuit in Figure 36 as a Function of Frequency
9.3 Typical Application — Reducing Oscillation from High-Capacitive Loads
capacitance, adding a small resistance in series with the load should alleviate the problem (see Figure 39).
9.3.1 Test Schematic
Figure 39. Capacitive Load Testing Circuit
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0.25 V per Division
9.3.2 Output Characteristics
Figure 40. Pulse Response Figure 41. Pulse Response Figure 42. Pulse Response Figure 44. Pulse Response
10 Power Supply Recommendations
operating voltage or temperature.
11 Layout
11.1 Layout Guidelines
- Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
- Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, (SLOA089).
- To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
- Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Example.
- Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
- Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Figure 46. Operational Amplifier Schematic for Noninverting Configuration
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Figure 47. Operational Amplifier Board Layout for Noninverting Configuration
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: LM833
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM833D Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 LM833 LM833DGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 85 RSU LM833DGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RSU LM833DGKT Obsolete Production VSSOP (DGK) | 8 - - Call TI Call TI -40 to 85 RSU LM833DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LM833 LM833DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LM833 LM833P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 LM833P LM833P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 LM833P (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
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PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM833DGKR VSSOP DGK 8 2500 353.0 353.0 32.0 LM833DR SOIC D 8 2500 356.0 356.0 35.0 LM833DR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM833P P PDIP 8 50 506 13.97 11230 4.32 LM833P.A P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM
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