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LM8333FLQ8Y/NOPB

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Mobile I/O Companion Supporting Key-Scan, I/O Expansion, PWM and ACCESS.bus Host Interface

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 LM8333MobileI/OCompanionSupportingKey-Scan,I/OExpansion,PWM,and ACCESS.busHostInterface Check forSamples: LM8333 1FEATURES DESCRIPTION The LM8333 Mobile I/O Companion offloadsthe 2• 8 × 8 Standard Keys burden of keyboard scanningfrom the host,while• 8 SpecialFunctionKeys (SF Keys) Providinga providingextremelylow power consumptionin bothTotalof72 Keys fortheMaximum Keyboard operationaland standbymodes. Itsupportskeypad Matrix matricesup to8 × 8 insize(plusanother8 special- functionkeys),for portableapplicationssuch as• ACCESS.Bus (I2C-compatible)Communication cellphones,PDAs, games, and other handheldInterfacetotheHost applications.• Four GeneralPurpose Host Programmable I/O Pins withTwo Optional(Slow)External Key press and releaseevents are encoded intoa byteformatand loadedintoa FIFO bufferforretrievalInterrupts by the host processor.An interruptoutput(IRQ) is• 15-byteFIFO BuffertoStoreKey Pressed and used tosignaleventssuch as keypad activity,a stateKey Released Events change on eitherof two interrupt-capablegeneral-

ErrorControlwithErrorReports on (FIFO purposeI/Opins,or an errorcondition.Interruptand Overrun,Keypad Overrun,InvalidCommand) errorcodes are availableto the host by reading dedicatedregisters.• Host Programmable PWM
Host Programmable ActiveTime and Four general-purposeI/O pinsare available,two of which have interruptcapability.A pulse-widthDebounce Time modulated outputbased on a host-programmable internaltimerisalsoavailable,whichcan be used asAPPLICATIONS a general-purposeoutputifthe PWM functionisnot• MobilePhones required.
PersonalDigitalAssistants(PDAs) To minimizepower,theLM8333 automaticallyenters
Smart Handheld Devices a low-powerstandbymode when thereisno keypad, I/O,orhostactivity.• PersonalMedia Players The deviceispackaged in a 32–pin WQFN and a 49-pincsBGA. Botharechip-scalepackages. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com Block Diagram Pin Assignments Figure1. 32-Lead WQFN (Top View) See Package Number NJE0032A

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 Figure2. 49-BallcsBGA (Top View) See Package Number NYC0049A Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM8333

SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com SIGNAL DESCRIPTIONS Name 32 Pins 49 Pins I/O Description WAKE_IN0 29 D7 Input Wake-up input/Keyboardscanninginput0 WAKE_IN1 30 C7 Input Wake-up input/Keyboardscanninginput1 WAKE_IN2 27 E7 Input Wake-up input/Keyboardscanninginput2 WAKE_IN3 28 D6 Input Wake-up input/Keyboardscanninginput3 WAKE_IN4 31 B6 Input Wake-up input/Keyboardscanninginput4 WAKE_IN5 32 A7 Input Wake-up input/Keyboardscanninginput5 WAKE_IN6 1 A6 Input Wake-up input/Keyboardscanninginput6 WAKE_IN7 2 B5 Input Wake-up input/Keyboardscanninginput7 K_OUT0 21 G3 Output Keyboardscanningoutput0 K_OUT1 22 F4 Output Keyboardscanningoutput1 K_OUT2 23 G4 Output Keyboardscanningoutput2 K_OUT3 24 G5 Output Keyboardscanningoutput3 K_OUT4 3 A5 Output Keyboardscanningoutput4 K_OUT5 4 B4 Output Keyboardscanningoutput5 K_OUT6 5 A4 Output Keyboardscanningoutput6 K_OUT7 6 A3 Output Keyboardscanningoutput7 GEN_IO_0 12 D2 I/O General-purposeI/O0 GEN_IO_1 13 D1 I/O General-purposeI/O1 GEN_IO_2 7 B3 I/O General-purposeI/O2 GEN_IO_3 8 A2 I/O General-purposeI/O3 SDA 25 F7 I/O ACCESS.bus datasignal SCL 26 E6 Input ACCESS.bus clocksignal IRQ 17 F2 Output Interruptrequestoutput PWM 16 F1 Output Pulse-widthmodulatedoutput WD_OUT 18 G1 Output Watchdog timeroutput(connecttoRESET input) RESET 20 F3 Input Resetinput CLK_IN 11 B1 Input Clockinput(connecttogroundthrougha 68k ohm resistor) VCC 15 E1,E2 n.a. Vcc GND 9,10,14 A1,B2,C3, n.a. Ground C4, C5, D3, D4, D5, E3, E4,E5 NC 19 B7,C1, C2, n.a. No connect C6, F5,F6, G2, G6, G7

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 TypicalApplication Figure3. TypicalKeypad Configuration

FEATURES

The followingfeaturesaresupported:

8 x 8 StandardKeys.
8 SpecialFunctionKeys (SF keys)withWake-Up Capabilityby Forcinga WAKE_INx PintoGround.Pressing a SF Key Overridesany otherKey intheSame Row.
A Totalof72 Keys can be Scanned.
ACCESS.Bus (I2C-Compatible)InterfaceforCommunicationwiththeHost.
The Watchdog TimerisMandatory,so WD_OUT Must be ConnectedtoRESET. I/OEXPANSION OPTIONS
One Host-ProgrammablePWM Outputwhichalsomay be Used as a General-PurposeOutput.
Four Host-ProgrammableGeneral-PurposeI/O Pins,GEN_IO_0, GEN_IO_1, GEN_IO_2, and GEN_IO_3. GEN_IO_0 and GEN_IO_1 can alsobe Configuredfor“Slow”Interrupts,inwhichany TransitionwillTriggera Hardware InterruptEventtotheHost. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM8333

SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com WATCHDOG TIMER The watchdog timerisalways enabled in hardware.To use the timer,connectthe WD_OUT outputto the RESET input. HALT MODE The fullystaticarchitectureoftheLM8333 allowsstoppingtheinternalRC clockinHaltmode, which reduces power consumptiontotheminimum level. Haltmode isenteredwhen no key-press,key-release,orACCESS.bus activityisdetectedfora certainperiodof time(bydefault,500 milliseconds).The mechanism forenteringHaltmode isalwaysenabledinhardware,but thehostcan programtheperiodofinactivitywhichtriggersentryintoHaltmode. The LM8333 willremaininActivemode as longas a key event,orany otherevent,whichcauses theIRQ output tobe assertedisnotresolved. ACCESS.bus Activity When theLM8333 isinHaltmode, any activityon theACCESS.bus interfacewillcause theLM8333 toexitfrom Haltmode. However,theLM8333 willnotbe abletoacknowledgethefirstbus cycleimmediatelyfollowingwake- up fromHaltmode. Itwillrespondwitha negativeacknowledgement,and thehostshouldthenrepeatthecycle. The LM8333 willbe preventedfromenteringHaltmode ifitsharesthebus withperipheralsthatarecontinuously active.For lowestpower consumption,theLM8333 shouldonlysharethebus withperipheralsthatrequirelittle orno bus activityaftersysteminitialization. KEYPAD SCANNING The LM8333 startsnew scanningcyclesat fixedtimeintervalsof about 4 ms. Ifa change inthe stateof the keypad isdetected,thekeypad isrescannedaftera debounce delay.When thestatechange has been reliably captured,itisencoded and writtentotheFIFO buffer. Ifmore thantwo keys are pressedsimultaneously,thepatternofkey closuresmay be ambiguous,so pressing more thantwo keys assertstheErrorFlagconditionand theIRQ output(ifenabled).The hostmay attemptto interprettheeventsstoredintheFIFO ordiscardthem. The SF keys connecttheWAKE_INx pinsdirectlytoground.There can be up toeightSF-keys.Ifany ofthese keysarepressed,otherkey pressesthatuse thesame WAKE_INx pinwillbe ignored. COMMUNICATION INTERFACE The two-wireACCESS.bus interfaceisused to communicate witha host.The ACCESS.bus interfaceisfully compliantwiththeI2Cbus standard.The LM8333 operatesas a bus slaveatspeeds up to400 kHz. An ACCESS.bus transferstartswitha bytethatincludesa 7-bitslavedeviceaddress.The LM8333 respondsto a fixeddeviceaddress.Thisaddressis0xA2,when alignedtotheMSB (7-bitaddressmapped tobits7:1,rather thanbits6:0).Bit0 isa directionbit(0on write,1 on read). Because itisa slave,theLM8333 neverinitiatesan ACCESS.bus cycle,itonlyrespondstobus cyclesinitiated by thehost.The LM8333 may signaleventstothehostby assertingtheIRQ interruptrequest. InterruptsBetween theHost and LM8333 The IRQ outputisused tosignalunresolvedinterrupts,errors,and key-eventstothehost. The hostcan use an availableGEN_IO_0 or GEN_IO_1 pinto interrupt(orwake-up)the LM8333, ifitisnot beingused foranotherfunction.The hostcan alsowake-up the LM8333 by sendinga StartConditionon the ACCESS.bus interface. NOTE The LM8333 itwillnotbe abletoacknowledgethefirstbytereceivedfrom thehostafter wake-up.Inthiscase,thehostwillhave toresendtheslaveaddress.

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 InterruptSources The IRQ outputisassertedon theseconditions:

Any new key-event.
Any errorcondition,whichisindicatedby theerrorcode.
Any enabled interrupton eitherof the GEN_IO_0 or GEN_IO_1 pinsthatcan be configuredas external interruptinputs.When enabled,any risingorfallingedge triggersan interrupt. The IRQ outputremainsasserteduntiltheinterruptcode isread. Device Operation EVENT CODE ASSIGNMENT Afterpower-onreset,theLM8333 startsscanningthekeypad.Itstaysactivefora defaulttimeofabout500 ms afterthe lastkey isreleased,afterwhich itentersa standbymode to minimizepower consumption(<2 µA standbycurrent). Table 1 liststhe codes assignedto the matrixpositionsencoded by the hardware.Key-pressevents are assignedthe codes listedinTable 1, but withthe MSB set.When a key isreleased,the MSB of the code is clear. Table1.Keypad MatrixCode Assignments K_OUT0 K_OUT1 K_OUT2 K_OUT3 K_OUT4 K_OUT5 K_OUT6 K_OUT7 SF Keys WAKE_IN0 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 WAKE_IN1 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 WAKE_IN2 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 WAKE_IN3 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 WAKE_IN4 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 WAKE_IN5 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 WAKE_IN6 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 WAKE_IN7 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 The codes are loadedintothe FIFO bufferinthe orderinwhich theyoccurred.Table 2 shows an example sequence ofevents,and Figure4 shows theresultingsequence ofeventcodes loadedintotheFIFO buffer. Table2.Example Sequence ofEvents Event Number Event Code Event on Input MatrixNode Description 1 0xF1 Wake_INP7 K_OUT0 Key ispressed 2 0xB6 Wake_INP3 K_OUT5 Key ispressed 3 0x71 Wake_INP7 K_OUT0 Key isreleased 4 0x36 Wake_INP3 K_OUT5 Key isreleased 5 0xB4 Wake_INP3 K_OUT3 Key ispressed 6 0x34 Wake_INP3 K_OUT3 Key isreleased33 7 0x91 Wake_INP1 K_OUT0 Key ispressed 8 0x00 NA NA Indicatesend ofstoredevents Figure4. Example Event Codes Loaded inFIFO Buffer I/OEXPANSION Inadditiontokeypad scanning,theLM8333 supportsvariousI/Oexpansionoptions. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM8333

SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com PWM Output withProgrammable Duty Cycle The PWM pinmay be used eitheras a pulse-widthmodulatedoutputdrivenby a 16-bittimeror as a general- purposeoutputpin.InthePWM mode, thelow time(TLO )and hightime(THI)areprogrammablebetween 1 × tC and 65K × tC cyclesinwhich tC isthecycletime(nominally1 microsecond),as shown inFigure5.The period TPD isthe sum of THI and TLO . The PWM_LO command writesTLO , and the PWM_HI command writesTHI. Operationalmodes of the PWM pin are controlledby the PWM_CTL command. Beforeactivatingthe PWM output,theTLO and THI timesmust be initialized.Figure6 shows thecommand formats. Figure5. Programmable PWM Figure6. PWM ControlCommands forArbitraryDuty Cycle Table3.Summary ofPWM ControlBits OUT_DIR Bit PWM_DIR Bit MOD BIT Description 0 1 0 Driveoutputlow 1 1 0 Driveoutputhigh 0 0 0 TRI-STATE ® mode X X 1 PWM timeroutput General-PurposeI/O(GPIO) Figure7 shows the commands to write,read and controlthe general-purposeI/O portpins,GEN_IO_0, GEN_IO_1, GEN_IO_2, and GEN_IO_3. Allgeneral-purposeI/Opinscan be programmed as inputsoroutputsas shown inTable4.The GEN_IO_0 and GEN_IO_1 pinsprovidean additionalcapabilityforprogrammablewake-up.

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 Figure7. General-PurposeI/OControlCommands Table4 shows thepinconfigurationforallfourcombinationsofcontrolbitsettings(dataoutputand direction)for the general-purposeI/O pins.GEN_IO_3 cannot be put intothe high impedance (Hi-Z)inputmode. When programmed as an input,itcan onlybe configuredas an inputwitha weak pullup. Table4.GeneralPurpose I/OPin Configuration GEN_IO_DIR Bit GEN_IO_OUT Bit Direction State 0 0 Input Hi-Z 0 1 Input Weak Pullup 1 0 Output DriveLow 1 1 Output DriveHigh ExternalInterrupts When the GEN_IO_0 or GEN_IO_1 pinsare configuredas inputs,a SET_EXT_INT command (0xD1)can be used toenablereceivingexternalinterruptson eitherorbothofthesepins.SettingtheEX_0 orEX_1 bitsinthe databyteoftheSET_EXT_INT command (asshown inFigure8)enablesthecorrespondingpinas an external interruptinput.When enabled as an interruptinput,any risingor fallingedge causes the IRQ outputto be asserted.IftheLM8333 was inHaltmode, italsowakes up intoActivemode. Figure8. SET_EXT_INT Command Data Byte When both GEN_IO_0 and GEN_IO_1 are configuredas interruptinputs,bits1 and 2 of the interruptcode indicatewhichinputassertedtheinterrupt.However,ifonlyone ofGEN_IO_0 orGEN_IO_1 isconfiguredas an interruptinput,bothbits1 and 2 oftheinterruptcode willbe setwhen an interruptoccurs. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM8333

SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com Table5.InterfaceCommands forControllingtheLM8333 Function Cmd Dir Data Bits Data Description Read an eventfromtheFIFO. Maximum 14 eventcodes storedintheFIFO.EventCodes fromFIFO_READ 0x20 R 128 FIFO MSB = 1:key pressed. MSB = 0:key released. Repeatsa FIFO readwithoutadvancingtheFIFO pointer, forexample toretrya readafteran error. EventCodes from Maximum 14 eventcodes storedintheFIFO.RPT_FIFO_READ 0x21 R 128 FIFO MSB = 1:key pressed. MSB = 0:key released. Defaultis10 ms. Validrange1–255. DEBOUNCE 0x22 W 8 nnnn nnnn Time ~ n × 3 ms GEN_IO_IN 0x30 R 8 0000 nnnn Read portdata. Specifyportmode. (Drive0 or1 when theportisconfigured GEN_IO_OUT 0x31 W 8 0000 nnnn as an output;selectHi-Zorpullupwhen theportis configuredas an input.) GEN_IO_DIR 0x32 W 8 0000 nnnn Selectportdirection(inputoroutput). PWM_HI 0x40 W 16 (n+1)× tC SetsthelowpulsetimeofthePWM signal. PWM_LO 0x41 W 16 (n+1)× tC SetsthehighpulsetimeofthePWM signal. PWM_CTL 0x42 W 8 0000 0nnn Activate,reactivate,orstopPWM. Reads theinterruptcode,acknowledgestheinterrupt,READ_INT 0xD0 R 8 0000 nnnn deassertstheIRQ output,and clearsthecode. Enables/disablesexternalinterruptson GEN_IO_0 andSET_EXT_INT 0xD1 W 8 0000 00nn GEN_IO_1. READ_STAT 0xE0 R 8 000n nnnn StatusInformation. Requestsrescanningthekeypad (forexample,afteran errorSCAN_REQ 0xE3 W 8 was reported). Specifiesthetimeafterthelasteventduringwhichthe LM8333 staysactivebeforeenteringHaltmode. The active timemust be greaterthanthedebounce time.ACTIVE 0xE4 W 8 nnnn nnnn Defaultis500 msec Validrangeforn is1–255 Time ~ n × 3 msec. READ_ERROR 0xF0 R 8 0nnn nnnn Reads and clearstheerrorcode. HOST COMMAND EXECUTION Command Structure AllcommunicationwiththeLM8333 overtheACCESS.bus interfaceisinitiatedby thehost,usuallyinresponse toan interruptrequest(IRQ low)assertedby theLM8333. Figure9 shows a sequence ofStartconditions,slave addresses,READ_INT command (0xD0),acknowledge cycles,data bytes,and Stop conditionforreadingthe interruptcode.

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 Figure9. TypicalCommand Sequence from Host Everytransferisprecededby a Startcondition(S)ora Repeated Startcondition(RS).The latteroccurswhen a command followsimmediatelyupon anothercommand withoutan interveningStop condition(P).A Stop conditionindicatestheend oftransmission.Everybyteisacknowledged(A)by thereceiver. The firstbyteina writefrom thehosttotheLM8333 is0xA2, and thefirstbyteina read is0xA3. Thisbyteis composed ofa 7-bitslaveaddressinbits7:1and a directionbitinbit0.The directionbitis0 on writesfromthe hosttotheslaveand 1 on readsfromtheslavetothehost. The second bytesends the command. The commands are listedinTable 5. In the example,the READ_INT command (0xD0)readstheinterruptcode. The slaveaddressisrepeatedinthe thirdbyte,withthe directionbitsetto 1. The Start(orRepeated Start) conditionmust be repeatedwhenever theslaveaddressorthedirectionbitischanged.Inthiscase,thedirection bitischanged. The data issent from the slaveto the host in the fourthbyte.When the master isthe receiver,itsends a negativeacknowledgement(NA)toindicatetheend ofthedata. HOST WRITE COMMANDS Some hostcommands includeone ormore databyteswrittentotheLM8333. Figure10 shows a SET_EXT_INT command, whichconsistsofan addressbyte,a command byte,and one databyte. The firstbyteiscomposed ofa 7-bitslaveaddressinbits7:1and a directionbitinbit0.The stateofthedirection bitis0 on writesfromthehosttotheslaveand 1 on readsfromtheslavetothehost. The second bytesends thecommand. The commands are listedinFigure11.The SET_EXT_INT command is 0xD1. The thirdbytesend thedata,inthiscase configuringGEN_IO_0 as an externalinterruptinput. Figure10. Host WriteCommand HOST READ COMMANDS NOTE: AllNSIDs performas describedinthissection.NSID LM8333GGR8AXS isan enhanced versionwhich alsoallowstheuse ofa STOP START sequence inadditiontotheREPEATED_START sequence describedin thissection. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM8333

SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com Some hostcommands includeone or more databytesread from theLM8333. Figure11 shows a READ_INT command whichconsistsofan addressbyte,a command byte,a second addressbyte,and a databyte. The firstaddressbyteissentwiththedirectionbitdrivenlow toindicatea writetransactionofthecommand to the LM8333. The second addressbyteissentwiththe directionbitundriven(pulledhigh)to indicatea read transactionofthedatafromtheLM8333. The Repeated Startconditionmust be repeatedwhenever theslaveaddressor thedirectionbitischanged.In thiscase,thedirectionbitischanged. The dataissentfromtheslavetothehostinthefourthbyte.Thisbyteends witha negativeacknowledgement (NACK) toindicatetheend ofthedata. Figure11. Host Read Command WAKE-UP FROM HALT MODE Any bus transactioninitiatedby thehostmay encountertheLM8333 deviceinHaltmode orbusy withprocessing data,such as controllingtheFIFO bufferorexecutinginterruptserviceroutines. Figure12 shows thecase inwhichthehostsends a command whiletheLM8333 isinHaltmode (CPU clockis stopped).Any activityon theACCESS.bus wakes up theLM8333, butitcannotacknowledgethefirstbus cycle immediatelyafterwake-up. The hostdrivesa Startconditionfollowedby seven addressbitsand a R/W bit.The hostthenreleasesSDA for one clockperiod,so thatitcan be drivenby theLM8333. IftheLM8333 does notdriveSDA low duringthehighphase oftheclockperiodimmediatelyaftertheR/W bit, thebus cycleterminateswithoutbeingacknowledged(shown as NACK inFigure12).The hostthenabortsthe transactionby sendinga Stop condition.Afterabortingthebus cycle,thehostmay thenretrythebus cycle.On the second attempt,the LM8333 willbe ableto acknowledge the slaveaddress,because itwillbe inActive mode. Alternatively,theI2C specificationallowssendinga START byte(00000001),whichwillnotbe acknowledgedby any device.Thisbytecan be used towake up theLM8333 fromHaltmode. The LM8333 may alsostallthebus transactionby pullingtheSCL low,whichisa validbehaviordefinedby the I2C specification.

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 Figure12. LM8333 Responds withNACK, Host RetriesCommand Interrupts INTERRUPT CODE The interruptcode isread and acknowledgedwiththeREAD_INT command (0xD0).Thiscommand clearsthe code and deassertstheIRQ output.Table6 shows theformatoftheinterruptcode. Note thatwhen onlyone of the interrupt-capablepinsGEN_IO_0 or GEN_IO_1 isconfiguredas an interrupt input,bits1 and 2 are both set when an interruptoccurs.When both GEN_IO_0 and GEN_IO_1 pinsare configuredas interruptinputs,onlyone bitcorrespondingtotheinterruptsourceissetwhen an interruptoccurs. Table6.InterruptCode 7 6 5 4 3 2 1 0 0 0 0 0 ERROR EX_1 EX_0 KEYPAD Bit Description ERROR An errorconditionoccurred. EX_1 A risingorfallingedge was detectedon GEN_IO_1. EX_0 A risingorfallingedge was detectedon GEN_IO_0. KEYPAD A key-pressorkey-releaseeventoccurred. ERROR CODE IftheLM8333 reportsan error,theREAD_ERROR command (0xF0)isused toread and cleartheerrorcode. Table7 shows theformatoftheerrorcode. Table7.ErrorCode 7 6 5 4 3 2 1 0

0 FIFOOVR 0 NOINT 0 KEYOVR CMDUNK CMDOVR

FIFOOVR Key eventoccurredwhiletheFIFO was full. NOINT Interruptdeassertedbeforeitcouldbe serviced. KEYOVR More thantwo keyswere pressedsimultaneously. CMDUNK Not a validcommand. CMDOVR Command receivedbeforeitcouldbe accepted,e.g.afterwake-up. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM8333

SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com STATUS CODES The hostcan use theREAD_STAT command (0xE0)toread thestatuscode,forexample tosynchronizeafter an error. Table8.StatusCodes Status Code Description Reset 0000 0000 Defaultafterreset. Wake Up Interrupt 0000 0010 Wake-up caused by externalinterrupt. Ack 0000 0110 Lasthostcommand was successful. NoAck 0001 0101 Lasthostcommand was notsuccessful. INTERRUPT PROCESSING Unexpectedstatesencounteredduringrun-time,forexample overrunoftheFIFO buffer,arereportedas errors. When thehostreceivesan interruptfromtheLM8333, ituses a READ_INT command toreadtheinterruptcode. Ifthe code has a setERROR bit,the hostthen uses a READ_ERROR command to read the errorcode,as shown inFigure13.

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SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com COMMAND EXECUTION SUMMARY

With the interrupt,status,and errorcodes,the LM8333 providesthe featuresneeded to supporta reliable key-scanfunctionality.
Up to14 key-scaneventscan be storedinan internalFIFO buffer.The end ofbufferisindicatedwiththe00 (emptycharacter)code.
The host can repeatedlyread the FIFO withoutmodifyingthe FIFO pointerusingthe RPT_FIFO_READ command (0x21),forexample ifan errorisencounteredduringa read.
The LM8333 assertstheIRQ outputlowwhen a new characterispressedafterthelastinterruptacknowledge fromthehost.The IRQ outputwillbe deassertedafterthehosthas acknowledgedtheinterruptby readingthe interruptcode usingtheREAD_INT command (0xD0).
The host can synchronizewiththe LM8333 by readingthe statuscode withthe READ_STAT command (0xE0).The statuscode verifieswhetherthelastcommand was successfullycompleted.
Two GPIO pinson theLM8333 may be configuredas externalinterruptinputs.A risingorfallingedge on an enabledinterruptinputtriggerswake-up from Haltmode and assertsan interrupttothehostby pullingthe IRQ outputlow.
The host can change the debounce time from the defaulttime of 10 ms. This can be used forreliable scanningofkeyboardswithnoisycontacts.The debounce timecan be settoabout1 second instepsof4 milliseconds.The debounce timeissetwiththeDEBOUNCE command (0x22).
The hostcan change theactivetimepermittedbeforeenteringHaltmode fromthedefaultperiodof500 ms. The activetimeisthetimeduringwhichthekeypad isscanned afterthelastkey isreleased,beforeentering Haltmode. The activetimemust be longerthanthedebounce time.
The hostcan program thedirectionand outputstateoffourgeneral-purposeI/Opins.The hostcan alsoread thestateson thesepins.
The hostcan program a 16-bittimerforgeneratinga PWM output.IfthePWM functionisnotused,thePWM pincan be used as a general-purposeoutput.

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VCC ) 3.5V VoltageatAny Pin -0.3VtoVCC +0.3V Maximum InputCurrentWithoutLatchup ±100 mA ESD ProtectionLevel Human Body Model 2 kV Machine Model 200V TotalCurrentintoVCC Pin(Source) 80 mA TotalCurrentoutofGND Pin(Sink) 60 mA StorageTemperatureRange −65°C to+140°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butspecificperformanceisnotspecified.Forspecificationsand testconditions,see the ElectricalCharacteristicstables. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. DC ELECTRICAL CHARACTERISTICS (Temperature:-40°C ≤ TA ≤ +85°C) Data sheetspecificationlimitsarespecifiedby design,test,orstatisticalanalysis. Symbol Parameter Conditions Min (1) Typ Max (1) Units VCC OperatingVoltage 2.25 2.9 V Power SupplyRiseTime from0.0V 20 µs 10 ms (On ChipPower-On ResetSelected) IDD SupplyCurrent(2) RC Clock= 10 MHz, 6 mA VCC = 2.75V,TC = 1 µs (3) IHALT StandbyMode Current(4) VCC = 2.75V,TC = 0 µs,(3),TA <2 15 µA = 25°C VIL Logical0 InputVoltage 0.25VCC V VIH Logical1 InputVoltage 0.8VCC V Hi-ZInputLeakage (TRI-STATE Output) VCC = 2.75V -0.1 0.1 µA InputPullupCurrent VCC = 2.75V,VIN = 0V -15 -120 µA PortInputHysteresis(5) 0.1 V OutputCurrentSource(Weak Pull-Up) VCC = 2.25V,VOH = 1.7V -10 -80 µA OutputCurrentSource(Push-PullMode) VCC = 2.25V,VOH = 1.7V -10 mA OutputCurrentSink(Push-PullMode) VCC = 2.25V,VOL = 0.4V 10 mA AllowableSinkand SourceCurrentperPin 16 mA C PAD InputCapacitance 8.5 pF (1) Data sheetminimum and maximum limitsarespecifiedby design,test,orstatisticalanalysis. (2) Supplycurrentismeasured withinputsconnectedtoVCC and outputsdrivenlowbutnotconnectedtoa load. (3) TC = instructioncycletime(min.0.7µs). (4) InHaltmode, theinternalclockisswitchedoff.SupplycurrentinHaltmode ismeasured withinputsconnectedtoVCC and outputs drivenlowbutnotconnectedtoa load. (5) Specifiedby design,nottested. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM8333

SNLS246K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS (Temperature:-40°C ≤ TA ≤ +85°C) Data sheetspecificationlimitsarespecifiedby design,test,orstatisticalanalysis. Parameter Conditions Min (1) Typ Max (1) Units ExternalR fromCLK_IN toGND 0.75 µs (R = 68 kΩ) InternalOscillator 2.25V≤ VCC ≤ 2.75V System Oscillator(mclk) ExternalR fromCLK_IN toGND 75 ns (R = 68 kΩ) 2.25V≤ VCC ≤ 2.75V System Oscillatorand InternalFrequencyVariation2.25V≤ VCC ≤ 2.75V ±30 % InputPulseWidthLow 0.7 µs InputPulseWidthHigh 0.7 ACCESS Bus InputSignals: Bus FreetimeBetween Stopand StartCondition 16 (IBUFI) (1)(2) SCL SetupTime (tCSTO si)(1)(2) BeforeStopCondition 8 SCL HoldTime (tCSTR hi)(1)(2) AfterStopCondition 8 SCL SetupTime (tCSTR si)(1)(2) BeforeStartCondition 8 mclkData HighSetupTime (tDHCsi) (1)(2) BeforeSCL RisingEdge (RE) 2 Data Low SetupTime (tDLCsi) (1)(2) BeforeSCL RE 2 SCL Low Time (tSCLlowi) (1) AfterSCL FallingEdge (FE) 12 SCL HighTime (tSCLhighi) (1)(2) AfterSCL RE 12 SDA HoldTime (tSDAhi) (1) AfterSCL FE 0 SDA SetupTime (tSDAsi) (1)(2) BeforeSCL RE 2 ACCESS Bus OutputSignals AfterSCL FE 7 mclkSDA HoldTime (tSDAho ) (3) (1) Specifiedby design,test,orstatisticalanalysis. (2) The ACCESS.bus interfaceimplementsand meets thetimingnecessaryforinterfacetotheI2C bus and SMBus protocolatlogiclevels. The bus driversaredesignedwithopen-drainoutputas requiredforbidirectionaloperation.Due toSystem Oscillator(mclk)Variation, thisspecificationmay notmeet theAC timingand current/voltagedriverequirementsofthefullbus specification. (3) Specifiedby design,test,orstatisticalanalysis. Figure14. ACCESS.bus Startand Stop ConditionTiming

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www.ti.com SNLS246K –SEPTEMBER 2006–REVISED MAY 2013

REVISION HISTORY

www.ti.com 8-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM8333FLQ8X/NOPB ACTIVE WQFN NJE 32 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR LM8333F LM8333FLQ8Y/NOPB ACTIVE WQFN NJE 32 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR LM8333F LM8333GGR8/NOPB ACTIVE csBGA NYC 49 1000 Green (RoHS & no Sb/Br) CU SNAGCU Level-1-260C-UNLIM -40 to 85 LM8333 LM8333GGR8AXS/NOPB ACTIVE csBGA NYC 49 1000 Green (RoHS & no Sb/Br) CU SNAGCU Level-1-260C-UNLIM 8333AXS LM8333GGR8AXSX/NOPB ACTIVE csBGA NYC 49 3500 Green (RoHS & no Sb/Br) CU SNAGCU Level-1-260C-UNLIM 8333AXS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 8-Oct-2015 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LM8333GGR8AXSX/NOP B PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8333FLQ8X/NOPB WQFN NJE 32 2500 367.0 367.0 38.0 LM8333FLQ8Y/NOPB WQFN NJE 32 250 213.0 191.0 55.0 LM8333GGR8/NOPB csBGA NYC 49 1000 210.0 185.0 35.0 LM8333GGR8AXS/NOPB csBGA NYC 49 1000 210.0 185.0 35.0 LM8333GGR8AXSX/NOPB csBGA NYC 49 3500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 2

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