LM8333 NSC | Alldatasheet
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Keypad Controller with I/O Expansion and ACCESS.bus Host Interface
1.0 General Description
The LM8333 is a general-purpose controller for matrix- addressed keypads which provides an ACCESS.bus (I 2C- compatible) interface to a host microcontroller. It offloads the burden of keyboard scanning from the host, while providing extremely low power consumption in both operational and standby modes. It supports keypad matrices up t o8x8i n size (plus another 8 special-function keys), for portable ap- plications such as cellphones, PDAs, games, and other handheld applications. Key press and release events are encoded into a byte format and loaded into a FIFO buffer for retrieval by the host pro- cessor. An interrupt output (IRQ) is used to signal events such as keypad activity, a state change on either of two interrupt-capable general-purpose I/O pins, or an error con- dition. Interrupt and error codes are available to the host by reading dedicated registers. Four general-purpose I/O pins are available, two of which have interrupt capability. A pulse-width modulated output based on a host-programmable internal timer is also avail- able, which can be used as a general-purpose output if the PWM function is not required. To minimize power, the LM8333 automatically enters a low- power standby mode when there is no keypad, I/O, or host activity. The device is packaged in a 49-pin MICRO-ARRAY chip- scale package.
2.0 Features
n 8 special function keys (SF keys) providing a total of 72 keys for the maximum keyboard matrix n ACCESS.bus (I2C-compatible) communication interface to the host n Four general purpose host programmable I/O pins with two optional (slow) external Interrupts n 16 byte FIFO buffer to store key pressed and key released events n Error control with error reports on (FIFO overrun, Keypad overrun, invalid command) n Host programmable PWM n Host programmable active time and debounce time
3.0 Block Diagram
LM8333 Keypad Controller with I/O Expansion and ACCESS.bus Host Interface © 2006 National Semiconductor Corporation DS202106 www.national.com
4.0 Pin Assignments
See NS Package Number GRA49A LM8333 www.national.com 2
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5.0 Signal Descriptions
WAKE_IN0 D7 Input Wake-up input/Keyboard scanning input 0 WAKE_IN1 C7 Input Wake-up input/Keyboard scanning input 1 WAKE_IN2 E7 Input Wake-up input/Keyboard scanning input 2 WAKE_IN3 D6 Input Wake-up input/Keyboard scanning input 3 WAKE_IN4 B6 Input Wake-up input/Keyboard scanning input 4 WAKE_IN5 A7 Input Wake-up input/Keyboard scanning input 5 WAKE_IN6 A6 Input Wake-up input/Keyboard scanning input 6 WAKE_IN7 B5 Input Wake-up input/Keyboard scanning input 7 K_OUT0 G3 Output Keyboard scanning output 0 K_OUT1 F4 Output Keyboard scanning output 1 K_OUT2 G4 Output Keyboard scanning output 2 K_OUT3 G5 Output Keyboard scanning output 3 K_OUT4 A5 Output Keyboard scanning output 4 K_OUT5 B4 Output Keyboard scanning output 5 K_OUT6 A4 Output Keyboard scanning output 6 K_OUT7 A3 Output Keyboard scanning output 7 GEN_IO_0 D2 I/O General-purpose I/O 0 GEN_IO_1 D1 I/O General-purpose I/O 1 GEN_IO_2 B3 I/O General-purpose I/O 2 GEN_IO_3 A2 I/O General-purpose I/O 3 SDA F7 I/O ACCESS.bus data signal SCL E6 I/O ACCESS.bus clock signal IRQ F2 Output Interrupt request output PWM F1 Output Pulse-width modulated output WD_OUT G1 Output Watchdog timer output (connect to RESET input) RESET F3 Input Reset input CLK_IN B1 Input Clock input (connect to ground through a 68k ohm resistor) VCC E1, E2 n.a. Vcc GND A1, B2, C3, C4, C5, D3, D4, D5, E3, E4, E5 n.a. Ground NC B7, C1, C2, C6, F5, F6, G2, G6, n.a. No connect LM8333 www.national.com 4
6.0 Typical Application
6.1 I/O EXPANSION OPTIONS
used as a general-purpose output. interrupt event to the host.
6.2 WATCHDOG TIMER
the timer, connect the WD_OUT output to the RESET input.
6.3 HALT MODE
consumption to the minimum level. ment, and the host should then repeat the cycle. shares the bus with peripherals that are continuously active. activity after system initialization. FIGURE 1. Typical Keypad Configuration
6.0 Typical Application(Continued)
6.4 KEYPAD SCANNING
detected, the keypad is rescanned after a debounce delay. encoded and written to the FIFO buffer. events stored in the FIFO or discard them. The SF keys connect the WAKE_INx pins directly to ground.
6.5 COMMUNICATION INTERFACE
slave at speeds up to 400 kHz. MSB (7-bit address mapped to bits 7:1, rather than bits 6:0). Bit 0 is a direction bit (0 on write, 1 on read). asserting the IRQ interrupt request.
6.5.1 Interrupts Between the Host and LM8333
errors, and key-events to the host. by sending a Start Condition on the ACCESS.bus interface.
6.5.2 Interrupt Sources
Any error condition, which is indicated by the error code.
7.0 Device Operation
7.1 EVENT CODE ASSIGNMENT
is released, the MSB of the code is clear. TABLE 1. Keypad Matrix Code Assignments codes loaded into the FIFO buffer.
7.0 Device Operation (Continued)
TABLE 2. Example Sequence of Events
7.2 I/O EXPANSION
7.2.1 PWM Output with Programmable Duty Cycle
initialized. Figure 4shows the command formats. FIGURE 2. Example Event Codes Loaded in FIFO Buffer FIGURE 3. Programmable PWM
TABLE 3. Summary of PWM Control Bits
7.2.2 General-Purpose I/O (GPIO)
FIGURE 4. PWM Control Commands for Arbitrary Duty Cycle FIGURE 5. General-Purpose I/O Control Commands
TABLE 4. General Purpose I/O Pin Configuration
7.2.3 External Interrupts
mode, it also wakes up into Active mode. TABLE 5. Interface Commands for Controlling the LM8333 Read an event from the FIFO. Maximum 14 event codes stored in the FIFO. pointer, for example to retry a read after an error. Maximum 14 event codes stored in the FIFO. DEBOUNCE 0x22 W 8 nnnn nnnn Default is 10 ms. Valid range 1255. GEN_IO_IN 0x30 R 8 0000 nnnn Read port data. GEN_IO_DIR 0x32 W 8 0000 nnnn Select port direction (input or output). C Sets the low pulse time of the PWM signal. PWM_LO 0x41 W 16 (n+1) x t C Sets the high pulse time of the PWM signal. PWM_CTL 0x42 W 8 0000 0nnn Activate, reactivate, or stop PWM. deasserts the IRQ output, and clears the code. READ_STAT 0xE0 R 8 000n nnnn Status Information. active time must be greater than the debounce time. READ_ERROR 0xF0 R 8 0nnn nnnn Reads and clears the error code. FIGURE 6. SET_EXT_INT Command Data Byte
7.3 HOST COMMAND EXECUTION
7.3.1 Command Structure
bytes, and Stop condition for reading the interrupt code. a 7-bit slave address in bits 7:1 and a direction bit in bit 0. 1 on reads from the slave to the host. (0xD0) reads the interrupt code. tion bit is changed. In this case, the direction bit is changed. The data is sent from the slave to the host in the fourth byte. knowledgement (NA) to indicate the end of the data.
7.4 HOST WRITE COMMANDS
listed in Figure 9. The SET_EXT_INT command is 0xD1. N_IO_0 as an external interrupt input.
7.5 HOST READ COMMANDS
second address byte, and a data byte. whenever the slave address or the direction bit is changed. In this case, the direction bit is changed. FIGURE 7. Typical Command Sequence from Host FIGURE 8. Host Write Command
The data is sent from the slave to the host in the fourth byte. indicate the end of the data.
7.6 WAKE-UP FROM HALT MODE
period, so that it can be driven by the LM8333. because it will be in Active mode. FIGURE 9. Host Read Command FIGURE 10. LM8333 Responds with NACK, Host Retries Command
8.0 Interrupts
8.1 INTERRUPT CODE
format of the interrupt code. set when an interrupt occurs. TABLE 6. Interrupt Code ERROR An error condition occurred. EX_1 A rising or falling edge was detected on GEN_IO_1. EX_0 A rising or falling edge was detected on GEN_IO_0. KEYPAD A key-press or key-release event occurred.
8.2 ERROR CODE
7 shows the format of the error code. TABLE 7. Error Code
0 FIFOOVR 0 NOINT 0 KEYOVR CMDUNK CMDOVR
FIFOOVR Key event occurred while the FIFO was full. NOINT Interrupt deasserted before it could be serviced. KEYOVR More than two keys were pressed simultaneously. CMDOVR Command received before it could be accepted, e.g. after wake-up.
8.3 STATUS CODES
the status code, for example to synchronize after an error. TABLE 8. Status Codes Reset 0000 0000 Default after reset. Wake Up Interrupt 0000 0010 Wake-up caused by external interrupt. Ack 0000 0110 Last host command was successful. NoAck 0001 0101 Last host command was not successful.
8.4 INTERRUPT PROCESSING
ample overrun of the FIFO buffer, are reported as errors.
8.0 Interrupts (Continued)
8.5 COMMAND EXECUTION SUMMARY
rupt code using the READ_INT command (0xD0). the status code with the READ_STAT command (0xE0). entering Halt mode from the default period of 500 ms. pin can be used as a general-purpose output. FIGURE 11. Interrupt Processing
9.0 Electrical Characteristics
10.0 Absolute Maximum
Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC) 3.5V Voltage at Any Pin -0.3V to VCC +0.3V Maximum Input Current Without Latchup ±100 mA ESD Protection Level Human Body Model 2 kV Machine Model 200V Total Current into VCC Pin (Source) 80 mA Total Current out of GND Pin (Sink) 60 mA Storage Temperature Range −65˚C to +140˚C
11.0 DC Electrical Characteristics
(Temperature: -40˚C ≤ TA ≤ +85˚C) Data sheet specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions Min (Note 2) Typ Max (Note 2) Units VCC Operating Voltage 2.25 2.75 V Power Supply Rise Time from 0.0V 20 µs 10 ms (On Chip Power-On Reset Selected) I DD Supply Current (Note 3) RC Clock = 10 MHz, 6 mA VCC = 2.75V, TC = 1 µs (Note IHALT Standby Mode Current (Note 5) V CC = 2.75V, TC = 0 µs, (Note 4), TA = 25˚C <21 5 µ A VIL Logical 0 Input Voltage 0.25 VCC V VIH Logical 1 Input Voltage 0.8 V CC V Hi-Z Input Leakage (TRI-STATE Output) VCC = 2.75V -0.1 0.1 µA Input PullupCurrent V CC = 2.75V, VIN = 0V -15 -120 µA Port Input Hysteresis 0.1 V Output Current Source (Weak Pull-Up) (Note 6) V CC = 2.25V, VOH = 1.7V -10 -80 µA Output Current Source (Push-Pull Mode) VCC = 2.25V, VOH = 1.7V -10 mA Output CurrentSink (Push-Pull Mode) VCC = 2.25V, VOL = 0.4V 10 mA Allowable Sink and Source Current per Pin 16 mA CPAD Input Capacitance 8.5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Chara cteristics tables. Note 2: Data sheet minimum and maximum limits are guaranteed by design, test, or statistical analysis. Note 3: Supply current is measured with inputs connected to V CC and outputs driven low but not connected to a load. Note 4: TC = instruction cycle time (min. 0.7 µs). Note 5: In Halt mode, the internal clock is switched off. Supply current in Halt mode is measured with inputs connected to V CC and outputs driven low but not connected to a load. Note 6: Guaranteed by design, not tested. LM8333 www.national.com 14
12.0 AC Electrical Characteristics
(Temperature: -40˚C ≤ TA ≤ +85˚C) Data sheet specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions Min (Note 7) Typ Max (Note 7) Units Internal Oscillator External R from CLK_IN to Gnd (R = 68 kohm) 0.75 µs 2.25V ≤ VCC ≤ 2.75V Internal Oscillator Frequency Variation 2.25V ≤ VCC ≤ 2.75V ±30 % Input Pulse Width Low 0.7 µs Input Pulse Width High 0.7 µs ACCESS.bus Input Timing(Note 8) tBUFi Bus free time between Stop and Start Condition tSCLhigho tCSTOHsi SCL setup time Before Stop Condition 8 t c tCSTRHhi SCL hold time After Start Condition 8 t c tDHCsi Data High setup time Before SCL Rising Edge (RE) 2 t c tDLCsi Data Low setup time Before SCL RE 2 t c tSCLlowi SCL low time After SCL Falling Edge (FE) 12 t c tSCLhighi SCL high time After SCL RE 12 t c tSDAhi SDA hold time After SCL FE 0 ns tSDAsi SDA setup time Before SCL RE 2 t c ACCESS.bus Output Timing(Note 8) tBUFo Bus free time between Stop and Start Condition tSCLhigho tCSTOso SCL setup time Before Stop Condition t SCLhigho tCSTRho SCL hold time After Start Condition t SCLhigho tCSTRso SCL setup time Before Start Condition t SCLhigho tDHCso Data High setup time Before SCL RE t SCLhigho tDLCso Data Low setup time Before SCL RE t SCLhigho tSCLlowo SCL low time After SCL FE 16 t c tSCLhigho SCL high time After SCL RE 16 t c tSDAho SDA hold time After SCL FE 7 t c tSDAvo SDA valid time Before SCL FE 7 t c Note 7: Data sheet minimum and maximum limits are guaranteed by design, test, or statistical analysis. Note 8: The ACCESS.bus interface of the LM8333 device implements and meets the timing necessary for interface to the I 2C bus and SMBus protocol at logic levels. The bus drivers are designed with open-drain output as required for bidirectional operation. The LM8333 device will not meet the AC timing and current/voltage requirements of the full bus specification. LM8333 www.national.com15
12.0 AC Electrical Characteristics(Continued)
FIGURE 12. ACCESS.bus Start and Stop Condition Timing
13.0 Physical Dimensionsinches (millimeters) unless otherwise noted
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