LM8327JGR8X

LM8327 TI1 | Alldatasheet

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LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface Literature Number: SNLS329

September 14, 2011 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface

1.0 General Description

The LM8327 GenI/O-Expander and Keypad Controller is a dedicated device to unburden a host processor from scanning a matrix-addressed keypad and to provide flexible and gen- eral purpose, host-programmable input/output functions. Three independent PWM timer outputs are provided for dy- namic LED brightness modulation. It communicates with a host processor through an I 2C-com- patible ACCESS.bus serial interface. It can communicate in Standard (100 kHz) and Fast-Mode (400 kHz) in slave Mode only. All available input/output pins can alternately be used as a direct key input connection, an input or an output in a keypad matrix, or as a host-programmable general purpose input or output. Any pin programmed as an input can also sense hardware interrupts. The interrupt polarity (“high-to-low” or “low-to-high” transition) is thereby programmable. The LM8327 follows a predefined register based set of com- mands. Upon startup (power on) a configuration file must be sent from the host to setup the hardware of the device.

2.0 Applications:

■ Cordless Phones ■ Smart Handheld Devices ■ Keyboard Applications

3.0 LM8327 Function Blocks

© 2011 National Semiconductor Corporation 301242 www.national.com LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface

4.0 Features

4.1 KEY FEATURES

• Internal RC oscillator, no external clock required
• Internal PWM clock generation, no external clock required
• Programmable I2C-compatible ACCESS.bus address (Default 0x8A)
• Support for Keypad matrices of up to of 8 x 12 keys, plus 8 special function (SF) keys, for a full 104 key support
• Support for up to 26 direct connect keys
• I2C-compatible ACCESS.bus slave interface at 100 kHz (Standard-Mode) and 400 kHz (Fast-Mode)
• Three host-programmable PWM outputs for smooth LED brightness modulation
• Supports general-purpose I/O expansion on pins not otherwise used for keypad or PWM output
• 15-byte Key event buffer
• Multiple Key event storage
• Key events, errors, and dedicated hardware interrupts request host service by asserting an IRQ output
• Automatic HALT Mode for low power operation
• Wake-up from HALT mode on any interface (rising edge, falling edge or pulse)
• Three PWM outputs with dedicated script buffer for up to 32 commands
• Register-based command interpreter with auto-increment address

4.2 HOST-CONTROLLED FEATURES

• PWM scripting for three PWM outputs
• Period of inactivity that triggers entry into HALT mode
• Debounce time for reliable key event polling
• Configuration of general purpose I/O ports
• Various initialization options (keypad size, etc.)

4.3 KEY DEVICE FEATURES

• 1.8V ± 10% single-supply operation
• On-chip power-on reset (POR)
• ESD glitch filter on RESETN pin
• Watchdog timer
• Dedicated slow clock input for 32 kHz up to 8MHz
• −40°C to +85°C temperature range
• 36-pin MICRO ARRAY package www.national.com 2 LM8327

5.0 Pin Assignments

FIGURE 1. LM8327 Pinout - Top View

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5 www.national.com LM8327

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6.0 Ordering Information

7.0 Signal Descriptions

7.1 DEVICE PIN FUNCTIONS

TABLE 1. KEY AND ALTERNATE FUNCTIONS OF ALL DEVICE PINS

Ball Function 0 Function 1 Function 2 Function 3 Pin Count Ball Name E3 Direct Keypad16 Keypad - I/O Y8 Genio 1 DIRECT16 KPY8 D5 Direct Keypad17 Keypad - I/O Y9 Genio 1 DIRECT17 KPY9 E6 Direct Keypad18 Keypad - I/O Y10 Genio 1 DIRECT18 KPY10 F6 Direct Keypad19 Keypad - I/O Y11 Clockout Genio 1 DIRECT19 KPY11 E4 Direct Keypad20 PWM output 0 Genio 1 DIRECT20 PWM0 F5 Direct Keypad21 PWM output 1 Genio 1 DIRECT21 PWM1 E5 Direct Keypad22 PWM output 2 Genio 1 DIRECT22 PWM2 D6 Direct Keypad23 Genio 1 DIRECT23 GENIO1 Ground 4 GND TOTAL 36 www.national.com 8 LM8327

7.2 PIN CONFIGURATION AFTER RESET

on the states of all functional pins. TABLE 2. Pin Configuration after Reset Full Buffer mode input with an on-chip pull-up resistor enabled. IRQN Open Drain mode with no pull resistor enabled, driven low. SDA Open Drain mode with no pull resistor enabled.

8.0 Typical Application Setup

FIGURE 2. LM8327 in a Typical Setup with Standard Handset Keypad

8.1 FEATURES

8.1.1 Hardware

• 4 x 8 keys and 8 Special Function (SF) keys for 40 keys.
• ACCESS.bus interface for communication with a host device. - communication speeds supported are: 100 kHz standard mode and 400 kHz fast mode of operation.
• Interrupt signal (IRQN) to indicate any keypad or hardware interrupt events to the host.
• Sophisticated PWM function block with 3 independent channels to control color LED.
• External clock input for accurate PWM clock (not used).
• Four host-programmable dedicated general-purpose output pins (GPIOs:KPY4:7) supporting I/O-expansion capabilities for host device.
• Six host-programmable dedicated direct key connection input pins (DIRECT 16:19, 23, 25) with wake-up supporting I/O-expansion capabilities for host device.

8.1.2 Communication Layer

• Versatile register-based command integration supported from on-chip command interpreter.
• Keypad event storage.
• Individual PWM script file storage and execution control for 3 PWM channels. www.national.com 10 LM8327

9.0 Halt Mode

9.1 HALT MODE DESCRIPTION

FIGURE 3. Halt Current vs. Temperature at 1.98V

10.0 LM8327 Programming Interface

LM8327 Register Set for the complete register set. Figure 4 shows a typical read cycle initiated by the host. FIGURE 4. Master/Slave Serial Communication (Host to LM8327) TABLE 3. Definition of Terms used in Serial Command Example address the host wants to read from or write to. DATA 8 The DATA field contains information to be stored into a register or information read from a register. P STOP condition (always generated from the master device). Figure 4 are controlled from the master (host) device. controlled from the slave (LM8327) device.

10.1.1 Starting a Communication Cycle

1. The LM8327 device has set the IRQN line low in order to

initializes a hardware interrupt from LM8327 to the host.

1. The host device wants to set a GENIO port, read from a

communication with the LM8327 device.

10.1.2 Communication Initialized from Host (Restart from

FIGURE 5. Host Starts Communication While LM8327 is in Sleep Mode

• In the timing diagram shown in Figure 5 the LM8327 resides in sleep mode. Since the LM8327 device can’t acknowledge the slave address the host must generate a STOP condition followed by a second START condition.
• On the second attempt the slave address is being acknowledged from the LM8327 device because it is in active mode now.
• The host can send different WRITE and/or READ commands subsequently after each other.
• The host must finally free the bus by generating a STOP condition. 10.1.3 ACCESS.Bus Communication Flow The LM8327 will only be driven in slave mode. The maximum communication speed supported is Fast Mode (FS) which is 400 kHz. The device can be heavily loaded as it is processing different kind of events caused from the human interface and the host device. In such cases the LM8327 may temporarily be unable to accept new commands and data sent from the host device. Please Note: “It is a legitimate measure of the slave device to hold SCL line low in such cases in order to force the master device into a waiting state!. It is therefore the obligation of the host device to detect such cases. Typically there is a control bit set in the master device indicating the Busy status of the bus. As soon as the SCL line is released the host can continue sending commands and data.” Further Remarks:
• In systems with multiple masters it is recommended to separate commands with Repeat START conditions rather than sending a STOP - and another START - condition to communicate with the LM8327 device.
• Delays enforced by the LM8327 during very busy phases of operation should typically not exceed a duration of 100 µsec.
• Normally the LM8327 will clock stretch after the acknowledge bit is transmitted; however, there are some conditions where the LM8327 will clock stretch between the SDA Start bit and the first rising edge of SCL.

10.1.4 Auto Increment

supports the auto increment of the address pointer. until the STOP condition is received. ACCESS.bus flow of reading and writing multiple data bytes.

10.1.5 Reserved Registers and Bits

10.1.6 Global Call Reset

TABLE 4. Multi-Byte Write with Auto Increment

1 M S START condition

3 M R/W 0 Write

4 S ACK Acknowledge

5 M REG 0xAA 0xAA Register Address, used as Address Pointer

6 S ACK 0xAA Acknowledge

7 M DATA 0x01 0xAA Write Data to Address in Pointer

8 S ACK 0 0xAB Acknowledge, Address pointer incremented

9 M DATA 0x05 0xAB Write Data to address 0xAB

10 S ACK 0 0xAC Acknowledge, Address pointer incremented

11 M P STOP condition

TABLE 5. Multi-Byte Read with Auto Increment

7 M RS 0xAA Repeated Start

9 M R/W 1 Read

10 S ACK 0 0xAA Acknowledge

11 S DATA 0x01 0xAA Read Data from Address in Pointer

12 M ACK 0 0xAB Acknowledge, Address Pointer incremented

13 S DATA 0x05 0xAB Read Data from Address in Pointer

14 M NACK 0 0xAC No Acknowledge, stops transmission

15 M P STOP condition

All non-bolded actions rows in Tables 4 and 5 are controlled from the master (host) device. All highlighted rows in Tables 4 and 5 are controlled from the slave (LM8327) device.

11.0 Keyscan Operation

11.1 KEYSCAN INITIALIZATION

FIGURE 6. Keyscan Initialization

11.2 KEYSCAN INITIALIZATION EXAMPLE

• Keypad matrix configuration is 8 rows x 12 columns.

TABLE 6. Keyscan Initialization Example

11.3 KEYSCAN PROCESS

the device sets the RAW keyboard event interrupt REVTINT. as soon as one interrupt in KBDRIS is set. which registers are affected. FIGURE 7. Example Keyscan Operation for

1 Key Press and Release

11.4 READING KEYSCAN STATUS BY THE HOST

act on the Interrupt signaled by the IRQN pin. of KBDRIS and reflects the source for raising the interrupt pin. buffer by sending one command. FIGURE 8. Example Host Reacting to

11.5 MULTIPLE KEY PRESSES

The LM8327 supports up to four simultaneous key presses. All KBDCODE[3:0] registers are cleared on read. FIGURE 9. Example Keyscan Operation for 2 Key Press Events

12.0 Direct Key Operation

12.1 DIRECT KEY INITIALIZATION

FIGURE 10. Direct Key Initialization

12.2 DIRECT KEY INITIALIZATION EXAMPLE

Table 7 shows all the LM8327 register configurations to initialize direct keys.

• Direct key configuration is for 26 direct keys.

TABLE 7. Direct Key Initialization Example DBOUNCE 0xE7 byte 0x04 Set the keyscan debounce time to 12 msec.

13.0 PWM Timer

LED control techniques (lighting controls).

13.1 OVERVIEW OF PWM FEATURES

• Each PWM can establish fixed - or variable - duty-cycle signal sequences on its output.
• Each PWM can trigger execution of any pre-programmed task on another PWM channel.
• The execution of any pre-programmed task is self- sustaining and does not require further interaction from the host.
• 64-byte script buffer for each PWM for up to 32 consecutive instructions.
• Direct addressing within script buffer to support multiple PWM tasks in one buffer.

13.2 OVERVIEW ON PWM SCRIPT COMMANDS

with help of the register-based command set. TABLE 8. PWM Script Commands

13.2.1 RAMP COMMAND

and the PRESCALE bit determine the duration of one step. imum time for one step would be 1 second. TABLE 9. RAMP Command Bit Fields

0 PRESCALE STEPTIME SIGN INCREMENT

TABLE 10. Description of Command Bit Fields of the RAMP Command

1 Decrement RAMP counter

WAIT determined by STEPTIME.

13.2.2 SET_PWM COMMAND

PWM output with a fixed duty cycle between 0% and 100%. TABLE 11. SET_PWM Command Bit Fields

TABLE 12. Description of Bit Fields of the SET_PWM Command DUTYCYCLE 0 Duty cycle is 0%.

13.2.3 GO_TO_START COMMAND

TABLE 13. GO_TO_START Command Bit Fields

13.2.4 BRANCH COMMAND

Please note: Nested loops are not allowed. TABLE 14. BRANCH Command Bit Fields TABLE 15. Description of Command Bit Fields of the BRANCH Command LOOPCOUNT 0 Loop until a STOP PWM SCRIPT command is issued by the host. 1 - 63 Number of loops to perform.

1 Relative addressing

13.2.5 TRIGGER COMMAND

for a trigger takes at least sixteen 32.768 kHz clock cycles. stall script execution until the trigger conditions are satisfied. a TRIGGER command that waits for the trigger. TABLE 16. TRIGGER Command Bit Fields TABLE 17. Description of Command Bit Fields

13.2.6 END COMMAND

assert an interrupt to the host if the INT bit is set to “1”. of the script command buffer.

exception - in this case the IRQ signal will not be asserted. TABLE 18. END Command Bit Fields TABLE 19. Description of Command Bit Fields of the END Command INT 0 No interrupt will be sent. 1 Set TIMRIS.CDIRQ for this PWM channel to notify that program has ended.

14.0 LM8327 Register Set

14.1 KEYBOARD REGISTERS AND KEYBOARD

the functions of the associated registers down to the bit level.

14.1.1 KBDSETTLE - Keypad Settle Time Register

TABLE 20. KBDSETTLE - Keypad Settle Time Register KBDSETTLE 0x01 R/W Initial time for keys to settle, before the key-scan process is started.

14.1.2 KBDBOUNCE - Debounce Time Register

TABLE 21. KBDBOUNCE - Debounce Time Register KBDBOUNCE 0x02 R/W Time between first detection of key and final sampling of key. The default value 0x80 : 0xBF sets a time target of 12 msec.

14.1.3 KBDSIZE - Set Keypad Size Register

TABLE 22. KBDSIZE - Set Keypad Size Register KBDSIZE 0x03 R/W Defines the physical keyboard matrix size. inputs if scanning is enabled by CLKEN.KBEN.

14.1.4 KBDDEDCFG - Dedicated Key Register

TABLE 23. KBDDEDCFG - Dedicated Key Register it is used as dedicated key input. Each bit in ROW [7:2] corresponds to ball KPX7 : KPX2. Bit=0: the dedicated key function applies. Each bit in COL [11:10] corresponds to ball KPY11 : KPY10. Bit=0: the dedicated key function applies. Bit=0: the dedicated key function applies.

14.1.5 KBDRIS - Keyboard Raw Interrupt Status Register

TABLE 24. KBDRIS - Keyboard Raw Interrupt Status Register KBDRIS 0x06 R Returns the status of stored keyboard interrupts. Raw keyboard event interrupt. At least one key press or key release is in the keyboard event buffer. Raw key lost interrupt indicates a lost key-code.

14.1.6 KBDMIS - Keypad Masked Interrupt Status Register

TABLE 25. KBDMIS - Keypad Masked Interrupt Status Register Masked event lost interrupt. Masked keyboard event interrupt. At least one key press or key release is in the keyboard event buffer. or when more than 4 keys are pressed simultaneously. changed, after masking process.

14.1.7 KBDIC - Keypad Interrupt Clear Register

TABLE 26. KBDIC - Keypad Interrupt Clear Register KBDIC 0x08 W Setting these bits clears Keypad active Interrupts. has no special function layout. RELINT by writing a 1 to this bit position.

14.1.8 KBDMSK - Keypad Interrupt Mask Register

TABLE 27. KBDMSK - Keypad Interrupt Mask Register trigger an event on the Interrupt output.

14.1.9 KBDCODE0 - Keyboard Code Register 0

a bit (MULTIKEY) indicating if another key has been detected. the KBDCODE0 register means that no key was pressed. TABLE 28. KBDCODE0 - Keyboard Code Register 0 KBDCODE0 0x0B R Holds the row and column information of the first detected key. MULTIKEY 7 0x0 If this bit is 1 another key is available in KBDCODE1 register. KEYCOL[3:0] 3:0 0xF Column index of detected (0 to 11, 12 for special function key).

14.1.10 KBDCODE1 - Keyboard Code Register 1

TABLE 29. KBDCODE1 - Keyboard Code Register 1 KBDCODE1 0x0C R Holds the row and column information of the second detected key. MULTIKEY 7 0x0 If this bit is 1 another key is available in KBDCODE2 register. KEYCOL[3:0] 3:0 0xF Column index of detected key (0 to 11, 12 for special function key).

14.1.11 KBDCODE2 - Keyboard Code Register 2

TABLE 30. KBDCODE2 - Keyboard Code Register 2 KBDCODE2 0x0D R Holds the row and column information of the third detected key. MULTIKEY 7 0x0 If this bit is 1 another key is available in KBDCODE3 register. KEYCOL[3:0] 3:0 0xF Column index of detected key (0 to 11, 12 for special function key).

14.1.12 KBDCODE3 - Keyboard Code Register 3

TABLE 31. KBDCODE3 - Keyboard Code Register 3 KBDCODE3 0x0E R Holds the row and column information of the forth detected key. KEYCOL[3:0] 3:0 0xF Column index of detected key (0 to 11, 12 for special function key).

14.1.13 EVTCODE - Key Event Code Register

TABLE 32. EVTCODE - Key Event Code Register is empty. See further details below. always read from the same address. KEYROW[2:0] 6:4 0x7 Row index of key that is pressed or released.

14.2 PWM TIMER CONTROL REGISTERS

ated registers down to the bit level.

14.2.1 TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers

TABLE 33. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers

14.2.2 PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers

TABLE 34. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers PWMCFG1 0x69 PGEx is used to start and stop the PWM script execution. or the value configured in PWMPOLx. this channel. Script execution is started always from beginning. Off-state of PWM output, when PWMEN=0.

14.2.3 TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers

TABLE 35. TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers use the same slow clock, TIMSCAL0 affects all 3 PWM channels. TIMSCAL1 and TIMSCAL2 are directly linked to TIMSCAL0. SCAL[7:0] 7:0 0x0 CLKIN is divided by (SCAL+1).

14.2.4 TIMSWRES - PWM Timer Software Reset Registers

TABLE 36. TIMSWRES - PWM Timer Software Reset Registers Reset control on all PWM timers. it. Each reset stops all state-machines and timer. Patterns stored in the pattern configuration register remain unaffected. writing into register TIMIC. 1: Software reset on timer 2, needs not to be written back to 0. 1: Software reset on timer 1, needs not to be written back to 0. 1: software reset on timer 0, needs not to be written back to 0.

14.2.5 TIMRIS - PWM Timer Interrupt Status Register

TABLE 37. TIMRIS - PWM Timer Interrupt Status Register

14.2.6 TIMMIS - PWM Timer Masked Interrupt Status Register

TABLE 38. TIMMIS - PWM Timer Masked Interrupt Status Register bits to get the masked interrupt status of this register.

14.2.7 TIMIC - PWM Timer Interrupt Clear Register

TABLE 39. TIMIC - PWM Timer Interrupt Clear Register This register clears timer and pattern interrupts.

14.2.8 PWMWP - PWM Timer Pattern Pointer Register

TABLE 40. PWMWP - PWM Timer Pattern Pointer Register will be overwritten by the next write access to be PWMCFG register.

14.2.9 PWMCFG - PWM Script Register (Two Byte)

TABLE 41. PWMCFG - PWM Script Register by PWMWP. PWMWP is automatically incremented. at 0x7E for each word access. CMD[15:8] 15:8 High byte portion of a PWM script command. CMD[7:0] 7:0 Low byte portion of a PWM script command.

14.3 INTERFACE CONTROL REGISTERS

trol registers provided for the main controller. has to be used for this device.

• Write - I2CSA
• Read - MFGCODE 14.3.1 I2CSA - I2C-Compatible ACCESS.bus Slave Address Register

TABLE 42. I2CSA - I2C-Compatible ACCESS.bus Slave Address Register I2C-compatible ACCESS.bus Slave Address. The address is internally applied after the next I2C STOP. SLAVEADDR[7:1] 7:1 0x45 7-bit address field for the I2C-compatible ACCESS.bus slave address.

14.3.2 MFGCODE - Manufacturer Code Register

TABLE 43. MFGCODE - Manufacturer Code Register MFGCODE 0x80 R Manufacturer code of the LM8327. MFGBIT 7:0 0x00 8-bit field containing the manufacturer code.

14.3.3 SWREV - Software Revision Register

TABLE 44. SWREV - Software Revision Register Software revision code of the LM8327. SWBIT 7:0 0xC4 8-bit field containing the SW Revision number.

14.3.4 SWRESET - Software Reset

TABLE 45. SWRESET - Software Reset Register Reading this register provides the software revision (see Table 44). SWBIT 7:0 Reapply inverted value for software reset.

14.3.5 RSTCTRL - System Reset Register

This register allows to reset specific blocks of the LM8327.

TABLE 46. RSTCTRL - System Reset Register RSTCTRL 0x82 R/W Software reset of specific parts of the LM8327.

14.3.6 RSTINTCLR - Clear NO Init/Power-On Interrupt Register

TABLE 47. RSTINTCLR - Clear NO Init/Power-On Interrupt Register IRQCLR 0 1: Clears the PORIRQ Interrupt signalled in IRQST register.

14.3.7 CLKMODE - Clock Mode Register

TABLE 48. CLKMODE - Clock Mode Register current operating mode, which should always be 01.

14.3.8 CLKCFG - Clock Configuration Register

TABLE 49. CLKCFG - Clock Configuration Register CLKCFG 0x89 R/W Configures clock sources and power options of the device. NOTE: Don't change while a PWM script is in progress.

14.3.9 CLKEN - Clock Enable Register

TABLE 50. CLKEN - Clock Enable Register enable the functional blocks globally and independently. 00: CLKOUT clock disabled. Fixed to low level. 01: CLKOUT frequency = PWM slow clock frequency. 1: Timer 0, 1, 2 clock enabled. *Note: Only one of KBDEN or DKBDEN of CLKEN register can be set at a time, since Direct Key functions cannot be used at the same time as Keypad (Matrix). Setting both bits to 1 at the same time will enable only Direct Key.

14.3.10 AUTOSLP - Autosleep Enable Register

TABLE 51. AUTOSLP - Autosleep Enable Register AUTOSLP 0x8B R/W This register controls the Auto Sleep function of the LM8327 device.

14.3.11 AUTOSLPTI - Auto Sleep Time Register

TABLE 52. AUTOSLPTI - Auto Sleep Time Register AUTOSLP.ENABLE bit is set to 1.

14.3.12 IRQST - Global Interrupt Status Register

TABLE 53. IRQST - Global Interrupt Status Register after power-on, the bit is set. 1: Failure, device was completely reset and requires re-programming.

14.4 GPIO FEATURE CONFIGURATION

14.4.1 GPIO Feature Mapping

• Direct Key
• Keypad
• GPIO
• PWM With this, each ball will be available as keypad, GPIO, or PWM unless it is specified to be a direct key. The configuration for direct key, keypad, GPIO or PWM usage is defined by the following registers:
• DIRECTn — This register defines a ball as a direct key.
• KBDSIZE and KBDDEDCFG — Both registers define a ball as either part of the keypad matrix or as dedicated key input. These settings have highest priority and will overwrite settings made in other registers.
• IOCFG — This register is used to define the usage of PWM[2:0] and EXTIO if not configured to be part of the keymatrix, to be used as GPIO.

TABLE 54. Ball Configuration Options

14.4.2 IOCGF - Input/Output Pin Mapping Configuration Register

TABLE 55. IOCGF - Input/Output Pin Mapping Configuration Register

14.4.3 IOPC0 - Pull Resistor Configuration Register 0

TABLE 56. IOPC0 - Pull Resistor Configuration Register 0 IOPC0* OxAA R/W Defines the pull resistor configuration for balls KPX[7:0].

• Written values of 0x2 and 0x3 will always be read back as 0x3.

14.4.4 IOPC1 - Pull Resistor Configuration Register 1

TABLE 57. IOPC1 - Pull Resistor Configuration Register 1 IOPC1** 0xAC R/W Defines the pull resistor configuration for balls KPY[7:0].

** Written values of 0x2 and 0x3 will always be read back as 0x3.

14.4.5 IOPC2 - Pull Resistor Configuration Register 2

TABLE 58. IOPC2 - Pull Resistor Configuration Register 2

*** Written values of 0x2 and 0x3 will always be read back as 0x3.

14.4.6 GPIOOME0 - GPIO Open Drain Mode Enable Register 0

TABLE 59. GPIOOME0 - GPIO Open Drain Mode Enable Register 0 GPIOOME0 0xE0 R/W Configures KPX[7:0] for Open Drain or standard output functionality. The Open Drain drive source is configured by GPIOOMS0.

14.4.7 GPIOOMS0 - GPIO Open Drain Mode Select Register 0

TABLE 60. GPIOOMS0 - GPIO Open Drain Mode Select Register 0

14.4.8 GPIOOME1 - GPIO Open Drain Mode Enable Register 1

TABLE 61. GPIOOME1 - GPIO Open Drain Mode Enable Register 1 GPIOOME1 0xE2 R/W Configures KPY[7:0] for Open Drain or standard output functionality. The Open Drain drive source is configured by GPIOOMS1.

14.4.9 GPIOOMS1 - GPIO Open Drain Mode Select Register 1

TABLE 62. GPIOOMS1 - GPIO Open Drain Mode Select Register 1

14.4.10 GPIOOME2 - GPIO Open Drain Mode Enable Register 2

TABLE 63. GPIOOME2 - GPIO Open Drain Mode Enable Register 2

14.4.11 GPIOOMS2 - GPIO Open Drain Mode Select Register 2

TABLE 64. GPIOOMS2 - GPIO Open Drain Mode Select Register 2 EXTIO if selected by GPIOOME2.

14.5 GPIO DATA INPUT/OUTPUT

14.5.1 GPIOPDATA0 - GPIO Data Register 0

TABLE 65. GPIOPDATA0 - GPIO Data Register 0 masked with the associated MASK register. register are masked with MASK and then applied to the associated pin. register hold the masked input value of the associated pin.

DATA7 7 0x0 Pin Status for KPX7 when enabled as GPIO. DATA6 6 0x0 Pin Status for KPX6 when enabled as GPIO. DATA5 5 0x0 Pin Status for KPX5 when enabled as GPIO. DATA4 4 0x0 Pin Status for KPX4 when enabled as GPIO. DATA3 3 0x0 Pin Status for KPX3 when enabled as GPIO. DATA2 2 0x0 Pin Status for KPX2 when enabled as GPIO. DATA1 1 0x0 Pin Status for KPX1 when enabled as GPIO. DATA0 0 0x0 Pin Status for KPX0 when enabled as GPIO.

14.5.2 GPIOPDATA1 - GPIO Data Register 1

TABLE 66. GPIOPDATA1 - GPIO Data Register 1 masked with the associated MASK register. register are masked with MASK and then applied to the associated pin. register hold the masked input value of the associated pin.

DATA15 7 0x0 Pin Status for KPY7 when enabled as GPIO. DATA14 6 0x0 Pin Status for KPY6 when enabled as GPIO. DATA13 5 0x0 Pin Status for KPY5 when enabled as GPIO. DATA12 4 0x0 Pin Status for KPY4 when enabled as GPIO. DATA11 3 0x0 Pin Status for KPY3 when enabled as GPIO. DATA10 2 0x0 Pin Status for KPY2 when enabled as GPIO. DATA9 1 0x0 Pin Status for KPY1 when enabled as GPIO. DATA8 0 0x0 Pin Status for KPY0 when enabled as GPIO.

14.5.3 GPIOPDATA2 - GPIO Data Register 2

TABLE 67. GPIOPDATA2 - GPIO Data Register 2 EXTIO. Every data I/O is masked with the associated MASK register. register are masked with MASK and then applied to the associated pin. register hold the masked input value of the associated pin. DATA23 7 0x0 Pin Status for EXTIO when enabled as GPIO. DATA22 6 0x0 Pin Status for PWM2 when enabled as GPIO. DATA21 5 0x0 Pin Status for PWM1 when enabled as GPIO. DATA20 4 0x0 Pin Status for PWM0 when enabled as GPIO.

DATA18 2 0x0 Pin Status for KPY10 when enabled as GPIO. DATA17 1 0x0 Pin Status for KPY9 when enabled as GPIO. DATA16 0 0x0 Pin Status for KPY8 when enabled as GPIO.

14.5.4 GPIOPDIR0 - GPIO Port Direction Register 0

TABLE 68. GPIOPDIR0 - GPIO Port Direction Register 0 GPIODIR0 0xC6 R/W Port direction for KPX[7:0].

14.5.5 GPIOPDIR1 - GPIO Port Direction Register 1

TABLE 69. GPIOPDIR1 - GPIO Port Direction Register 1 GPIODIR1 0xC7 R/W Port direction for KPY[7:0].

14.5.6 GPIOPDIR2 - GPIO Port Direction Register 2

TABLE 70. GPIOPDIR2 - GPIO Port Direction Register 2 GPIODIR2 0xC8 R/W Port direction for KPY[11:8], PWM[2:0], EXTIO.

14.6 GPIO INTERRUPT CONTROL

14.6.1 GPIOIS0 - Interrupt Sense Configuration Register 0

TABLE 71. GPIOIS0 - Interrupt Sense Configuration Register 0 GPIOIS0 0xC9 R/W Interrupt type on KPX[7:0].

14.6.2 GPIOIS1 - Interrupt Sense Configuration Register 1

TABLE 72. GPIOIS1 - Interrupt Sense Configuration Register 1 GPIOIS1 0xCA R/W Interrupt type on KPY[7:0].

14.6.3 GPIOIS2 - Interrupt Sense Configuration Register 2

TABLE 73. GPIOIS2 - Interrupt Sense Configuration Register 2 GPIOIS2 0xCB R/W Interrupt type on KPY[11:8], PWM[2:0], EXTIO.

14.6.4 GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0

TABLE 74. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0 or on a single edge. See Table 77 for the edge configuration.

14.6.5 GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1

TABLE 75. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1 or on a single edge. See Table 78 for the edge configuration.

14.6.6 GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2

TABLE 76. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2

14.6.7 GPIOIEV0 - GPIO Interrupt Edge Select Register 0

TABLE 77. GPIOIEV0 - GPIO Interrupt Edge Select Register 0 GPIOIEV0 0xCF R/W Select Interrupt edge for KPX[7:0].

14.6.8 GPIOIEV1 - GPIO Interrupt Edge Select Register 1

TABLE 78. GPIOIEV1 - GPIO Interrupt Edge Select Register 1 GPIOIEV1 0xD0 R/W Select Interrupt edge for KPY[7:0].

14.6.9 GPIOIEV2 - GPIO Interrupt Edge Select Register 2

TABLE 79. GPIOIEV2 - GPIO Interrupt Edge Select Register 2 GPIOIEV2 0xD1 R/W Select Interrupt edge for KPY[11:8], PWM[2:0], EXTIO.

14.6.10 GPIOIE0 - GPIO Interrupt Enable Register 0

TABLE 80. GPIOIE0 - GPIO Interrupt Enable Register 0 GPIOIE0 0xD2 R/W Enable/disable interrupts on KPX[7:0].

14.6.11 GPIOIE1 - GPIO Interrupt Enable Register 1

TABLE 81. GPIOIE1 - GPIO Interrupt Enable Register 1

14.6.12 GPIOIE2 - GPIO Interrupt Enable Register 2

TABLE 82. GPIOIE2 - GPIO Interrupt Enable Register 2 GPIOIE2 0xD4 R/W Enable/disable interrupts on KPY[11:8], PWM[2:0], EXTIO.

14.6.13 GPIOIC0 - GPIO Clear Interrupt Register 0

TABLE 83. GPIOIC0 - GPIO Clear Interrupt Register 0 GPIOIC0 0xDC W Clears the interrupt on KPX[7:0]. Clear Interrupt on KPX[7:0].

14.6.14 GPIOIC1 - GPIO Clear Interrupt Register 1

TABLE 84. GPIOIC1 - GPIO Clear Interrupt Register 1 GPIOIC1 0xDD W Clears the interrupt on KPY[7:0]. Clear Interrupt on KPY[7:0].

14.6.15 GPIOIC2 - GPIO Clear Interrupt Register 2

TABLE 85. GPIOIC2 - GPIO Clear Interrupt Register 2 GPIOIC2 0xDE W Clears the interrupt on KPY[11:8], PWM[2:0], EXTIO.

14.7 GPIO INTERRUPT STATUS

14.7.1 GPIORIS0 - Raw Interrupt Status Register 0

TABLE 86. GPIORIS0 - Raw Interrupt Status Register 0 GPIORIS0 0xD6 R Raw interrupt status on KPX[7:0].

14.7.2 GPIORIS1 - Raw Interrupt Status Register 1

TABLE 87. GPIORIS1 - Raw Interrupt Status Register 1 GPIORIS1 0xD7 R Raw interrupt status on KPY[7:0].

14.7.3 GPIORIS2 - Raw Interrupt Status Register 2

TABLE 88. GPIORIS2 - Raw Interrupt Status Register 2 GPIORIS2 0xD8 R Raw interrupt status on KPY[11:8], PWM[2:0], EXTIO.

14.7.4 GPIOMIS0 - Masked Interrupt Status Register 0

TABLE 89. GPIOMIS0 - Masked Interrupt Status Register 0 GPIOMIS0 0xD9 R Masked interrupt status on KPX[7:0].

14.7.5 GPIOMIS1 - Masked Interrupt Status Register 1

TABLE 90. GPIOMIS1 - Masked Interrupt Status Register 1 GPIOMIS1 0xDA R Masked interrupt status on KPY[7:0].

14.7.6 GPIOMIS2 - Masked Interrupt Status Register 2

TABLE 91. GPIOMIS2 - Masked Interrupt Status Register 2 GPIOMIS2 0xDB R Masked interrupt status on KPY[11:8], PWM[2:0], EXTIO.

14.8 GPIO WAKE-UP CONTROL

14.8.1 GPIOWAKE0 - GPIO Wake-Up Register 0

TABLE 92. GPIOWAKE0 - GPIO Wake-Up Register 0 Configures wake-up conditions for KPX[7:0]. contributes to wakeup from auto sleep mode.

14.8.2 GPIOWAKE1 - GPIO Wake-Up Register 1

TABLE 93. GPIOWAKE1 - GPIO Wake-Up Register 1 Configures wake-up conditions for KPY[7:0]. contributes to wakeup from auto sleep mode.

14.8.3 GPIOWAKE2 - GPIO Wake-Up Register 2

TABLE 94. GPIOWAKE2 - GPIO Wake-Up Register 2 Configures wake-up conditions for KPY[11:8], PWM[2:0}, EXTIO. contributes to wakeup from auto sleep mode.

14.9 DIRECT KEY REGISTERS AND DIRECT KEY

the functions of the associated registers down to the bit level.

14.9.1 DEVTCODE - Direct Key Event Code Register

TABLE 95. DEVTCODE - Direct Key Event Code Register address means that the FIFO buffer is empty and a key is still pressed. empty state. See further details below. always read from the same address. DKEYCODE 4:0 0x1F Column index of key is pressed (0...24, 25 for Direct keys).

14.9.2 DBOUNCE - Direct Key Debounce Time Register

TABLE 96. DBOUNCE - Direct Key Debounce Time Register DBOUNCE 0xE7 R/W Time between first detection of key and final sampling of key. De-bounce time for direct keys.

14.9.3 DIRECT0 - Direct Key Register 0

TABLE 97. DIRECT0 - Direct Key Register 0 DIRECT0 0xEC R/W Enable Direct Key connections for DK[7:0]. 0: Direct Key follows IOCFG and keypad registers.

14.9.4 DIRECT1 - Direct Key Register 1

TABLE 98. DIRECT1 - Direct Key Register 1 DIRECT1 0xED R/W Enable Direct Key connections for DK[15:8]. 0: Direct Key follows IOCFG and keypad registers.

14.9.5 DIRECT2 - Direct Key Register 2

TABLE 99. DIRECT2 - Direct Key Register 2 DIRECT2 0xEE R/W Enable Direct Key connections for DK[23:16]. 0: Direct Key follows IOCFG and keypad registers.

14.9.6 DIRECT3 - Direct Key Register 3

TABLE 100. DIRECT3 - Direct Key Register 3 DIRECT3 0xEF R/W Enable Direct Key connections for DK[25:24]. 0: Direct Key follows IOCFG and keypad registers.

14.9.7 DKBDRIS - Direct Key Raw Interrupt Status Register

TABLE 101. DKBDRIS - Direct Key Raw Interrupt Status Register DKBDRIS 0xF0 R Returns the status of stored direct key interrupts. Raw direct key event interrupt. automatically clear this interrupt.

14.9.8 DKBDMIS - Direct Key Masked Interrupt Status Register

TABLE 102. DKBDMIS - Direct Key Masked Interrupt Status Register Masked event lost interrupt. Masked direct key event interrupt. automatically clear this interrupt.

14.9.9 DKBDIC - Direct Key Interrupt Clear Register

TABLE 103. DKBDIC - Direct Key Interrupt Clear Register DKBDIC 0xF2 W Setting these bits clears direct key active interrupts. DRELINT by writing a '1' to this bit position.

14.9.10 DKBDMSK - Direct Key Interrupt Mask Register

TABLE 104. DKBDMSK - Direct Key Interrupt Mask Register trigger an event of the interrupt output. 1: direct key event lost interrupt DRELINT is masked. 1: direct key event interrupt DREVTINT is masked.

15.0 Absolute Maximum Ratings (Note

Distributors for availability and specifications.

16.0 Electrical Characteristics

TABLE 105. DC ELECTRICAL CHARACTERISTICS Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. TABLE 106. AC ELECTRICAL CHARACTERISTICS Data sheet specification limits are guaranteed by design, test, or statistical analysis.

TABLE 107. GENERAL GPIO CHARACTERISTICS Characteristics for all pins except CLKIN, IRQN/KPY11/PWM2, SDA, and SCL in GPIO mode. TABLE 108. BACKDRIVE/OVERVOLTAGE I/O DC CHARACTERISTICS TABLE 109. BACKDRIVE/OVERVOLTAGE I/O AC CHARACTERISTICS

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. Note 2: Supply and IDLE current is measured with inputs connected to VCC and outputs driven low but not connected to a load. Note 3: Values are estimates. Values will be updated after characterization is completed. Note 4: In sleep mode, the internal clock is switched off. Supply current in sleep mode is measured with inputs connected to VCC and outputs driven low but not connected to a load. Note 5: Guaranteed by design, not tested. Note 6: The ACCESS.bus interface implements and meets the timings necessary for interface to the I2C and SMBus protocols at logic levels. The bus drivers have open-drain outputs for bidirectional operation. Due to Internal RC Oscillator Frequency Variation, this specification may not meet the AC timing and current/ voltage drive requirements of the full-bus specifications. Note 7: The sum of all I/O sink/source current must not exceed the maximum total current into VCC and out of GND as specified in the absolute maximum ratings. Note 8: This is the internal weak pull-up (pull-down) current when driver output is disabled. If enabled, during receiving mode, this is the current required to switch the input from one state to another. Note 9: IOZ1 for CLKIN is max 60 µA if VPIN > VCC because the weak pull-down is enabled. www.national.com 60 LM8327

17.0 Registers

17.1 REGISTER MAPPING

17.1.1 Keyboard Registers

Table 110 shows the register map for keyboard functionality. TABLE 110. Register Map for Keyboard Functionality

17.1.2 Direct Key Registers

TABLE 111. Register Map for Direct Key Registers DKBDMIS Direct Key Masked Int.

17.1.3 PWM Timer Registers

RSTCTRL.TIMRST (see Section 14.3.5 RSTCTRL - System Reset Register). TABLE 112. Register Map for PWM Timer Functionality TIMMIS PWM Timer Masked Int.

17.1.4 System Registers

Reset using SWRESET (seeTable 45). TABLE 113. Register Map for System Control Functionality

17.1.5 Global Interrupt Registers

RSTCTRL - System Reset Register). TABLE 114. Register Map for Global Interrupt Functionality

17.1.6 GPIO Registers

TABLE 115. Register Map for GPIO Functionality

Register Name Description Register File Address Register Type ACCESS Size Default value Next RF Address GPIODIR2 GPIO I/O Direction 2 0xC8 R/W byte 0x00 0xC9 GPIOIS0 GPIO Int Sense Config 0 0xC9 R/W byte 0x00 0xCA GPIOIS1 GPIO Int Sense Config 1 0xCA R/W byte 0x00 0xCB GPIOIS2 GPIO Int Sense Config 2 0xCB R/W byte 0x00 0xCC GPIOIBE0 GPIO Int Both Edges Config 0 0xCC R/W byte 0x00 0xCD GPIOIBE1 GPIO Int Both Edges Config 1 0xCD R/W byte 0x00 0xCE GPIOIBE2 GPIO Int Both Edges Config 2 0xCE R/W byte 0x00 0xCF GPIOIEV0 GPIO Int Edge Select 0 0xCF R/W byte 0x00 0xD0 GPIOIEV1 GPIO Int Edge Select 1 0xD0 R/W byte 0x00 0xD1 GPIOIEV2 GPIO Int Edge Select 2 0xD1 R/W byte 0x00 0xD2 GPIOIE0 GPIO Interrupt Enable 0 0xD2 R/W byte 0x00 0xD3 GPIOIE1 GPIO Interrupt Enable 1 0xD3 R/W byte 0x00 0xD4 GPIOIE2 GPIO Interrupt Enable 2 0xD4 R/W byte 0x00 0xD5 GPIORIS0 GPIO Raw Int Status 0 0xD6 R byte 0x00 0xD7 GPIORIS1 GPIO Raw Int Status 1 0xD7 R byte 0x00 0xD8 GPIORIS2 GPIO Raw Int Status 2 0xD8 R byte 0x00 0xD9 GPIOMIS0 GPIO Masked Int Status 0 0xD9 R byte 0x00 0xDA GPIOMIS1 GPIO Masked Int Status 1 0xDA R byte 0x00 0xDB GPIOMIS2 GPIO Masked Int Status 2 0xDB R byte 0x00 0xDC GPIOIC0 GPIO Interrupt Clear 0 0xDC W byte 0xDD GPIOIC1 GPIO Interrupt Clear 1 0xDD W byte 0xDE GPIOIC2 GPIO Interrupt Clear 2 0xDE W byte 0xDF GPIOOME0 GPIO Open Drain Mode Enable 0 0xE0 R/W byte 0x00 0xE1 GPIOOMS0 GPIO Open Drain Mode Select 0 0xE1 R/W byte 0x00 0xE2 GPIOOME1 GPIO Open Drain Mode Enable 1 0xE2 R/W byte 0x00 0xE3 GPIOOMS1 GPIO Open Drain Mode Select 1 0xE3 R/W byte 0x00 0xE4 GPIOOME2 GPIO Open Drain Mode Enable 2 0xE4 R/W byte 0x08 0xE5 GPIOOMS2 GPIO Open Drain Mode Select 2 0xE5 R/W byte 0x00 0xE6 GPIOWAKE0 GPIO Wakeup Enable 0 0xE9 R/W byte 0x00 0xEA GPIOWAKE1 GPIO Wakeup Enable 1 0xEA R/W byte 0x00 0xEB GPIOWAKE2 GPIO Wakeup Enable 2 0xEB R/W byte 0x00 0xEC www.national.com 64 LM8327

TABLE 116. REGISTER LAYOUT - Control Bits in LM8327 Registers

Register Addr. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RSTCTRL 0x82 IRQRST TIMRST KBDRST GPIRST RSTINTCLR 0x84 IRQCLR CLKMODE 0x88 MODCTL[1:0] CLKCFG 0X89 CLKSRCSEL[1:0] CLKEN 0x8A CLKOUTEN[1:0] TIMEN DKBDEN KBDEN AUTOSLP 0x8B ENABLE AUTOSLPTI (Low) 0x8C UP-TIME [7:0] AUTOSLPTI (High) 0x8D UP-TIME [10:8] IRQST 0x91 PORIRQ KBD1RQ DKBDIRQ TIM2IRQ TIM1IRQ TIM01RQ GPIIRQ IOCFG 0xA7 IOCFGPM [7:0] IOPC0 (Low) 0xAA KPX3PR[1:0] KPX2PR[1:0] KPX1PR[1:0] KPX0PR[1:0] IOPC0 (High) 0xAB KPX7PR[1:0] KPX6PR[1:0] KPX5PR[1:0] KPX4PR[1:0] IOPC1 (Low) 0xAC KPY3PR[1:0] KPY2PR[1:0] KPY1PR[1:0] KPY0PR[1:0] IOPC1 (High) 0xAD KPY7PR[1:0] KPY6PR[1:0] KPY5PR[1:0] KPY4PR[1:0] IOPC2 (Low) 0xAE KPY11PR[1:0] KPY10PR[1:0] KPY9PR[1:0] KPY8PR[1:0] IOPC2 (High) 0xAF EXTIOPR[1:0] PWM2PR[1:0] PWM1PR{1:0] PWM0PR[1:0] GPIODATA0 0xC0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GPIOMASK0 0xC1 MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 GPIODATA1 0xC2 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 GPIOMASK1 0xC3 MASK15 MASK14 MASK13 MASK12 MASK11 DATA10 DATA9 DATA8 GPIODATA2 0xC4 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 GPIOMASK2 0xC5 MASK23 MASK22 MASK21 MASK20 MASK19 MASK18 MASK17 MASK16 GPIODIR0 0xC6 KPX7DIR KPX6DIR KPX5DIR KPX4DIR KPX3DIR KPX2DIR KPX1DIR KPX0DIR GPIODIR1 0xC7 KPY7DIR KPY6DIR KPY5DIR KPY4DIR KPY3DIR KPY2DIR KPY1DIR KPY0DIR GPIODIR2 0xC8 EXTIODIR PWM2DIR PWM1DIR PWM0DIR KP11DIR KPY10DIR KPY9DIR KPY8DIR GPIOIS0 0xC9 KPX7IS KPX6IS KPX5IS KPX4IS KPX3IS KPX2IS KPX1IS KPX0IS GPIOIS1 0xCA KPY7IS KPY6IS KPY5IS KPY4IS KPY3IS KPY2IS KPY1IS KPY0IS GPIOIS2 0xCB EXTIOIS PWM2IS PWM1IS PWM0IS KPY11IS KPY10IS KPY9IS KPY8IS GPIOIBE0 0xCC KPX7IBE KPX6IBE KPX5IBE KPX4IBE KPX3IBE KPX2IBE KPX1IBE KPX0IBE GPIOIBE1 0xCD KPY7IBE KPY6IBE KPY5IBE KPY4IBE KPY3IBE KPY2IBE KPY1IBE KPY0IBE GPIOIBE2 0xCE EXTIOIBE PWM2IBE PWM1IBE PWM0IBE KPY11IBE KPY10IBE KPY9IBE KPY8IBE GPIOIEV0 0xCF KPX7EV KPX6EV KPX5EV KPX4EV KPX3EV KPX2EV KPX1EV KPX0EV GPIOIEV1 0xD0 KPY7EV KPY6EV KPY5EV KPY4EV KPY3EV KPY2EV KPY1EV KPY0EV GPIOIEV2 0xD1 EXTIOIEV PWM2IEV PWM1IEV PWM0IEV KPY11IEV KPY10IEV KPY9IEV KPY8IEV GPIOIE0 0xD2 KPX7IE KPX6IE KPX5IE KPX4IE KPX3IE KPX2IE KPX1IE KPX0IE www.national.com 66 LM8327

Register Addr. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPIOIE1 0xD3 KPY7IE KPY6IE KPY5IE KPY4IE KPY3IE KPY2IE KPY1IE KPY0IE GPIOIE2 0xD4 EXTIOIE PWM2IE PWM1IE PWM0IE KPY11IE KPY10IE KPY9IE KPY8IE GPIORIS0 0xD6 KPX7RIS KPX6RIS KPX5RIS KPX4RIS KPX3RIS KPX2RIS KPX1RIS KPX0RIS GPIORIS1 0xD7 KPY7RIS KPY6RIS KPY5RIS KPY4RIS KPY3RIS KPY2RIS KPY1RIS KPY0RIS GPIORIS2 0xD8 EXTIORIS PWM2RIS PWM1RIS PWM0RIS KPY11RIS KPY10RIS KPY9RIS KPY8RIS GPIOMIS0 0xD9 KPX7MIS KPX6MIS KPX5MIS KPX4MIS KPX3MIS KPX2MIS KPX1MIS KPX0MIS GPIOMIS1 0xDA KPY7MIS KPY6MIS KPY5MIS KPY4MIS KPY3MIS KPY2MIS KPY1MIS KPY0MIS GPIOMIS2 0xDB EXTIOMIS PWM2MIS PWM1MIS PWM0MIS KPY11MIS KPY10MIS KPY9MIS KPY8MIS GPIOIC0 0xDC KPX7IC KPX6IC KPX5IC KPX4IC KPX3IC KPX2IC KPX1IC KPX0IC GPIOIC1 0xDD KPY7IC KPY6IC KPY5IC KPY4IC KPY3IC KPY2IC KPY1IC KPY0IC GPIOIC2 0xDE EXTIOIC PWM2IC PWM1IC PWM0IC KPY11IC KPY10IC KPY9IC KPY8IC GPIOOME0 0xE0 KPX7ODE KPX6ODE KPX5ODE KPX4ODE KPX3ODE KPX2ODE KPX1ODE KPX0ODE GPIOOMS0 0xE1 KPX7ODM KPX6ODM KPX5ODM KPX4ODM KPX3ODM KPX2ODM KPX1ODM KPX0ODM GPIOOME1 0xE2 KPY7ODE KPY6ODE KPY5ODE KPY4ODE KPY3ODE KPY2ODE KPY1ODE KPY0ODE GPIOOMS1 0xE3 KPY7ODM KPY6ODM KPY5ODM KPY4ODM KPY3ODM KPY2ODM KPY1ODM KPY0ODM GPIOOME2 0xE4 EXTIO-ODE PWM2-ODE PWM1-ODE PWM0-ODE KPY11ODE KPY10ODE KPY9 ODE KPY8 ODE GPIOOMS2 0xE5 EXTIO-ODM PWM2-ODM PWM1-ODM PWM0-ODM KPY11ODM KPY10ODM KPY9 ODM KPY8 ODM DEVTCODE 0xE6 DKEYCODE[4:0] DBOUNCE 0xE7 DBOUNCE[4:0] GPIOWAKE0 0xE9 KPX7WAKE KPX6WAKE KPX5WAKE KPX4WAKE KPX3WAKE KPX2WAKE KPX1WAKE KPX0WAKE GPIOWAKE1 0xEA KPY7WAKE KPY6WAKE KPY5WAKE KPY4WAKE KPY3WAKE KPY2WAKE KPY1WAKE KPY0WAKE GPIOWAKE2 0xEB EXTIOWAKE PWM2WAKE PWM1WAKE PWM0WAKE KPY11WAKE KPY10WAKE KPY9WAKE KPY8WAKE DIRECT0 0xEC DK07 DK06 DK05 DK04 DK03 DK02 DK01 DK00 DIRECT1 0xED DK15 DK14 DK13 DK12 DK11 DK10 DK09 DK08 DIRECT2 0xEE DK23 DK22 DK21 DK20 DK19 DK18 DK17 DK16 DIRECT3 0xEF DK25 DK24 DKBDRIS 0xF0 DRELINT DREVTINT DKBDMIS 0xF1 DMELINT DMEVTINT DKBDIC 0xF2 DEVTIC DKBDMSK 0xF3 DMSKELINT DMSKEINT MMASTER 0xF4 MSTADR[7:1] MMSTEN 67 www.national.com LM8327

www.national.com 68 LM8327

18.0 Physical Dimensions inches (millimeters) unless otherwise noted

Order Number LM8327JGR8 NOPB or LM8327JGR8X NOPB 69 www.national.com LM8327

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