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LM8323JGR8AXMX/NOPB

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LM8323 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface REVISED MARCH 2013

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 LM8323MobileI/OCompanionSupportingKeyscan,I/OExpansion,PWM,and ACCESS.busHostInterface Check forSamples: LM8323 1FEATURES Polling – ConfigurationofGeneral-purposeI/OPorts 2• Key Features – VariousInitializationOptions (Keypad Size,– Supports Keypad Matricesofup to8 × 12 etc.)Keys Plus 8 Special-function(SF)Keys for a Totalof104 Keys. SF Keys PullKeypad • Key Device Characteristics Scan InputsDirectlytoGround, Ratherthan – 1.8V± 180 mV Single-supplyOperation Connecting toa Keypad Scan Output. – On-chip Power-on Reset (POR) – Supports I2C-compatibleACCESS.bus – Watchdog TimerInterfaceinSlaveMode up to400 kHz – DedicatedSlow Clock Inputfor32 kHz(Fast-mode). – -40°C to+85°C IndustrialTemperature– Three Host-programmable PWM Outputs RangeUsefulforSmooth LED Brightness – 36-pincsBGA PackageModulation. – Supports General-purposeI/OExpansion APPLICATIONSon Pins Not OtherwiseUsed forKeypad or RotaryEncoder Interface. • CordlessPhones – Key-scan Event Storageina FIFO Bufferfor • Smart Handheld Devices up to15 Events. DESCRIPTION– Key Events,Errors,and Dedicated The LM8323 key-scan controlleris a dedicatedHardware InterruptsRequest Host Service deviceto unburden a host from scanninga matrix-by AssertingtheIRQ Output. addressedkeypad.Inaddition,theLM8323 provides– The CorrectReceptionofa Command May general-purposeI/O expansion,a rotaryencoderbe Assumed, ifNo ErrorisReported from interfaceand PWM outputsusefulfordynamic LEDtheLM8323 AfterReceivingit. brightnessmodulation. – Wake-up from HaltMode on any Matrix It communicates with the host through an I2C-Key-scan Event,any Use oftheSF Keys, or compatible ACCESS.bus interface.An interruptAny Activityon theACCESS.bus Interface, outputisavailableforsignalingkey-pressand key-or Any Change intheRotaryEncoder releaseevents.Communication frequenciesup to Counter Value (ifEnabled). 400 kHz (Fast-mode)bus speed are supported.The LM8323 supportsa predefinedset of commands.• Host-ControlledFunctions These commands enable a host device to keep– Three PWM Outputs controloverallfunctions.– PeriodofInactivitythatTriggersEntryinto HaltMode – Debounce Time forReliableKey Event Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 PIN ASSIGNMENTS Figure1. Top View 36-PincsBGA Package See Package Number NYB0036A SIGNAL DESCRIPTIONS Pin Function I/O Description A6 KP-X0 Input Wake-up input/Keyboardscanninginput0 A5 KP-X1 Input Wake-up input/Keyboardscanninginput1 F1 KP-X2 Input Wake-up input/Keyboardscanninginput2 KP-X3 Input Wake-up input/Keyboardscanninginput3 GPIO_13 I/O General-purposeI/Oport13 KP-X4 Input Wake-up input/Keyboardscanninginput4 GPIO_12 I/O General-purposeI/Oport12 KP-X5 Input Wake-up input/Keyboardscanninginput5 GPIO_11 I/O General-purposeI/Oport11 KP-X6 Input Wake-up input/Keyboardscanninginput6 GPIO_10 I/O General-purposeI/Oport10 KP-X7 Input Wake-up input/Keyboardscanninginput7 GPIO_09 Input General-purposeI/Oport9 C6 KP_Y0 Output Keyboardscanningoutput0 C5 KP-Y1 Output Keyboardscanningoutput1 B6 KP-Y2 Output Keyboardscanningoutput2 KP-Y3 Output Keyboardscanningoutput3 GPIO_08 I/O General-purposeI/Oport8 KP-Y4 Output Keyboardscanningoutput4 GPIO_07 I/O General-purposeI/Oport7 KP-Y5 Output Keyboardscanningoutput5 GPIO_06 I/O General-purposeI/Oport6 KP-Y6 Output Keyboardscanningoutput6 GPIO_05 I/O General-purposeI/Oport5 KP-Y7 Output Keyboardscanningoutput7 GPIO_04 I/O General-purposeI/Oport4 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com SIGNAL DESCRIPTIONS (continued) Pin Function I/O Description KP-Y8 Output Keyboardscanningoutput8 E3 SLOWCLKOUT Output 32.768kHz clockoutput GPIO_03 I/O General-purposeI/Oport3 KP-Y9 Output Keyboardscanningoutput9 D5 MUX2_IN1 Input Multiplexer2 input1 GPIO_02 I/O General-purposeI/Oport2 KP-Y10 Output Keyboardscanningoutput10 E6 MUX2_IN2 Input Multiplexer2 input2 GPIO_01 I/O General-purposeI/Oport1 KP-Y11 Output Keyboardscanningoutput11 F6 MUX2_OUT Output Multiplexer2 output GPIO_00 I/O General-purposeI/Oport0 E2 ACB_SDA I/O ACCESS.bus datasignal E1 ACB_SCL I/O ACCESS.bus clocksignal PWM_0 Output Pulse-widthmodulatedoutput0 MUX_IN1 Input Multiplexer1 input1 PWM_1 Output Pulse-widthmodulatedoutput1 MUX_IN2 Input Multiplexer1 input2 PWM_2 Output Pulse-widthmodulatedoutput2 MUX1_OUT Output Multiplexer1 output CONFIG_2 Input Slaveaddressselectinput2 GPIO_15 I/O General-purposeI/Oport15 CONFIG_1 Input Slaveaddressselectinput1 GPIO_14 I/O General-purposeI/Oport14 D1 XTAL_OUT Output 32.768kHz crystaloutput SLOWCLK Input 32.768kHz clock XTAL_IN Input 32.768kHz crystalinput F3 IRQ Output Interruptrequestoutput C1 RESET Input ResetInput A4,F4 VCC N/A VCC C3, C4, GND N/A Ground D3, D4

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 TERMINATION OF UNUSED SIGNALS TERMINATION OF UNUSED SIGNALS Signal Termination RESET ConnecttoVCC ifnotdrivenfroman externalSupervisorycircuit. ConnecttoVCC orGND througha pulluporpulldownresistorbecause theslaveaddressisselectedby theCONFIG_1 levelon thispin.Thispincannotbe leftunconnected. XTAL_IN Thispinisa high-impedanceinputand must be connectedtoVCC orGND ifitisunused. XTAL_OUT Thispinhas a weak pullupand can be leftopen-circuitifitisunused. These pinsarededicatedkeypad pins.Intheminimum configuration,thesepinsarekeypad inputswithweakKP-X[2:0] pullups. These pinsareinhigh-impedancemode afterpower-oninitialization.There aretwo ways tohandlethesepins ifunused:

ConnecttoVCC orGND.
Program as inputswithweak pullupsoroutputs. KP-X[7:3] Care must be takenwhen connectingtoVCC orGND. Erroneousparameterssentwiththe WRITE_PORT_SEL orWRITE_PORT_STATE commands couldcause excessivecurrentconsumption.A betterapproachistoleaveunused keyboardinputsopen-circuitand use theWRITE_PORT_SEL and WRITE_PORT_STATE commands toconfigurethepinsas inputswithweak pullupsoroutputs. KP-X7 can onlybe an input.Thispinshouldbe programmed as an inputwitha weak pullup. KP-Y[2:0] These pinsarededicatedkeypad pins.Intheminimum configuration,thesepinsarekeypad outputsdrivenlow. These pinsareinhigh-impedancemode afterpower-oninitialization.Therearetwo ways tohandlethesepins ifunused:
ConnecttoVCC orGND.
Program as inputswithweak pullupsoroutputsKP-Y[11:3] Care must be takenwhen connectingtoVCC orGND. Erroneousparameterssentwiththe WRITE_PORT_SEL orWRITE_PORT_STATE commands couldcause excessivecurrentconsumption.A betterapproachistoleaveunused keyboardinputsopen-circuitand use theWRITE_PORT_SEL and WRITE_PORT_STATE commands toconfigurethepinsas inputswithweak pullupsoroutputs. PWM_0, These pinsmust be connectedtoVCC orGND iftheyarenotused forany optionalfunctiondescribedinthe PWM_1 datasheet. PWM_2/ ConnecttoVCC orGND througha pulluporpulldownresistorbecause theslaveaddressisselectedby the CONFIG_2 levelon thispin.Thispincannotbe leftunconnected. IRQ Thispinmust be connected. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM8323

CONFIG_1 CONFIG_2 GPIO_14 GPIO_15 PWM_0 PWM_1 RESETVCC GND XTAL_IN XTAL_OUT IRQ ROT_IN_1 ROT_IN_2 ROT_IN_3 LM8323 SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com APPLICATION EXAMPLE Figure2. TypicalApplication

FEATURES

The applicationexample shown inFigure2 supportsthefollowingfeatures:

8 x 9 standardkeys.
8 specialfunctionkeys (SF keys)withwake-up capabilityby forcinga WAKE_INx pintoground.Pressinga SF key overridesany otherkey inthesame row.
ACCESS.bus (I2C-compatible)interfaceforcommunicationwiththehost.
Hardware IRQ interrupttohosttosignalkeypad,rotaryencoder,error,and statusevents.By default,thisis an open-drainoutput,so an externalpullupresistormay be requiredtoavoidfalseassertion.The hostcan program thisoutputforpush-pullmode, inwhichcase thepullupmightnotbe required,ifthehostcan ignore a falseassertionbeforetheLM8323 has been programmed.
Two LEDs drivenby PWM outputswithprogrammable ramp-up and ramp-down. PWM_2 (sharedwith GPIO_15 and CONFIG_2) couldbe used as an additionalPWM driverporttocontrola thirdexternalLED.
RotaryencoderinterfacesharespinswithKP-Y9, KP-Y10, and KP-Y11. For largerkeyboardconfigurations (suchas QWERTY layouts),therotaryencoderinterfaceisnotavailable.
ACCESS.bus addressisselectedby theCONFIG_1 and CONFIG_2 inputs.These pinsmay alsobe used as GPIO pins afterresetinitializationhas occurred.IfextraGPIO pins are not needed, CONFIG_1 and CONFIG_2 may be tieddirectlytoVCC and GND.
CrystalpinsXTAL_IN and XTAL_OUT may be used toconnecttoan external32.768kHz crystalorreceive an external32.768kHz clockinputforrunningthePWM peripheral.By default,thePWM isclockedby an on- chipclocksource. CLOCKS
System Clock (mclk)— The system clockisintherangeofabout21 MHz (±7%) typical.Thisclockisused todrivetheI2C-compatibleserialACCESS bus and istheinputclockforotherfunctionblocks.
Processingand Command ExecutionClock (tC )— The internalprocessingisbased on a 2MHz clock.This clockisderivedfromtheSystem Clock.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013

InternalPWM Clock — The internalPWM clockisa fixedscaleddown clock(÷ 64) oftheProcessingand Command ExecutionClock.This clockiscloseto 32 kHz which isin a good range to source the PWM functionblockas an alternativetoan externalclocksource.
External32.768kHz Clock — drivenintotheSLOWCLK input.May be used internallyas thetimebasefor thePWM and drivenon theSLOWCLKOUT output.
External32.768 kHz Crystal— connected across the XTAL_IN and XTAL_OUT pins (XTAL_IN is an alternatefunctionoftheSLOWCLK pin).May be used internallyas thetimebaseforthePWM and drivenon theSLOWCLKOUT output. Figure3. Clock Architecture INTERNAL EXECUTION CYCLE The Processing-and Command -executionclockisabout2MHz. ThisclockisstoppedinHaltmode, whichonly occursundercontroloftheLM8323. However,thehostcan settheperiodofinactivitywhichcauses thedevice toenterHaltmode. ExitfromHaltmode can be triggeredby any oftheseevents:
Occurrenceofa key-pressorkey-releaseevent.
A Startconditiondrivenby thehoston theACCESS.bus interface.
Any change totherotaryencodercountervalue(iftheinterfaceisenabled).
AssertionoftheRESET input. Afterreset,thedefaulttimebaseforthePWM outputsistheinternalexecutionclockdividedby 64. BUFFERED CLOCK The timebaseforthePWM comes fromany ofthreesources:
PrescaledinternalExecutionclock.
External32.768kHz clockreceivedon theSLOWCLK input.
On-chiposcillatorwithan externalcrystalconnectedacrossXTAL_IN and XTAL_OUT. Any ofthesesourcesmay be bufferedand drivenon theSLOWCLKOUT output.The clockbufferisenabledwith theWRITE_CLOCK command. IfXTAL_IN isnotused itmust be terminatedtoVCC orGND. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com CLOCK CONFIGURATION Table 1 shows the clock configurationsavailableby loadingthe clock configurationregisterwith the WRITE_CLOCK command. The WRITE_CLOCK command must be issuedonlyonce duringsysteminitialization. Thiscommand isused tooverridethedefaultsettings. Table1.Clock ConfigurationRegister 7 6 5 4 3 2 1 0

0 SLOWCLKOUT 0 0 SLOWCLKEN 0 RCPWM

0 DisableSLOWCLKOUT buffer. SLOWCLKOUT 1 EnableSLOWCLKOUT buffer. 0 External32.768kHz crystalisinstalledbetween theXTAL_IN and XTAL_OUT pins. SLOWCLKEN 1 External32.768kHz clockisreceivedon theSLOWCLK pin,orno 32.768kHz clockisrequired. 00 On-chipRC clockdividedby 64 drivesthePWM and clockbuffer.

01 Reserved

10 Reserved

11 External32.768kHz clockorcrystaldrivesthePWM and clockbuffer. The SLOWCLKOUT signalisan alternatefunctionof the pin used forthe KP-Y8 scanningoutputand the GPIO_03 port.IftheSLOWCLKOUT functionisenabled,theseotherfunctionsofthepinareunavailable. RESET The LM8323 may be resetby eitheran externalreset,RESET command, or an internallygeneratedpower-on reset(POR) signal.The RESET inputmust notbe allowedtofloat.IftheexternalRESET inputisnotused,it must be connectedtoVCC, eitherdirectlyorthrougha pull-upresistor. EXTERNAL RESET The deviceentersa resetstateimmediatelywhen theRESET inputisdrivenlow.RESET must be heldlow fora minimum of700 ns toensurea validreset.IfRESET isassertedatpower-on,itmust be heldlow untilVCC rises above the minimum operatingvoltage(1.62V).Ifan RC circuitisused to driveRESET, itmust have a time constant5 times(5×)greaterthantheVCC risetimetothislevel. When RESET goes low,the I/Oportsare initializedimmediately,any observeddelaybeingonlypropagation delay.When theRESET pingoes high,theLM8323 comes outoftheresetstatewithinabout1400 ns. POWER-ON RESET (POR) The POR circuitisalwaysenabled.When VCC risesabove thePOR thresholdvoltageVPOR (about1.2–1.5V),an on-chipresetsignalisasserted.The VCC risetimemust be greaterthan20 µs and lessthan10 ms, otherwise theon-chipresetsignalmay deassertbeforeVCC reachestheminimum operatingvoltage.WhileVCC isbelow VPOR ,theLM8323 isheldinresetand a timerclockedby theon-chipRC clockispresetwith0xFF (256 clock cycles).When VCC reachesa valuegreaterthanVPOR ,thetimerstartscountingdown. When itunderflows,the on-chipresetsignalisdeassertedand theLM8323 beginsoperation. PIN CONFIGURATION AFTER RESET Table2 shows thepinconfigurationafterreset.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 Table2. Pin ConfigurationAfterReset Pins AfterReset AfterLM8323 Initialization KP-X00 KP-X01 High-impedancemode. Inputmode withan on-chippullupenabled. KP-X02 KP-X03 KP-X04 KP-X05 High-impedancemode. High-impedancemode, untilhostconfiguresthem as keypad inputsorGPIO. KP-X06 KP-X07 KP-Y00 KP-Y01 High-impedancemode. Activedrivelow. KP-Y02 KP-Y03 KP-Y04 KP-Y05 KP-Y06 KP-Y07 High-impedancemode. High-impedancemode, untilhostconfiguresthem as keypad outputsorGPIO. KP-Y08 KP-Y09 KP-Y10 KP-Y11 CONFIG_1 The ACCESS.bus slaveaddressmust be selectedwithexternalpulluporHigh-impedancemode. pulldownresistorsordirectconnectionstoVCC orGND.CONFIG_2 IRQ High-impedancemode. Activedrivelow. PWM_0 PWM_1 High-impedancemode. High-impedancemode. PWM_2 ACB_SDA Open-drainmode. Open-drainmode. ACB_SCL XTAL_IN High-impedancemode. High-impedancemode. TerminatetoVCC orGND ifnotused. XTAL_OUT Weak pullupdevice. Weak pullupdevice. RESET High-impedancemode. High-impedancemode. DEVICE CONFIGURATION AFTER RESET AftertheLM8323 has completeditsresetinitialization,itwillhave thefollowinginternalconfiguration:

PWM Clock:The PWM clocksourceistheon-chipclockdividedby 64.Thisremainsineffectuntilchanged by a hostcommand.
Keypad Size:3 × 3.
RotaryEncoder Interface:disabled.
DigitalMultiplexers:disabled.
IRQ:enabled,activelow.
NOINIT Bit:set.
Debounce Time:3 scan cycles(about12 milliseconds).
ActiveTime:500 milliseconds. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com NOTE When FW6 versiondevicesreceivea RESET command theIRQ lineissethighand held highfor60 ms and thenpulledlow toshow thedevicewas successfullyresetand isready tobe used. CONFIGURATION INPUTS The statessampled from the CONFIG_1 and CONFIG_2 inputsduringresetselectthe ACCESS.bus address used by theLM8323, as shown inTable3.The addressoccupiesthehighseven bitsofthefirstbyteofa bus transaction,withtheLSB (shown as X below)indicatingthedirectionoftransfer. Table3. Bus Address Selection CONFIG_1 CONFIG_2 Bus Address 0 0 1000 010X 0 1 1000 011X 1 0 1000 100X 1 1 1000 101X When thesepinsareused as GPIO ports,thedesignmust ensurethattheyhave thedesiredstatesduringreset. For example,a 100-kΩ resistorto ground can impose a logic0 duringresetwithoutinterferingwithnormal operationas a GPIO port. INITIALIZATION The LM8323 waitsfora WRITE_CFG command from the host.Duringthistime,IRQ isassertedto request servicefromthehost.Figure4 describesthebehavioroftheLM8323 followingreset. Figure4. LM8323 InitializationBehavior Figure5 shows thetimingofIRQ relativetoa RESET or POR eventand theWRITE_CFG command. 100 µs aftera RESET or POR event,IRQ isassertedand any READ_INT command willreturnan interruptcode with theNOINIT bitset.90 µs aftera WRITE_CFG command isreceived,IRQ isdeasserted.

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bit set? No YesIs KEYPAD bit set? Read keypad events. READ_FIFO No YesIs ROTATOR bit set? Read rotation steps. READ_ROTATOR No YesIs a PWMxEND bit set? Service PWM channel. Check error code. READ_ERROR Initialize configuration. WRITE_CFG Configure clocks. WRITE_CLOCK Specify keypad size. SET_KEY_SIZE Configure GPIO pins. WRITE_PORT_STATE WRITE_PORT_SEL Check interrupt code. READ_INT Initialize keypad scan timing. SET_ACTIVE SET_DEBOUNCE NoIs NOINIT bit set? Yes NoAre NOINIT,ERROR, and COMMAND bits clear? Yes Check interrupt code. READ_INT NoYes Send any command. READ_PORT_STATE PWM_WRITE, etc. Host Initialization Is IRQ low? Service error condition. If the error code reports a FIFOOVR or KEYOVR error, then the FIFO buffer must be unloaded to clear the FIFO. If this is not done, the LM8323 will not store any new events in the FIFO. Any data unloaded from the FIFO after the error interrupt should be ignored. LM8323 www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 Figure5. IRQ Reset Timing AftersendingtheWRITE_CFG command, thehostmust send a seriesofcommands toconfiguretheLM8323, as shown inFigure6.(See lefthand side.) ThisFlow - diagramillustratesalsothebasichostcommunicationstepswhich thehostmust executeupon an IRQ requestreceivedfrom the LM8323 duringoperation.Such requestswillbe made from the LM8323 as a resultofkey pressedevents,thedetectionofan error,theterminationofa PWM cycleand others. Figure6. Host-SideLM8323 Initialization Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com INITIALIZATIONEXAMPLE Inthefollowingexample,theLM8323 isconfiguredas:

Keypad matrixconfigurationis8 × 4.
Rotaryencoderinterfaceenabled.
GPIO_03 throughGPIO_07 areavailabletouse as GPIO pins.
GPIO_03 isan outputdrivenlow.
GPIO_4 and GPIO_5 areoutputsdrivenhigh.
GPIO_06 and GPIO_07 areinputswithweak pulldowns.
GPIO_14 and GPIO_15 areinputswithweak pullups.
The PWM clocksourceistheinternalexecutionclockdividedby 64 (about32 kHz). Most of these settingscan be verifiedby executingcommands such as READ_CONF, READ_PORT_SEL, READ_CLOCK, etc. ALL GPIO pinstatescan be readusingtheREAD_PORT_STATE command, withoutregardtowhetherthepinis an inputoran output. An open-drainsignalcan be createdby alternatingbetween inputmode and drivingtheoutputlow. AllGPIOs can sinkand source16 mA when configuredas an output. Command Encoding Parameter 1 Parameter 2 Description Selects36-pinpackage and disablesthetwo digitalWRITE_CFG 0x81 0x40 multiplexers. SLOWCLKOUT disabled,no external32.768kHz clockWRITE_CLK 0x93 0x08 required,PWM clocksourceisinternal. SET_KEY_SIZE 0x90 0x84 Selectsa keypad matrixsizeof8 × 4. Setstheactivetimetoabout300 milliseconds(75× 4SET_ACTIVE 0x8B 0x4B milliseconds). Setsthekey debouncingtimetoabout12 milliseconds(3× 4 SET_DEBOUNCE 0x8F 0x03 ms).Thisisactuallythedefaultand wouldnothave tobe performed. ConfigureGPIO_03, GPIO_04, and GPIO_05 as outputs. WRITE_PORT_SEL 0x85 0x00 0x38 ConfigureGPIO_06, GPIO_07, GPIO_14, and GPIO_15 as inputs. Setthedirectionforthepullup/pulldowndeviceson GPIO_06 WRITE_PULL_DOWN 0x84 0x00 0x3F and GPIO_07 topulldown.Setthedirectionforthe pullup/pulldowndeviceson GPIO_14 and GPIO_15 topullup. SetGPIO_04 and GPIO_05 todrivehigh.EnablethepullupsWRITE_PORT_STATE 0x86 0xC0 0xF0 on GPIO_06, GPIO_07, GPIO_14, and GPIO_15. HALT MODE The fullystaticarchitectureoftheLM8323 allowsstoppingtheinternalRC clockinHaltmode, which reduces power consumptiontotheminimum level.Figure7 shows thecurrentinHaltmode atthemaximum VCC (1.98V) from25°C to+85°C.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 Figure7. HaltCurrentvs.Temperature at1.98V Haltmode isenteredwhen no key-pressevent,key-releaseevent,change intherotaryencodercountervalueor ACCESS.bus activityisdetectedfora certainperiodoftime(bydefault,500 ms).The mechanism forentering Haltmode isalwaysenabledinhardware,butthehostcan program theperiodofinactivitywhichtriggersentry intoHaltmode. NOTE When FW4 versiondevicesentertheHaltmode thereisapproximatelya 33% chance the devicemay miss key eventsduringtheperiodof3ms beforeenteringHaltmode until3ms afterenteringHaltmode resultinginlostkey events.Thiswas correctedinFW6 devices so that100% ofallkey eventsarecaptured,even as thedeviceisenteringHaltmode. ACCESS.bus ACTIVITY When theLM8323 isinHaltmode, any activityon theACCESS.bus interfacewillcause theLM8323 toexitfrom Haltmode. However,theLM8323 willnotbe abletoacknowledgethefirstbus cycleimmediatelyfollowingwake- up fromHaltmode. Itwillrespondwitha negativeacknowledgement,and thehostshouldthenrepeatthecycle. The LM8323 willbe preventedfromenteringHaltmode ifitsharesthebus withperipheralsthatarecontinuously active.For lowestpower consumption,theLM8323 shouldonlysharethebus withperipheralsthatrequirelittle orno bus activityaftersysteminitialization. KEYPAD INTERFACE EVENT CODE ASSIGNMENT Afterpower-onresetand hostinitialization,theLM8323 startsscanningthekeypad.Itstaysactivefora default time of about 500 ms afterthe lastkey is released,afterwhich itentersHalt mode to minimizepower consumption(typically<9 µA standbycurrent). Table 4 liststhe codes assignedto the matrixpositionsencoded by the hardware.Key-pressevents are assignedthe codes listedinTable 4, but withthe MSB set.When a key isreleased,the MSB of the code is clear. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com Table4. Keypad MatrixCode Assignments KP-Y0 KP-Y1 KP-Y2 KP-Y3 KP-Y4 KP-Y5 KP-Y6 KP-Y7 KP-Y8 KP-Y9 KP-Y10 KP-Y11 SF Keys KP-X0 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0F KP-X1 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1F KP-X2 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2F KP-X3 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3F KP-X4 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4F KP-X5 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5F KP-X6 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6F KP-X7 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7F When the rotaryencoder interfaceisenabled,KP-Y9, KP-Y10, and KP-Y11 (bolded inKeypad MatrixCode Assignments)become unavailableforkeypad scanning,whichlimitsthekeypad toa maximum sizeof8 × 9 + 8 SF keys. The codes are loadedintothe FIFO bufferinthe orderinwhich theyoccurred.Table 5 shows an example sequence ofevents,and Figure8 shows theresultingsequence ofeventcodes loadedintotheFIFO buffer. Table5. Example Sequence ofEvents Event Number Event Code Event on Input DrivenOutput Description 1 0xC5 KP-X4 KP-Y4 Key ispressed 2 0xB2 KP-X3 KP-Y1 Key ispressed 3 0x45 KP-X4 KP-Y4 Key isreleased 4 0x32 KP-X3 KP-Y1 Key isreleased 5 0x81 KP-X0 KP-Y0 Key ispressed 6 0x5F KP-X5 N/A SF Key isreleased 7 0x01 KP-X0 KP-Y0 Key isreleased 8 0x00 N/A N/A Indicatesend ofstoredevents Figure8. Example Event Codes Loaded inFIFO Buffer KEYPAD SCAN CYCLES The LM8323 startsnew scan cyclesatfixedtimeintervalsofabout4 milliseconds.Ifa change inthestateofthe keypad isdetected,thekeypad isrescannedaftera debounce delay.When thestatechange has been reliably captured,itisencoded and writtentotheFIFO buffer. Figure9 shows therelationshipbetween a KP-Yx outputand a KP-Xx inputovermultiplescan cyclesduringa key pressevent.Between scan cycles,theKP-Yx outputsthatare specifiedby theSET_KEY_SIZE command (0x90)forkeypad scanningaredrivenlow.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 Figure9. Keypad Scan Cycles Duringa scan cycle,onlyone KP-Yx outputpinwillbe drivenlow atany time,whiletheothersaredrivenhighor undriven.At thetimescaleused inFigure9,thelow phase ofa KP-Yx outputduringa scan cycleisnotvisible. The KP-Xx inputpinsarepulledhighby weak pullups. There are capacitiveloadson the KP-Xx inputsand KP-Yx outputsdue to protectioncircuits,wiring,etc.The LM8323 insertsdelaystoallowcompletechargingordischargingoftheseloadsbeforesamplingtheinputlevels on theKP-Xx inputs.The maximum parasiticloadcapacitanceon theKP-Xx inputsis5nF. Afterdetectinga key-pressor key-releaseevent,the debounce time specifiedby the SET_DEBOUNCE command (0x8F)setstheminimum timeforconfirmingtheeventbeforetheIRQ outputisasserted. Ifmore thantwo keys arepressedsimultaneously,thepatternofkey closuresmay be ambiguous,inwhichcase thetheinterruptcode indicatesan errorand theIRQ outputisasserted(ifenabled). The SF keys connectKP-Xx inputsdirectlytoground.There can be up toeightSF keys.Ifany ofthesekeys are pressed,otherkeysthatuse thesame KP-Xx pinareignored. Timing Parameters Two timingparametersaffectscanningofthekeypad:

Debounce Time — minimum delaybetween detectinga keypad event and confirmingthe event before assertingIRQ. The defaultdebounce timeis3 scan cycles(about12 milliseconds),but the hostcan set valuesintherange1–255 cycles(4–1020 milliseconds).
ActiveTime — periodwithoutdetectinga statechange inthekeypad or rotaryencoderthattriggersentry intoHaltmode, duringwhichkeypad scanningissuspended.The defaultactivetimeis500 milliseconds,but the host can set itvaluesin the range 4–1020 milliseconds.The activetime must be greaterthan the debounce time. MultipleKey Pressings Ifmore thantwo keys arepressedatthesame time,theLM8323 storesallkey pressedand releasedeventsin theFIFO bufferinthesequence inwhichtheywere decoded. Formultiplekey pressingsthefollowingcircumstanceshave tobe respected:
A multiplekey-presseventisgiveniftwo or more key-presseventsare reportedbutno correspondingkey- releaseevent.
Withtheactivitytimesetbetween theminimum and maximum time(4ms to1 second)itisnotsafetodetect two simultaneouskey pressingsinone inputrow (seeFigure10 on thelefthand side.)
Ifallkey pressings(twoor more) are locatedindifferentinputrows (seeFigure10 on therighthand side) thenthekey pressedeventswillbe correctlyfoundintheFIFO bufferwithoutany restriction. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com Figure10. Simultaneous Keys Pressed

Inordertosecurelydetectand storethekey codes ofsimultaneouskey pressingsinthesame inputrow the followingprecautionsmust be takenfromthehostside: As soon as thehostdevicehas detecteda key pressedeventthehostmust send theSET_ACTIVE Command withtheparametersetto“00”.ThiswillpreventtheLM8323 fromenteringHALT mode. Ifallkeyboardeventsare resolved(no remainingkey pressedstatusintheLM8323 anymore) thenthehostmust send theSET_ACTIVE Command againwiththeparametersettingthedesireddurationfortheactivetime.ThiswillenabletheLM8323 toenterlowpower HALT mode once theactivitytimehas passed withoutdetectingany events.
Once one or more key (pressedand/orreleased)eventshave been read from thehostwiththehelpofthe READ FIFO command therearetwo conditionscleaningtheFIFO buffercontents: – A second executionoftheREAD FIFO Command or, – A new key eventdetectedfromtheLM8323. EXAMPLE KEYPAD CONFIGURATION Figure11 shows an 8 × 4 keypad matrix.Thisconfigurationoccupiesallscanninginputs(KP-X0 throughKP-X7) and fourscanningoutputs(KP-Y0 throughKP-Y3).The remainingscanningoutputsKP-Y4 throughKP-Y11 are availableforuse as GPIO pins.Enablingtherotaryencoderinterfacereducesthenumber ofavailableGPIO pins toKP-Y4 throughKP-Y8. Figure11. Keypad InterfaceExample

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 In the example above, threekeys (Up, Down, and Select)are connectedas SF keys (connecteddirectlyto ground).Althoughthey couldhave shared the KP-Xx inputsused withthe scanned keys,the advantage of placingthem on theirown KP-Xx inputsisthatitallowsscanningthekeypad whilean SF key ispressed.Ifan SF key sharesa KP-Xx inputwithany scanned keys,pressingtheSF key preventstheLM8323 from readingthe scanned keys. The SET_KEY_SIZE command includesa databytethatspecifiesthekeypad size.The upper4 bitsofthedata byte specifythe number of KP-Xx inputs,and the lower4 bitsspecifythe number of KP-Yx outputs.The minimum number ofinputsand outputsis3.Therefore,theminimum keypad configurationsupports3 × 3 + 3 SF keys (totalof12 keys).The maximum number ofKP-Xx inputsis8,and themaximum number ofKP-Yx pinsis 12.AllKP-Xx and KP-Yx pinsnotused forthekeyboardinterfacecan be used forgeneral-purposeI/O. For theexample shown inFigure11,theSET_KEY_SIZE command would specify8 KP-Xx inputsand 4 KP-Yx outputs. GENERAL-PURPOSE I/OPORTS Any unused KP-Xx and KP-Yx pins may be used as general-purposeI/O (GPIO) port pins. The WRITE_PORT_SEL (0x85)command selectsthe portdirection,in which a clearbitin the parameterto the command selectstheinputdirectionand a setbitselectstheoutputdirection. The WRITE_PORT_STATE (0x86)command selectseitherthe portlevelwhen configuredas output(by the WRITE_PORT_SEL command) or when configuredas an inputselectsbetween a high-impedanceinputor an inputwitha pullupor pulldowndevice.The selectionbetween pullupor pulldowndevicesiscontrolledby the parameterbytestotheWRITE_PULL_DOWN (0x84)command. Clearbitsintheparameterbytesselectpullup devices,whilesetbitsselectpulldowndevices. Table 6 shows the GPIO port configurationsselected by the bits in the WRITE_PORT_SEL, WRITE_PORT_STATE, and WRITE_PULL_DOWN command parameters. Table6. GPIO PortControlBits WRITE_PORT_SEL WRITE_PORT_STATE WRITE_PULL_DOWN Description 0 0 x High-ImpedanceInput 0 1 0 InputwithPullupDevice 0 1 1 InputwithPulldownDevice 1 0 x Output,DriveLow 1 1 x Output,DriveHigh Any pinsused as GPIO portsmust be configuredaftertheperipheralconfigurationhas been initializedwiththe WRITE_CFG command (0x81)and the keypad configurationhas been initializedwiththe SET_KEY_SIZE command (0x90).The defaultkeypad configurationafterresetisa 3 × 3 keyboardmatrix.The defaultGPIO configurationisan inputwiththepullupdisabled. USING THE CONFIG_X PINS FOR GPIO The CONFIG_1 and CONFIG_2 pinsareavailableforuse as GPIO pinsafterpower-onorreset.However,stable statesmust be providedon these pinsduringpower-on or resetto selectthe I2C-compatibleACCESS.bus address. Externalpullupor pulldownresistorscan be used topulleitherCONFIG_x pinlow,whileretainingtheabilityto driveittoanotherstatewhen used as a GPIO pin. CONFIG_2 has two alternatefunctions,inadditiontoGPIO. Itcan be configuredas a multiplexeroutputusing theWRITE_CFG command (0x81),inwhichcase itwillnotbe availableas a GPIO pin.Itcan alsobe configured as a PWM output,whichalsowouldoverrideitsuse as a GPIO pin. USING THE ROT_IN_X PINS FOR GPIO The rotaryencoder interfaceuses alternatefunctionsof KP-Y9, KP-Y10, and KP-Y11. The maximum keypad sizeisautomaticallyreducedtoa 8 × 9 matrixiftherotaryencoderinterfaceisenabled. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com GPIO TIMING When a WRITE_PORT_STATE command (0x86)isreceived,the GPIO outputsdo not change to theirnew statesimmediatelyorsimultaneously.The firstone changes 54 µs afterthecommand isacknowledged,and the otherschange atintervalsof7.3µs,as shown inFigure12. Figure12. GPIO PortStateChange Timing ROTARY ENCODER INTERFACE A three-wireinterfaceisprovidedforan externalrotaryencoder.SettingtheROTEN bitwiththeWRITE_CFG command enables the interfaceand the ROT_IN_x inputs,which are alternatefunctionsof certainkeypad scanningpins.The ROT_IN_x inputsare bidirectionalsignalsused totestthestatusofswitchesinan external rotaryencoder,as shown inFigure13.

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ROT_IN_1 VCC Drive Low Sense ROT_IN_2 VCC Drive Low Sense ROT_IN_3 LM8323 www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 Figure13. RotaryEncorder ExternalInterface The ROT_IN_x inputsarealternatefunctionsofKP-Y9, KP-Y10, and KP-Y11. When therotaryencoderinterface isenabled,thesekeypad scanningoutputsarenotavailableforkeypad interface. Steps which correspondtoclockwiserotationincrementa counter,whilecounterclockwisestepsdecrementthe counter,as shown intheexample sequence inTable7.The READ_ROTATOR command returnsa databyte whichindicatestheaccumulatedcountsincethecounterwas lastread. Table7. RotaryEncoder Example Sequence Switch 1-2 Switch 2-3 Switch 3-1 Action Counter Closed Closed Open Increment 00000000 Open Closed Open No Change 00000000 Open Closed Closed Increment 00000001 Open Open Closed No Change 00000001 Closed Open Closed Increment 00000010 Closed Open Open No Change 00000010 Closed Closed Open Increment 00000011 Open Closed Open No Change 00000011 Open Closed Closed Increment 00000100 Open Open Closed No Change 00000100 Open Closed Closed Decrement 00000011 Open Closed Open No Change 00000011 Closed Closed Open Decrement 00000010 Closed Open Open No Change 00000010 Closed Open Closed Decrement 00000001 Open Open Closed No Change 00000001 Open Closed Closed Decrement 00000000 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com Table7. RotaryEncoder Example Sequence (continued) Switch 1-2 Switch 2-3 Switch 3-1 Action Counter Open Closed Open No Change 00000000 Closed Closed Open Decrement 11111111 Closed Open Open No Change 11111111 Closed Open Closed Decrement 11111110 Open Open Closed No Change 11111110 Open Closed Closed Decrement 11111101 The valueofthedatabyteisintwo’s complement form,inwhichpositivevaluesindicateclockwiserotationand negativevaluesindicatecounterclockwiserotation.Thisisshown intheexample when thecounterdecrements belowzero. A rotaryencodereventwillonlywake up theLM8323 fromHaltmode ifitchanges thecountervalue. PWM OUTPUT GENERATION Three pulse-widthmodulated(PWM) outputsare providedwithadvanced capabilitiesforramp-up and ramp- down ofthePWM dutycycleand executionofsimpletocomplex command sequences.These capabilitiesare supportedby threeindependentscript-executionengines capable of autonomous operationaftersetup and launchby thehost.Figure14 shows thearchitectureofa script-executionengine. Figure14. PWM ScriptExecutionEngine The hosthas threecommands forinterfacingtothescriptexecutionengine.The followingcommands arealways associatedwithone particularPWM channel:

PWM_WRITE — loadone word intothescriptcommand fileata specifiedaddress.
PWM_START — startexecutionofthescript.
PWM_STOP — stopexecutionofthescript.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 NOTE The PWM_STOP command mightnottakeimmediateeffectifthecurrentcommand being executedisa command withlongexecutiontime.Ifa PWM_STOP command issentwhen the PWM engineisrunninga longRAMP command, the PWM willonlystopafterthe RAMP iscompleted. The scriptcommands have theirown fixed-length16-bitformatand encodingunrelatedto the variable-length, byte-basedformatused forhostcommands. A scriptcommand issentby thehosttotheLM8323 as a parameter tothePWM_WRITE command. AnotherparametertothePWM_WRITE command specifiesan addressinthe scriptcommand fileforreceivingthecommand. COMMAND QUEUE Afterthehostissuesa PWM_START command, scriptcommands are read from thescriptcommand fileintoa command queue which consistsof a command fileoutputregister,command buffer,and activecommand register.Thisallowsone command tobe activewhileanothercommand isqueued inthecommand buffer,which allowsseamlessback-to-backcommand execution. A command loadedintothecommand fileoutputregisterissynchronizedtothe32.768kHz clockand storedin thecommand buffer.Ifno command iscurrentlyactive,thecommand passes throughtotheactivecommand register.In thiscase,anothercommand can be read from the scriptcommand file,which isqueued in the command buffer.On completionof the currentlyactivecommand, the contentsof the command bufferare transferredtotheactivecommand register,and thecommand buffermay thenreceivea new command. The hostdoes nothave directaccesstoany oftheregistersinthecommand queue.The operationswhichread scriptcommands from the scriptcommand fileoccur automaticallyafterthe host issuesthe PWM_START command. Scriptexecutionstopswhen the hostsends a PWM_STOP command or when the scriptengineexecutesan END command. Executingan END command assertsIRQ tothehost. PWM TIMER OPERATION The timersimplement a fixed256-cycleperiodwitha programmable duty cycleand programmable ramp- up/ramp-downofthedutycycle.Figure15 shows thearchitectureofa PWM timer. Figure15. PWM Timer Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com The periodcounterisa freerunning8-bitup-counterwhichstartscountingwhen thescriptcommand fileissues thefirstRAMP command. An END command stopstheperiodcounter. The dutycycleofthePWM outputiscontrolledby theramp counter.IfthePWM periodcounterisactive,the PWM outputsignalisassertedwhiletheperiodcounterhas a valuelessthanorequaltothevalueoftheramp counter. The ramp countercan incrementor decrementata ratecontrolledby theprescalerand steptimecounter.The prescalerselectsa factorof 16 or 512 fordividingdown the frequencyof the 32.768 kHz clock.The ramp countersaturatesateither0x00 or0xFF dependingon theramp direction. The number of incrementor decrement stepsisspecifiedby the INCREMENT fieldof the RAMP command, whichisloadedintothestepcounter.Even iftheramp counterhitsitssaturationvalue,therequestednumber of steps willbe performed.An optionenables assertionof the IRQ outputto the host afterthe laststep is performed. PWM SCRIPT COMMANDS Table8 summarizesthescriptcommands. Table8.PWM ScriptCommands Command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRESRAMP 0 STEPTIME SIGN INCREMENTCALE SET_PWM 0 1 0 PWMVALUE GO_TO_ 0START BRANCH 1 0 1 LOOPCOUNT 0 ADDRESS RESEND 1 1 0 0 0ET TRIGGER 1 1 1 WAITTRIGGER SENDTRIGGER 0 RAMP COMMAND The RAMP command generatesa duty-cycleramp startingfrom the currentvalue.At each step,the ramp counterisincrementedordecrementedby one,unlessithas reacheditsitssaturationvalue(0xFF forincrement, or 0x00 fordecrement).The timeforone stepiscontrolledby the PRESCALE bitand STEPTIME field.The minimum timeforone stepis0.49milliseconds.and themaximum timeisabout1 second,whichsupportsboth veryfastand veryslow ramps. The INCREMENT fieldspecifiesthe number of stepsto be executedby the command. The maximum valueis126,whichcorrespondstohalfoffullscale. There aretwo specialcases intheinstructionencoding.Ifallbitsand fieldsare0,itisinterpretedas theGO TO START command. Ifthe STEPTIME fieldis0 but any otherbitor fieldisnon-zero,itisinterpretedas the SET_PWM command. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 PRESCALE STEPTIME SIGN INCREMENT

Bitor Field Value Description 0 Dividethe32.768kHz clockby 16 PRESCALE 1 Dividethe32.768kHz clockby 512 STEPTIME 1–63 Number ofprescaledclockcyclesperstep

0 Incrementramp counter

1 Decrement ramp counter

INCREMENT 1–126 Number ofstepsexecutedby thisinstruction

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 SET_PWM COMMAND The SET_PWM command loadstheramp counterfromthe8-bitDUTYCYCLE fieldintheinstruction. NOTE Only 0x00 and 0xFF are validvaluesforthe dutycycleinSET_PWM command. Other valuescan be establishedby initializingthedutycycletoeither100% or0% followedby a RAMP command. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 DUTYCYCLE Bitor Field Value Description 0 Dutycycleis0%. DUTYCYCLE 255 Dutycycleis100%. GO_TO_START COMMAND The GO_TO_START command jumps tothefirstcommand inthescriptcommand file. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRANCH COMMAND The BRANCH command jumps tothespecifiedcommand inthescriptcommand file,withtheoptionoflooping fora specifiednumber ofrepetitions.Nestedloopsarenotallowed. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 LOOPCOUNT 0 ADDRESS Field Value Description 0 Loop untila STOP PWM SCRIPT command isissuedby thehost. LOOPCOUNT 1–63 Number ofrepetitionstoperform,biasedby -1.The rangeis0–62 repetitions. Branchdestinationaddressinthescriptcommand file.Ifthisfieldisgreaterthan59,no loopingADDRESS 0–59 willbe performed. END COMMAND The END command terminatesscriptexecutionand assertsan interrupttothehostiftheRESET bitissetto“1” or“0”. IftheEND command isexecutedwiththeRESET bitsetto“1”,thePWM outputwillbe disabled.IftheRESET bitis“0” when executingtheEND command, thePWM channelremainsactivewiththefixeddutycycleitwas lastsetto. NOTE Ifa PWM channeliswaitingforthetrigger(lastexecutedcommand was "TRIGGER") and the scriptexecutionishaltedthen the "END" command can’t be executedbecause the previouscommand isstillpending.Thisisan exception- inthiscase theIRQ signalwill notbe asserted. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 RESET 0 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com Bit Value Description 0 PWM_x outputisactivewhen scriptexecutionterminates. RESET 1 PWM_x outputisTristatewhen scriptexecutionterminates. TRIGGER COMMAND Triggersare used to synchronizeoperationsbetween PWM channels.A TRIGGER command thatsends a triggertakessixteen32.768 kHz clockcycles,and a command thatwaitsfora triggertakesat leastsixteen 32.768kHz clockcycles. A TRIGGER command thatwaitsfora trigger(ortriggers)willstallscriptexecutionuntilthetriggerconditionsare satisfied.Then,itwillclearthetrigger(s)and continuetothenextcommand. When a triggerissent,itisstoredby thereceivingchanneland can onlybe clearedwhen thereceivingchannel executesa TRIGGER command thatwaitsforthetrigger. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 WAITTRIGGER SENDTRIGGER 0 Field Value Description 000xx1 Waitfortriggerfromchannel0 WAITTRIGGER 000x1x Waitfortriggerfromchannel1 0001xx Waitfortriggerfromchannel2 000xx1 Send triggertochannel0 SENDTRIGGER 000x1x Send triggertochannel1 0001xx Send triggertochannel2 PWM SCRIPT EXAMPLE This example shows a complex ramping sequence thatuses triggersfor synchronization.Three scripts implementtheexample.Figure16 shows thePWM outputsforthisexample. Figure16. PWM Outputs

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 PWM Channel 0 Script Script PWM_WRITE PWM_WRITE PWM_WRITE ScriptCommand DescriptionParameter 1 Parameter 2 Parameter 3 CommandAddress 0x00 0x01 0x40 0x00 SET_PWM Initializechannelfor0% dutycycle 0x01 0x05 0xE2 0x00 TRIGGER Waitfortriggerfromchannel2 0x02 0x09 0x07 0x7E RAMP Ramp up by 126 steps 0x03 0x0D 0x07 0x7E RAMP Ramp up by 126 steps 0x04 0x11 0x07 0xFE RAMP Ramp down by 126 steps 0x05 0x15 0x07 0xFE RAMP Ramp down by 126 steps 0x06 0x19 0xA1 0x82 BRANCH Loop 2 timesstartingataddress0x02 0x07 0x1D 0xC8 0x00 END Terminatescriptand assertIRQ tohost PWM Channel 1 Script Script PWM_WRITE PWM_WRITE PWM_WRITE ScriptCommand DescriptionParameter 1 Parameter 2 Parameter 3 CommandAddress 0x00 0x02 0x40 0xFF SET_PWM Initializechannelfor100% dutycycle 0x01 0x06 0xE2 0x00 TRIGGER Waitfortriggerfromchannel2 0x02 0x0A 0x0F 0xFE RAMP Ramp down by 126 steps 0x03 0x0E 0x0F 0xFE RAMP Ramp down by 126 steps 0x04 0x12 0x0F 0x7E RAMP Ramp up by 126 steps 0x05 0x16 0x0F 0x7E RAMP Ramp up by 126 steps 0x06 0x1A 0xA2 0x02 BRANCH Loop 3 timesstartingataddress0x02 0x07 0x1E 0xE0 0x08 TRIGGER Send triggertochannel2 0x08 0x22 0xC8 0x00 END Terminatescriptand assertIRQ tohost PWM Channel 2 Script Script PWM_WRITE PWM_WRITE PWM_WRITE ScriptCommand DescriptionParameter 1 Parameter 2 Parameter 3 CommandAddress 0x00 0x03 0x40 0x00 SET_PWM Initializechannelfor0% dutycycle 0x01 0x07 0x03 0x7E RAMP Ramp up by 126 steps 0x02 0x0B 0x03 0x7E RAMP Ramp up by 126 steps 0x03 0x0F 0x03 0xFE RAMP Ramp down by 126 steps 0x04 0x13 0x03 0xFE RAMP Ramp down by 126 steps Send triggerstochannels0 and 1,0x05 0x17 0xE1 0x06 TRIGGER waitfortriggerfromchannel1 0x06 0x1B 0x03 0x7E RAMP Ramp up by 126 steps 0x07 0x1F 0x03 0x7E RAMP Ramp up by 126 steps 0x08 0x23 0x03 0xFE RAMP Ramp down by 126 steps 0x09 0x27 0x03 0xFE RAMP Ramp down by 126 steps 0x0A 0x2B 0xC8 0x00 END Terminatescriptand assertIRQ tohost Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com SELECTABLE SCRIPT EXAMPLE Multiplescriptscan be placedina singlebuffer.The scriptwhich isexecutedisselectedby theaddressinthe parametertothePWM_START command (0x96). Script PWM_WRITE PWM_WRITE PWM_WRITE ScriptCommand DescriptionParameter 1 Parameter 2 Parameter 3 CommandAddress 0x00 0x01 0x40 0x00 SetPWM_0 to0% dutycycle 0x01 Script1 0x05 0x0F 0x33 Ramp up 51 steps 0x02 0x09 0xC0 0x00 Keep channelat20% dutycycle 0x03 0x0D 0x40 0xFF SetPWM_0 to100% dutycycle 0x04 Script2 0x11 0x0F 0xD5 Ramp down 85 steps 0x05 0x15 0xC0 0x00 Keep channelat66.6% dutycycle 0x06 0x19 0x40 0x00 SetPWM_0 to0% dutycycle 0x07 0x1D 0x07 0x7E Ramp up 126 steps 0x08 0x21 0x07 0x7E Ramp up 126 steps Script3 0x09 0x25 0x07 0xFE Ramp down 126 steps 0x0A 0x29 0x07 0xFE Ramp down 126 steps 0x0B 0x2D 0xA5 0x07 Loop tentimestoscriptaddress0x07 SwitchPWM_0 off(script3 automaticallyenters0x0C Script4 0x31 0xC8 0x00 here) 0x0D 0x35 0x40 0x00 SetPWM_0 to0% dutycycle 0x0E Script5 0x39 0x07 0x25 Ramp up 37 steps 0x0F 0x3D 0xC0 0x00 Keep channelat14.5% dutycycle 0x10 Script6 0x41 0x40 0x00 SetPWM_0 to0% dutycycle 0x11 0x45 0x01 0x40 Ramp up 64 steps (Alternates0x12 0x49 0x3F 0x7E Ramp up 126 steps between 25% and 0x13 0x4D 0x3F 0xFE Ramp down 126 steps75% dutycycle) 0x14 0x51 0xA0 0x12 Alwaysbranchtoscriptaddress0x12 0x15 0x3B To seta fixeddutycycleon a PWM channelrequires3 steps(seescript1 fordutycyclesfrom0% to49% and script2 fordutycyclesfrom51% to100%). To keep a PWM channelactiveprovidinga fixeddutycycleon itsoutput,thescriptmust terminatewiththeEND command leavingthe RESET bitclear.To switchthischanneloff,the hostmust send anotherPWM_START command (0x96followedby theparameterbytes)triggeringthesinglecommand describedinscript4.ThisEND command willsettheRESET bitand thededicatedPWM outputwillbe disabled. Script3 willautomaticallyenterintothiscommand when the10 loopsoframpingup and down areexecuted. Script7 can be finishedby two commands:

PWM_STOP command withparameter0x01
PWM_START command withparameter0x31 (startPWM_0 fromaddress0x0C torunscript4) The scriptaddressisthephysicaladdresstobe used fromBRANCH instructionsinsidethescriptfilebuffer.The parameter1 bytecontainsthesame addresswiththe2 channelbitsappended and willbe associatedwiththe PWM_START command.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 DIGITAL MULTIPLEXERS Two 2:1multiplexersareprovidedforhost-controlleddigitalswitching.SettingtheMUX1EN orMUX2EN bitswith the WRITE_CFG command enables the correspondingmultiplexerand itsinputand outputsignals,which overridesany otherfunctionswhichmay use thesepins.The MUX1 signalsarealternatefunctionsofthePWM_x outputs.The MUX2 signalsarealternatefunctionsofthreeKP-Yx pinssharedwiththerotaryencoderinterface, so MUX2 isunavailablewhen theinterfaceisused. The dataselectinputsforthemultiplexersarecontrolledby theMUX1SEL and MUX2SEL bits,whicharewritten by theWRITE_CFG command. Ifitisimportanttoavoidmomentarilypassingan incorrectinputtotheoutput,the selectbitmust be loadedwitha firstWRITE_CFG command beforesendinga second WRITE_CFG command to settheenablebit.The truthtableforthemultiplexersisshown inTable9. Table9. DigitalMultiplexerFunctionTable MUXxEN Bit MUXxSEL MUXx_IN2 MUXx_IN1 MUXx_OUT Bit Pin Pin Pin 1 0 X 0 0 1 0 X 1 1 1 1 0 X 0 1 1 1 X 1 MUXx_OUT0 X X X notenabled HOST INTERFACE The two-wireACCESS.bus interfaceis used to communicate with a host.The ACCESS.bus interfaceis compatiblewiththeI2C bus standard.The LM8323 operatesas a bus slaveat400 kHz (Fastmode). AllcommunicationwiththeLM8323 overtheACCESS.bus interfaceisinitiatedby thehost,usuallyinresponse toan interruptrequest(IRQ low)assertedby theLM8323. The LM8323 may requestservicefrom thehostby assertingtheIRQ interruptoutput. START AND STOP CONDITIONS Everytransferisprecededby a Startconditionora Repeated Startcondition.The latteroccurswhen a command followsimmediatelyupon anothercommand withoutan interveningStop condition.A Stop conditionindicatesthe end oftransmission.Everybyteisacknowledgedby thereceiver. Figure17. Startand Stop Conditions CONTINUOUS COMMAND STRINGS A hostdevicemay send a continuousstringofcommands usingtheRepeated Startcondition,whichwould block anotherACCESS.bus devicefromgainingcontrolofthebus.AfterPower-On thehostdevicemust send multiple commands to initializethe LM8323 device.A minimalcommand stringwillincludethe commands shown in Table10. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LM8323

A more comprehensivecommand stringmay includetheadditionalcommands shown inTable11. serviceand consequentlycouldtriggera physicalRESET tothedevice. sequencesforSCL frequencies> 100 kHz. Table 12. In the firstbyteof a bus transaction,a 7-bitaddressplusa directionbitare broadcastby the bus pinscannotbe leftunconnected. SET_KEY_SIZE command, whichconsistsofan addressbyte,a command byte,and one databyte. bitis0 on writesfromthehosttotheslaveand 1 on readsfromtheslavetothehost. The second bytesends thecommand. The SET_KEY_SIZE command is0x90.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 The thirdbytesends thedata,inthiscase specifyingthenumber ofrows and columnsforthekeypad. Figure18. Host WriteCommand HOST READ COMMANDS Some host commands includeone or more data bytes read from the LM8323. Figure 19 shows a READ_PORT_SEL command whichconsistsofan addressbyte,a command byte,a second addressbyte,and two databytes. The firstaddressbyteissentwiththedirectionbitdrivenlow toindicatea writetransactionofthecommand to the LM8323. The second addressbyteissentwiththe directionbitundriven(pulledhigh)to indicatea read transactionofthedatafromtheLM8323. The Repeated Startconditionmust be repeatedwhenever theslaveaddressor thedirectionbitischanged.In thiscase,thedirectionbitischanged. The bus master can send any number of Repeated Startconditionswithoutreleasingcontrolof the bus.This techniquecan be used toimplementatomictransactions,inwhich thebus mastersends a command and then readsa registerwithoutallowingany otherdevicetogetcontrolofthebus between theseevents. The data issentfrom the slaveto the hostinthe fourthand fifthbytes.The fifthbyteends witha negative acknowledgement(NACK) toindicatetheend ofthedata. Figure19. Host Read Command INTERRUPTS The IRQ outputmay be assertedon theseconditions:

Any new key-eventafterthe lastinterruptwas assertedbut not yetacknowledged by readingthe interrupt code.
Any change inthestateoftherotaryencoderinputs. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LM8323

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Terminationofa PWM script(END command).
Any errorcondition,whichisindicatedby theerrorcode. INTERRUPT CODE The interruptcode isread and acknowledgedwiththeREAD_INT command (0x82).Thiscommand clearsthe code and deassertstheIRQ output.Table13 shows theformatoftheinterruptcode. Table13. InterruptCode 7 6 5 4 3 2 1 0 PWM2END PWM1END PWM0END NOINIT ERROR 0 ROTATOR KEYPAD Bit Description PWM2END An END scriptcommand was executedby PWM channel2. PWM1END An END scriptcommand was executedby PWM channel1. PWM0END An END scriptcommand was executedby PWM channel0. NOINIT The LM8323 iswaitingforan initializationsequence. ERROR An errorconditionoccurred. ROTATOR A statechange was detectedintherotaryencoderinputs. KEYPAD A key-pressorkey-releaseeventoccurred. ERROR CODE Ifthe LM8323 reportsan error,the READ_ERROR command (0x8C) isused to read the errorcode. This command clearstheerrorcode.Table14 shows theformatoftheerrorcode. Table14. ErrorCode 7 6 5 4 3 2 1 0

0 FIFOOVR 0 0 0 KEYOVR CMDUNK BADPAR

FIFOOVER EventoccurredwhiletheFIFO was full. KEYOVR More thantwo keyswere pressedsimultaneously. CMDUNK Not a validcommand. BADPAR Bad command parameter. WAKE-UP FROM HALT MODE Any bus transactioninitiatedby thehostmay encountertheLM8323 deviceinHaltmode orbusy withprocessing data,such as controllingtheFIFO bufferorexecutinginterruptserviceroutines. LM8323 shows the case in which the host sends a command whilethe LM8323 isin Haltmode (Internal executionclockisstopped).Any activityon theACCESS.bus wakes up theLM8323, butitcannotacknowledge thefirstbus cycleimmediatelyafterwake-up. The hostdrivesa Startconditionfollowedby seven addressbitsand a R/W bit.The hostthenreleasesSDA for one clockperiod,so thatitcan be drivenby theLM8323. IftheLM8323 does notdriveSDA low duringthehighphase oftheclockperiodimmediatelyaftertheR/W bit, thebus cycleterminateswithoutbeingacknowledged(shown as NACK inFigure20).The hostthenabortsthe transactionby sendinga Stop condition.Afterabortingthebus cycle,thehostmay thenretrythebus cycle.On the second attempt,the LM8323 willbe ableto acknowledge the slaveaddress,because itwillbe inActive mode. Alternatively,theI2C specificationallowssendinga START byte(00000001),whichwillnotbe acknowledgedby any device.Thisbytecan be used towake up theLM8323 fromHaltmode. The LM8323 may alsostallthebus transactionby pullingtheSCL low,whichisa validbehaviordefinedby the I2C specification.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 Figure20. LM8323 Responds withNACK, Host RetriesCommand HOST COMMANDS Function Cmd Dir Data Bytes Description nnnn nnnn Read themanufacturercode (nnnnnnnn)and thedeviceREAD_ID 0x80 R revisionnumber (pppppppp).pppp pppp WRITE_CFG 0x81 W nnnn nnnn Writethehardwareconfigurationregister. Read theinterruptcode,deasserttheIRQ output,and clear READ_INT 0x82 R nnnn nnnn thecode.(IftheNOINIT bitisset,itremainssetand IRQ remainsasserteduntila WRITE_CFG command isreceived.) RESET 0x83 W nnnn nnnn ResettheLM8323. Errorifnnnn nnnn isnot0xAA. nnnn nnnn Selectpullup(0)orpulldown(1)directionfortheWRITE_PULL_DOWN 0x84 W correspondinggeneral-purposeI/O(GPIO)portpins.pppp pppp nnnn nnnn Selectinput(0)oroutput(1)forthecorrespondinggeneral-WRITE_PORT_SEL 0x85 W purposeI/O(GPIO)portpins.pppp pppp nnnn nnnn Forpinsconfiguredas inputs,0 selectshigh-impedance WRITE_PORT_STATE 0x86 W mode and 1 enablesa weak pullup.Forpinsconfiguredas pppp pppp outputs,each bitspecifiesthelogicleveldrivenon thepin. nnnn nnnn READ_PORT_SEL 0x87 R Read thedirectionofthecorrespondingGPIO portpins. pppp pppp nnnn nnnn READ_PORT_STATE 0x88 R Read thestateon thecorrespondingGPIO portpins. pppp pppp Up to15 event Read an eventfromtheFIFO.READ_FIFO 0x89 R codes Maximum of14 eventcodes storedintheFIFO. Up to15 event Repeatsa FIFO readwithoutadvancingtheFIFO pointer,forRPT_READ_FIFO 0x8A R codes example toretrya readafteran error. SetthetimeduringwhichtheLM8323 staysactivebefore enteringHaltmode. The activetimemust be greaterthantheSET_ACTIVE 0x8B W nnnn nnnn debounce time.The defaulttimeis500 milliseconds.The validrangeis1255.Activetime= n × 4 milliseconds. READ_ERROR 0x8C R nnnn nnnn Read and cleartheerrorcode. READ_ROTATOR 0x8E R nnnn nnnn Read accumulatedrotationstepssincepreviousread. Setthetimeforrescanningthekeypad afterdetectinga key- pressorkey-releaseeventtoverifytheevent.The defaultSET_DEBOUNCE 0x8F W nnnn nnnn timeis12 milliseconds.The validrangeis1255.Debounce time= n × 4 millisecondsand must notexceed activetime. SET_KEY_SIZE 0x90 W nnnn pppp Setkeypad size.nnnn = KP-Xx pins,pppp = KP-Yx pins READ_KEY_SIZE 0x91 R nnnn pppp Read keypad size.nnnn = KP-Xx pins,pppp = KP-Yx pins READ_CFG 0x92 R nnnn nnnn Read thehardwareconfigurationregister. WRITE_CLOCK 0x93 W nnnn nnnn Writetheclockconfigurationregister. READ_CLOCK 0x94 R nnnn nnnn Read theclockconfigurationregister. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com Function Cmd Dir Data Bytes Description Writea command tothePWM scriptcommand file. nn = PWM channelnumber (01,10,or11) PWM_WRITE 0x95 W aaaa aann aaaaaa = addressinscriptcommand file(0-59) pppp pppp pppp pppp = highbyteofscriptcommand qqqq qqqq qqqq qqqq = lowbyteofscriptcommand PWM_START 0x96 W aaaa aann Startscripton channelnn (01,10,or11)ataddressaaaaaa. PWM_STOP 0x97 W 0000 00nn Stopscripton channelnn (01,10,or11). SPACER NOTE The data bytes which followthe command can be reads (towardthe host)or writes (towardtheLM8323). Inthecase oftheREAD_FIFO and RPT_READ_FIFO commands, the number of data bytesisvariable,withthe lasttransactionindicatedby returninga negativeacknowledgement(NACK). READ_ID COMMAND The READ_ID command consistsofa command byte(0x80)fromthehostand two databytesfromtheLM8323. The firstdatabytereturnsthemanufacturercode,and thesecond bytereturnsthedevicerevisionlevel. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 MANUFACTURER REVISION WRITE_CFG COMMAND The WRITE_CFG command consistsofa command byte(0x81)and a databytefromthehost.The databyteis loadedintothehardwareconfigurationregister.The defaultstateofthisregisteris0x80. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 IRQPST ROTEN 0 0 MUX2EN MUX2SEL MUX1EN MUX1SEL Bit Value Description 0 IRQ isan open-drainoutput. IRQPST 1 IRQ isa push-pulloutput. 0 Rotaryencoderinterfacedisabled. ROTEN Rotaryencoderinterfaceenabled.ThisselectionenablestheROT_IN_x inputswhicharealternate1 functionsofcertainKP-Yx pins. 0 MUX2_OUT outputdisabled. MUX2EN 1 MUX2_OUT outputenabled.Thisoverridesany otherfunctionavailableon thispin. 0 IftheMUX2 EN bitis1,theMUX2_IN1 inputdrivestheMUX2_OUT output. MUX2SEL 1 IftheMUX2 EN bitis1,theMUX2_IN2 inputdrivestheMUX2_OUT output. 0 MUX1_OUT outputdisabled. MUX1EN 1 MUX1_OUT outputenabled.Thisoverridesany otherfunctionavailableon thispin. 0 IftheMUX1 EN bitis1,theMUX1_IN1 inputdrivestheMUX1_OUT output. MUX1SEL 1 IftheMUX1 EN bitis1,theMUX1_IN2 inputdrivestheMUX1_OUT output.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 READ_INT COMMAND The READ_INT command consistsofa command byte(0x82)fromthehostand a databytefromtheLM8323. The databyteistheinterruptcode.Readingtheinterruptcode acknowledgestheinterrupt(whichdeassertsIRQ) and clearstheinterruptcode.An exceptiontothisbehavioroccursiftheNOINIT bitisset,inwhichcase IRQ will notbe deassertedand theinterruptcode willnotbe cleareduntila WRITE_CFG command isreceived. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 0 PWM2END PWM1END PWM0END NOINIT ERROR 0 ROTATOR KEYPAD Bit Value Description 0 No interruptfromPWM channel2. PWM2END 1 An END scriptcommand was executedby PWM channel2. 0 No interruptfromPWM channel1. PWM1END 1 An END scriptcommand was executedby PWM channel1. 0 No interruptfromPWM channel0. PWM0END 1 An END scriptcommand was executedby PWM channel0. 0 Normal operation. NOINIT 1 LM8323 iswaitingfortheinitializationsequence. 0 No errorconditionisindicated. ERROR 1 An errorconditionoccurred. 0 No statechange intherotaryencoderinputsisindicated. ROTATOR 1 A statechange was detectedintherotaryencoderinputs. 0 No key-pressorkey-releaseeventisindicated. KEYPAD 1 A key-pressorkey-releaseeventoccurred. RESET COMMAND The RESET command consistsof a command byte(0x83)and one data bytefrom the host.The command causes a reset,identicaltoan externalreset.The databytemust be 0xAA, otherwiseno resetwilloccurand an errorconditionwillbe signalled. NOTE When FW6 versiondevicesreceivea RESET command theIRQ lineissethighand held highfor60 ms, thenpulledlow toshow thedevicewas successfullyresetand isreadyto be used. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 WRITE_PULL_DOWN COMMAND The WRITE_PORT_SEL command consistsofa command byte(0x84)and two databytesfrom thehost.The databytesconfigurethepullup/pulldowndevice(ifenabled)forthecorrespondinggeneral-purposeI/Oportsas pullups(0)orpulldowns(1).The firstdatabytecontrolsportsGPIO_15 throughGPIO_08, and thesecond byte controlsportsGPIO_07 throughGPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 0 0 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_09 GPIO_08 GPIO_07 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description 0 GPIO portpinpullup/pulldowndeviceisa pullup. GPIO_xx 1 GPIO portpinpullup/pulldowndeviceisa pulldown. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com WRITE_PORT_SEL COMMAND The WRITE_PORT_SEL command consistsofa command byte(0x85)and two databytesfrom thehost.The databytesconfigurethecorrespondinggeneral-purposeI/Oportsas inputs(0)oroutputs(1).The firstdatabyte controlsportsGPIO_15 throughGPIO_08, and thesecond bytecontrolsportsGPIO_07 throughGPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 0 1 0 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_08 GPIO_07 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description 0 GPIO portpinisan input. GPIO_xx 1 GPIO portpinisan output. The GPIO_09 portpincan onlybe configuredas an inputwithweak pullup/pulldowndevice. WRITE_PORT_STATE COMMAND The WRITE_PORT_STATE command consistsofa command byte(0x86)and two databytesfromthehost.For general-purposeI/Oportsconfiguredas inputs,thedatabytesselectwhethertheinputsarehigh-impedance(0) orhave a weak pullup(1).For portsconfiguredas outputs,thedatabytescontrolthestatedrivenon theoutput. The firstdata byte controlsportsGPIO_15 throughGPIO_08, and the second byte controlsportsGPIO_07 throughGPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 1 0 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_09 GPIO_08 GPIO_07 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description IftheGPIO portpinisan input,pullupdeviceisdisabled.IftheGPIO portpinisan output,itis0 drivenlow. GPIO_xx IftheGPIO portpinisan input,pullupdeviceisenabled.IftheGPIO portpinisan output,itis1 drivenhigh. READ_PORT_SEL COMMAND The READ_PORT_SEL command consistsofa command byte(0x87)fromthehostand two databytesfromthe LM8323. The databytesindicatethedirectionconfiguredforthecorrespondingports,eitherinput(0)or output (1).The firstdatabytecontrolsportsGPIO_15 throughGPIO_08, and thesecond bytecontrolsportsGPIO_07 throughGPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 1 1 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_09 GPIO_08 GPIO_07 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description 0 GPIO portpinisan input. GPIO_xx 1 GPIO portpinisan output.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 READ_PORT_STATE COMMAND The READ_PORT_STATE command consistsofa command byte(0x88)fromthehostand two databytesfrom the LM8323. The data bytesindicatethe stateson the correspondingports.The firstdata bytecontrolsports GPIO_15 throughGPIO_08, and thesecond bytecontrolsportsGPIO_07 throughGPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_09 GPIO_08 GPIO_07 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description IftheGPIO portpinisan input,pullupisdisabled.IftheGPIO portpinisan output,itis0 drivenlow. GPIO_xx IftheGPIO portpinisan input,pullupisenabled.IftheGPIO portpinisan output,itis1 drivenhigh. READ_FIFO COMMAND The READ_FIFO command consistsofa command byte(0x89)sentfromthehostand a variablenumber ofdata bytesreceivedfrom theLM8323. The LM8323 willprovidedatauntiltheFIFO isempty.The lastdatabyteis indicatedby itsvalue(0x00)and a negativeacknowledgement(NACK) on theACCESS.bus interface.The data bytescorrespondtokey-pressand key-releaseevents,as describedinTable4. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 1 FIFODATA 0x00 Field Value Description 0xxxxxxx Key-releaseevent. FIFODATA 1xxxxxxx Key-pressevent. RPT_READ_FIFO COMMAND The RPT_READ_FIFO command consistsofa command byte(0x8A)and fromthehostand a variablenumber ofdatabytesfrom theLM8323. Thiscommand providesthesame dataas a previousREAD_FIFO command, but withoutadvancing the FIFO pointer.Itmay be used to recoverfrom an errorencounteredduringa READ_FIFO command. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 0 FIFODATA 0x00 Field Value Description 0xxxxxxx Key-releaseevent. FIFODATA 1xxxxxxx Key-pressevent. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com SET_ACTIVE COMMAND The SET_ACTIVE command consistsofa command byte(0x8B)and a databytefromthehost.Thiscommand setsthetimethattheLM8323 staysactivewithoutdetectinga key-press,key-releaseor rotaryencoderevent beforeenteringHaltmode. The defaultactivetimeis500 milliseconds.The hostcan program ACTIVETIME from 4–1020 millisecondswitha granularityof4 milliseconds. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 1 ACTIVETIME Field Value Description 0 Haltmode isdisabled. ACTIVETIME 1–255 Activetime= n × 4 milliseconds. READ_ERROR COMMAND The READ_ERROR command consistsof a command byte (0x8C) from the host and a data byte from the LM8323. Afterreadingan interruptcode thatindicatesan errorcondition,thiscommand isused toreadan error code thatindicatesthecause oftheerrorcondition. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 1 0 0 0 FIFOOVR 0 0 0 KEYOVR CMDUNK BADPAR Bit Value Description 0 No FIFO overrunoccurred. FIFOOVR 1 EventoccurredwhiletheFIFO was full. 0 No keypad overrunoccurred. KEYOVR 1 More thantwo keyswere pressedsimultaneously. 0 No invalidcommand was encountered. CMDUNK 1 Not a validcommand. 0 No bad parameterwas encountered. BADPAR 1 Bad command parameter. READ_ROTATOR COMMAND The READ_ROTATOR command consistsofa command byte(0x8E)from thehostand a databytefrom the LM8323. The databyteisa signedtwo'scomplement valuewhichindicatestheaccumulatednumber ofrotation stepsofan externalrotaryencodersincethelasttimetheREAD_ROTATOR command was executed. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 1 1 0 ROTATION Field Value Description Clockwiserotationisindicatedby a positivevalue.Counterclockwise ROTATION −128 to+127 movement isindicatedby a negativevalue. SET_DEBOUNCE COMMAND The SET_DEBOUNCE command consistsof a command byte (0x8F)and a data byte from the host.This command setsthe timethatthe LM8323 waitsbeforerescanningthe keypad to confirma key-pressor key- releaseevent.The defaultdebounce time is12 milliseconds.The host can program DEBOUNCETIME from 4–1020 millisecondswitha granularityof4 milliseconds.The DEBOUNCETIME must notexceed theactivetime setwiththeSET_ACTIVE command. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 1 1 1 DEBOUNCETIME

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 Field Value Description DEBOUNCETIME 1–255 Activetime= n × 4 milliseconds. SET_KEY_SIZE COMMAND The SET_KEY_SIZE command consistsof a command byte (0x90)and a data byte from the host.This command specifiesthekeypad sizeintermsofthenumber ofKP-Xx inputsand KP-Yx outputswhichareused. Any unused KP-Xx and KP-Yx pinsmay be used forgeneral-purposeI/O.The minimum valueforeitherfieldis3, whichcorrespondstoa keypad configurationthatsupports3 × 3 + 3 SF keys(totalof12 keys). The maximum number of KP-Xx inputsis8, and the maximum number of KP-Yx outputsis12. Ifthe digital multiplexerMUX2 or the rotaryencoder interfaceisused,the maximum number of KP-Yx outputsis9. Ifthe SLOWCLKOUT pinisused,themaximum number is8. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 0 0 0 KP-X KP-Y Field Value Description KP-X 3–8 Number ofKP-Xx inputs. KP-Y 3–12 Number ofKP-Yx outputs. READ_KEY_SIZE COMMAND The READ_KEY_SIZE command consistsof a command byte(0x91)from the hostand a data bytefrom the LM8323. The hostcan issuethecommand atany timetoreadtheconfigurationofthekeypad. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 0 0 1 KP-X KP-Y Field Value Description KP-X 3–8 Number ofKP-Xx inputs. KP-Y 3–12 Number ofKP-Yx outputs. READ_CFG COMMAND The READ_CFG command consistsofa command byte(0x92)fromthehostand a databytefromtheLM8323. The databytereturnsthesettingsinthehardwareconfigurationregister.The defaultstateofthisregisteris0x80. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 0 1 0 0 ROTEN 0 0 MUX2EN MUX2SEL MUX1EN MUX1SEL Bit Value Description 0 Rotaryencoderinterfacedisabled. ROTEN Rotaryencoderinterfaceenabled.ThisselectionenablestheROT_IN_x inputs,whichare1 alternatefunctionsofcertainKP-Yx pins. 0 MUX2_OUT outputdisabled. MUX2EN 1 MUX2_OUT outputenabled.Thisoverridesany otherfunctionavailableon thispin. 0 IftheMUX2 EN bitis1,theMUX2_IN1 inputdrivestheMUX2_OUT output. MUX2SEL 1 IftheMUX2 EN bitis1,theMUX2_IN2 inputdrivestheMUX2_OUT output. 0 MUX1_OUT outputdisabled. MUX1EN 1 MUX1_OUT outputenabled.Thisoverridesany otherfunctionavailableon thispin. 0 IftheMUX1 EN bitis1,theMUX1_IN1 inputdrivestheMUX1_OUT output. MUX1SEL 1 IftheMUX1 EN bitis1,theMUX1_IN2 inputdrivestheMUX1_OUT output. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com WRITE_CLOCK COMMAND The WRITE_CLOCK command consistsof a command byte (0x93)and a data byte from the host.This command setstheclockconfiguration,as describedinTable1. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 0 1 1 CONFIGURATION READ_CLOCK COMMAND The READ_CLOCK command consistsof a command byte (0x94)from the host and a data byte from the LM8323. Thiscommand readsbits7:2oftheclockconfiguration,as describedinTable1. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 1 0 0 CONFIGURATION 1 0 PWM_WRITE COMMAND The PWM_WRITE command consistsof a command byte (0x95)and threedata bytesfrom the host.The command writesa 16-bitscriptcommand intoa specifiedaddressinthe scriptcommand fileof the specified PWM channel. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 1 0 1 ADDRESS CH COMMAND Bit Value Description ADDRESS 0–59 LocationinthePWM scriptcommand file. 01 PWM channel0. CH 10 PWM channel1. 11 PWM channel2. PWM_START COMMAND The PWM_START command consistsofa command byte(0x96)and a databytefromthehost.Thiscommand startsexecutionofthescriptcommand fileatthespecifiedaddressforthespecifiedchannel. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 1 1 0 ADDRESS CH Bit Value Description ADDRESS 0–59 StartaddressinthePWM scriptcommand file. 01 PWM channel0. CH 10 PWM channel1. 11 PWM channel2. PWM_STOP COMMAND The PWM_STOP command consistsofa command byte(0x97)and a databytefrom thehost.Thiscommand stopsexecutionofthescriptcommand fileforthespecifiedchannel. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 CH Bit Value Description 01 PWM channel0. CH 10 PWM channel1. 11 PWM channel2.

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VCC ) 2V VoltageatAny Pin -0.3VtoVCC +0.3V Maximum InputCurrentWithoutLatchup ±100 mA ESD ProtectionLevel (Human Body Model) 2 kV (MachineModel) 200V (ChargeDeviceModel) 750V TotalCurrentintoVCC Pin(Source) 100 mA TotalCurrentoutofGND Pin(Sink) 100 mA StorageTemperatureRange −65°C to+140°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butspecificperformanceisnotensured.Forensuredspecificationsand testconditions, see theDC ELECTRICAL CHARACTERISTICS and AC ELECTRICAL CHARACTERISTICS tables. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. DC ELECTRICAL CHARACTERISTICS (Temperature:-40°C ≤ TA ≤ +85°C, unlessotherwisespecified) Data sheetspecificationlimitsarespecifiedby design,test,orstatisticalanalysis. Symbol Parameter Conditions Min Typ Max Units VCC OperatingVoltage 1.62 1.98 V IDD SupplyCurrent(1) InternalClock, No loadson pins, 1.9 3.0 mA VCC = 1.9V,TC = 0.5µs (2) IHALT StandbyMode Current(3) Typical: <9 40 µAVCC = 1.9V,TA = 25°C VIL Logical0 InputVoltage(4) 0.3x VVCC VIH Logical1 InputVoltage(4) 0.7x VVCC Hi-ZInputLeakage (TRI-STATE Output) VCC = 1.8V -2 2 µA PortInputHysteresis(4)(5) 100 400 mV Weak Pull-Up/Pull-DownCurrent 1.6V<VCC < 2.0V 150 µA OutputCurrentSource(Push-PullMode) VCC = 1.62V,VOH = 0.7x VCC -16 mA OutputCurrentSink(Push-PullMode) VCC = 1.62V,VOL = 0.3x VCC 16 mA AllowableSinkand SourceCurrentperPin (6) 16 mA C PAD Input/OutputCapacitance(5) 5 pF (1) Supplycurrentismeasured withinputsconnectedtoVCC and outputsdrivenlowbutnotconnectedtoa load. (2) Command executioncycle= 0.5µs. (3) Instandbymode, theinternalclockisswitchedoff.Supplycurrentinstandbymode ismeasured withinputsconnectedtoVCC and outputsdrivenlowbutnotconnectedtoa load. (4) Appliedtoalldigitalpins(includingRESET) exceptforSLOWCLK when configuredforan externalclock. (5) Specifiedby design,nottested. (6) The sum ofallI/Osink/sourcecurrentmust notexceed themaximum totalcurrentintoVCC and outofGND as specifiedintheabsolute maximum ratings. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:LM8323

SNLS273A –JULY 2010–REVISED MARCH 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS (Temperature:-40°C ≤ TA ≤ +85°C) Data sheetspecificationlimitsarespecifiedby design,test,orstatisticalanalysis. Parameter Conditions Min Typ Max Units System ClockFrequency InternalRC 21 MHz System ClockPeriod(mclk) 1.62V≤ VCC ≤ 1.98V 48 ns Processingand Command ExecutionCycle(tC ) 1.62V≤ VCC ≤ 1.98V 0.5 μs System Clock,Processingand Command Execution 7 % CycleVariation General-PurposeI/O(GPIO) OutputRiseTime(1) C LOAD = 50 pF 15 ns OutputFallTime(1) 15 ns ACCESS.bus InputSignals Bus FreeTime Between Stopand StartCondition 16 mclk (tBUFi)(1) SCL SetupTime (tCSTOsi)(1) BeforeStopCondition 8 mclk SCL HoldTime (tCSTRhi)(1) AfterStartCondition 8 mclk SCL SetupTime (tCSTRsi)(1) BeforeStartCondition 8 mclk Data HighSetupTime (tDHCsi)(1)(2) BeforeSCL RisingEdge (RE) 2 mclk Data Low SetupTime (tDLCsi)(1)(2) BeforeSCL RE 2 mclk SCL Low Time (tSCLlowi)(1) AfterSCL FallingEdge (FE) 12 mclk SCL HighTime (tSCLhighi)(1)(2) AfterSCL RE 12 mclk SDA HoldTime (tSDAhi)(1) AfterSCL FE 0 mclk SDA SetupTime (tSDAsi)(1)(2) BeforeSCL RE 2 mclk ACCESS.bus OutputSignals SCL HoldTime (tSDAho)(1) AfterSCL FE 7 mclk (1) Specifiedby design,nottested. (2) The ACCESS.bus interfaceimplementsand meets thetimingnecessaryforinterfacetotheI2C and SMBus protocolatlogiclevels.The bus driversaredesignedwithopen-drainoutputforbidirectionaloperation.Due toSystem Clock(mclk)Variation,thisspecificationmay notmeet theAC timingand current/voltagedriverequirementsofthefullbus specifications. Figure21. ACB Startand Stop ConditionTiming

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www.ti.com SNLS273A –JULY 2010–REVISED MARCH 2013

REVISION HISTORY

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM8323JGR8AXM/NOPB Active Production csBGA (NYB) | 36 1000 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 LM8323 LM8323JGR8AXM/NOPB.A Active Production csBGA (NYB) | 36 1000 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 LM8323 LM8323JGR8AXMX/NO.A Active Production csBGA (NYB) | 36 3500 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 LM8323 LM8323JGR8AXMX/NOPB Active Production csBGA (NYB) | 36 3500 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 LM8323 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LM8323JGR8AXMX/ NOPB Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8323JGR8AXM/NOPB csBGA NYB 36 1000 208.0 191.0 35.0 LM8323JGR8AXMX/NOPB csBGA NYB 36 3500 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com GRA36A (Rev A)

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