LM8322

LM8322 NSC | Alldatasheet

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Technical content

Mobile I/O Companion Supporting Key-Scan, I/O Expansion, PWM, and ACCESS.bus Host Interface

1.0 General Description

The LM8322 Mobile I/O Companion is a dedicated device to unburden a host processor from scanning a matrix-addressed keypad. In addition, the LM8322 provides general-purpose I/O expansion, and PWM outputs useful for dynamic LED brightness modulation. It communicates with the host through an I 2C-compatible ACCESS.bus interface. An interrupt output is available for signaling key-press and key-release events. Communication frequencies up to 400 kHz (Fast-mode) bus speed are sup- ported. The LM8322 supports a predefined set of commands. These commands enable a host device to keep control over all functions.

2.0 Features

■ Supports keypad matrices of up to 8 × 12 keys plus 8 special-function (SF) keys for a total of 104 keys. SF keys pull keypad scan inputs directly to ground, rather than connecting to a keypad scan output. ■ Supports I2C-compatible ACCESS.bus interface in slave mode up to 400 kHz (Fast-mode). ■ Three host-programmable PWM outputs useful for smooth LED brightness modulation. ■ Supports general-purpose I/O expansion on pins not otherwise used for keypad interface. ■ Key-scan event storage in a FIFO buffer for up to 15 events. ■ Key events, errors, and dedicated hardware interrupts request host service by asserting the IRQ output. ■ The correct reception of a command may be assumed, if no error is reported from the LM8322 after receiving a command. ■ Wake-up from Halt mode on any matrix key-scan event, any use of the SF keys, or any activity on the ACCESS.bus interface.

3.0 Applications

■ Mobile phones ■ Personal Digital Assistants (PDAs) ■ Smart handheld devices ■ Personal media players

4.0 Block Diagram

© 2007 National Semiconductor Corporation 300136 www.national.com LM8322 Mobile I/O Companion Supporting Key-Scan, I/O Expansion, PWM, and ACCESS.bus Host Interface

5.0 Ordering Information

NSID Spec. No. of Pins Package Type Temperature Package Method LM8322JGR8 NOPB 36 Micro-Array −40 to + 85°C 1000 pcs Tape & Reel LM8322JGR8X NOPB 36 Micro-Array −40 to + 85°C 3500 pcs Tape & Reel NOPB = No PB (No Lead)

6.0 Pin Assignments

36–Pin MICRO-ARRAY Package See NS Package Number GRA36A www.national.com 2 LM8322

3 www.national.com LM8322

www.national.com 4 LM8322

7.0 Signal Descriptions

Pin Function I/O Description A6 KP-X0 Input Wake-up input/Keyboard scanning input 0 A5 KP-X1 Input Wake-up input/Keyboard scanning input 1 F1 KP-X2 Input Wake-up input/Keyboard scanning input 2 F2 KP-X3 Input Wake-up input/Keyboard scanning input 3 GPIO_13 I/O General-purpose I/O port 13 A2 KP-X4 Input Wake-up input/Keyboard scanning input 4 GPIO_12 I/O General-purpose I/O port 12 B3 KP-X5 Input Wake-up input/Keyboard scanning input 5 GPIO_11 I/O General-purpose I/O port 11 A3 KP-X6 Input Wake-up input/Keyboard scanning input 6 GPIO_10 I/O General-purpose I/O port 10 B4 KP-X7 Input Wake-up input/Keyboard scanning input 7 GPIO_09 Input General-purpose I/O port 9 C6 KP_Y0 Output Keyboard scanning output 0 C5 KP-Y1 Output Keyboard scanning output 1 B6 KP-Y2 Output Keyboard scanning output 2 B5 KP-Y3 Output Keyboard scanning output 3 GPIO_08 I/O General-purpose I/O port 8 B2 KP-Y4 Output Keyboard scanning output 4 GPIO_07 I/O General-purpose I/O port 7 A1 KP-Y5 Output Keyboard scanning output 5 GPIO_06 I/O General-purpose I/O port 6 B1 KP-Y6 Output Keyboard scanning output 6 GPIO_05 I/O General-purpose I/O port 5 C2 KP-Y7 Output Keyboard scanning output 7 GPIO_04 I/O General-purpose I/O port 4 KP-Y8 Output Keyboard scanning output 8 SLOWCLKOUT Output 32.768 kHz clock output GPIO_03 I/O General-purpose I/O port 3 KP-Y9 Output Keyboard scanning output 9 MUX2_IN1 Input Multiplexer 2 input 1 GPIO_02 I/O General-purpose I/O port 2 KP-Y10 Output Keyboard scanning output 10 MUX2_IN2 Input Multiplexer 2 input 2 GPIO_01 I/O General-purpose I/O port 1 KP-Y11 Output Keyboard scanning output 11 MUX2_OUT Output Multiplexer 2 output GPIO_00 I/O General-purpose I/O port 0 E2 ACB_SDA I/O ACCESS.bus data signal E1 ACB_SCL I/O ACCESS.bus clock signal E4 PWM_0 Output Pulse-width modulated output 0 MUX_IN1 Input Multiplexer 1 input 1 F5 PWM_1 Output Pulse-width modulated output 1 MUX_IN2 Input Multiplexer 1 input 2 PWM_2 Output Pulse-width modulated output 2 MUX1_OUT Output Multiplexer 1 output CONFIG_2 Input Slave address select input 2 GPIO_15 I/O General-purpose I/O port 15 5 www.national.com LM8322

7.1 TERMINATION OF UNUSED SIGNALS

TABLE 1. Termination of Unused Signals RESET Connect to VCC if not driven from an external Supervisory circuit. by the level on this pin. This pin cannot be left unconnected. XTAL_IN This pin is a high-impedance input and must be connected to VCC or GND if it is unused. XTAL_OUT This pin has a weak pullup and can be left open-circuit if it is unused.

• Connect to VCC or GND.
• Program as inputs with weak pullups or outputs. Care must be taken when connecting to V CC or GND. Erroneous parameters sent with the WRITE_PORT_SEL or WRITE_PORT_STATE commands could cause excessive current consumption. A better approach is to leave unused keyboard inputs open-circuit and use the WRITE_PORT_SEL and WRITE_PORT_STATE commands to configure the pins as inputs with weak pullups or outputs. KP-X7 can only be an input. This pin should be programmed as an input with a weak pullup. KP-Y[2:0] These pins are dedicated keypad pins. In the minimum configuration, these pins are keypad outputs driven low. KP-Y[11:3] These pins are in high-impedance mode after power-on initialization. There are two ways to handle these pins if unused:
• Connect to VCC or GND.
• Program as inputs with weak pullups or outputs Care must be taken when connecting to V CC or GND. Erroneous parameters sent with the WRITE_PORT_SEL or WRITE_PORT_STATE commands could cause excessive current consumption. A better approach is to leave unused keyboard inputs open-circuit and use the WRITE_PORT_SEL and WRITE_PORT_STATE commands to configure the pins as inputs with weak pullups or outputs. PWM_0, PWM_1 These pins must be connected to V CC or GND if they are not used for any optional function described in the datasheet. PWM_2/ CONFIG_2 Connect to VCC or GND through a pullup or pulldown resistor because the slave address is selected by the level on this pin. This pin cannot be left unconnected. IRQ This pin must be connected. www.national.com 6 LM8322

8.0 Application Example

FIGURE 1. Typical Application

8.1 FEATURES

• 8 x 9 standard keys.
• 8 special function keys (SF keys) with wake-up capability by forcing a WAKE_INx pin to ground. Pressing a SF key overrides any other key in the same row.
• ACCESS.bus (I2C-compatible) interface for communication with the host.
• Hardware IRQ interrupt to host to signal keypad, error, and status events. By default, this is an open-drain output, so an external pullup resistor may be required to avoid false assertion. The host can program this output for push-pull mode, in which case the pullup might not be required, if the host can ignore a false assertion before the LM8322 has been programmed.
• Two LEDs driven by PWM outputs with programmable ramp-up and ramp-down. PWM_2 (shared with GPIO_15 and CONFIG_2) could be used as an additional PWM driver port to control a third external LED.
• ACCESS.bus address is selected by the CONFIG_1 and CONFIG_2 inputs. These pins may also be used as GPIO pins after reset initialization has occurred. If extra GPIO pins are not needed, CONFIG_1 and CONFIG_2 may be tied directly to VCC and GND.
• Crystal pins XTAL_IN and XTAL_OUT may be used to connect to an external 32.768 kHz crystal or receive an external 32.768 kHz clock input for running the PWM peripheral. By default, the PWM is clocked by an on-chip clock source. 7 www.national.com LM8322

9.0 Clocks

• System Clock (mclk) — The system clock is in the range of about 21 MHz (± 7%) typical. This clock is used to drive the I2C compatible serial ACCESS bus and is the input clock for other function blocks.
• Processing and Command Execution Clock (tC) — The internal processing is based on a 2 MHz clock. This clock is derived from the System Clock.
• Internal PWM Clock — The internal PWM clock is a fixed scaled down clock (÷ 64) of the Processing and Command Execution Clock. This clock is close to 32 kHz which is in a good range to source the PWM function block as an alternative to an external clock source.
• External 32.768 kHz Clock — driven into the SLOWCLK input. May be used internally as the timebase for the PWM and driven on the SLOWCLKOUT output.
• External 32.768 kHz Crystal — connected across the XTAL_IN and XTAL_OUT pins (XTAL_IN is an alternate function of the SLOWCLK pin). May be used internally as the timebase for the PWM and driven on the SLOWCLKOUT output. 30013602

FIGURE 2. Clock Architecture

9.1 INTERNAL EXECUTION CYCLE

• Occurrence of a key-press or key-release event.
• A Start condition driven by the host on the ACCESS.bus interface.
• Assertion of the RESET input. After reset, the default timebase for the PWM outputs is the internal execution clock divided by 64.

9.2 BUFFERED CLOCK

• Prescaled internal Execution clock.
• External 32.768 kHz clock received on the SLOWCLK input.
• On-chip oscillator with an external crystal connected across XTAL_IN and XTAL_OUT. Any of these sources may be buffered and driven on the SLOWCLKOUT output. The clock buffer is enabled with the WRITE_CLOCK command. If XTAL_IN is not used it must be terminated to VCC or GND. www.national.com 8 LM8322

9.3 CLOCK CONFIGURATION

override the default settings. TABLE 2. Clock Configuration Register

0 SLOWCLKOUT 0 0 SLOWCLKEN 0 RCPWM

SLOWCLKOUT 0 Disable SLOWCLKOUT buffer. 0 External 32.768 kHz crystal is installed between the XTAL_IN and XTAL_OUT pins. 00 On-chip RC clock divided by 64 drives the PWM and clock buffer. 11 External 32.768 kHz clock or crystal drives the PWM and clock buffer.

10.0 Reset

(POR) signal. The RESET input must not be allowed to float. to VCC, either directly or through a pull-up resistor.

10.1 EXTERNAL RESET

(5×) greater than the VCC rise time to this level. ately, any observed delay being only propagation delay. the reset state within about 1400 ns.

10.2 POWER-ON RESET (POR)

10.3 PIN CONFIGURATION AFTER RESET

Table 2 shows the pin configuration after reset. TABLE 3. Pin Configuration After Reset IRQ High-impedance mode. Active drive low. XTAL_IN High-impedance mode. High-impedance mode. Terminate to VCC or GND if not used. XTAL_OUT Weak pullup device. Weak pullup device. RESET High-impedance mode. High-impedance mode.

10.4 DEVICE CONFIGURATION AFTER RESET

• PWM Clock — the PWM clock source is the on-chip clock divided by 64. This remains in effect until changed by a host command.
• Keypad Size — 3 × 3.
• Digital Multiplexers — disabled.
• IRQ — enabled, active low.
• NOINIT Bit — set.
• Debounce Time — 3 scan cycles (about 12 milliseconds).
• Active Time — 500 milliseconds.

10.5 CONFIGURATION INPUTS

LSB (shown as X below) indicating the direction of transfer. TABLE 4. Bus Address Selection

10.6 INITIALIZATION

FIGURE 3. LM8322 Initialization Behavior command will return an interrupt code with the NOINIT bit set. FIGURE 4. IRQ Reset Timing

10.7 INITIALIZATION EXAMPLE

• Keypad matrix configuration is 8 × 4.
• GPIO_03 through GPIO_07 are available to use as GPIO pins.
• GPIO_03 is an output driven low.
• GPIO_4 and GPIO_5 are outputs driven high.
• GPIO_06 and GPIO_07 are inputs with weak pulldowns.
• GPIO_14 and GPIO_15 are inputs with weak pullups.
• The PWM clock source is the internal execution clock divided by 64 (about 32 kHz). Most of these settings can be verified by executing com- mands such as READ_CONF, READ_PORT_SEL, READ_CLOCK, etc. ALL GPIO pin states can be read using the READ_PORT_STATE command, without regard to whether the pin is an input or an output. An open-drain signal can be created by alternating between input mode and driving the output low. All GPIO s can sink and source 16 mA when configured as an output. Command Encoding Parameter 1 Parameter 2 Description WRITE_CFG 0x81 0x40 Selects 36-pin package and disables the two digital multiplexers. WRITE_CLK 0x93 0x08 SLOWCLKOUT disabled, no external 32.768 kHz clock required, PWM clock source is internal. SET_KEY_SIZE 0x90 0x84 Selects a keypad matrix size of 8 × 4. SET_ACTIVE 0x8B 0x4B Sets the active time to about 300 milliseconds (75 × 4 milliseconds). SET_DEBOUNCE 0x8F 0x03 Sets the key debouncing time to about 12 milliseconds (3 × 4 ms). This is actually the default and would not have to be performed. WRITE_PORT_SEL 0x85 0x00 0x38 Configure GPIO_03, GPIO_04, and GPIO_05 as outputs. Configure GPIO_06, GPIO_07, GPIO_14, and GPIO_15 as inputs. WRITE_PULL_DOWN 0x84 0x00 0x3F Set the direction for the pullup/pulldown devices on GPIO_06 and GPIO_07 to pulldown. Set the direction for the pullup/pulldown devices on GPIO_14 and GPIO_15 to pullup. WRITE_PORT_STATE 0x86 0xC0 0xF0 Set GPIO_04 and GPIO_05 to drive high. Enable the pullups on GPIO_06, GPIO_07, GPIO_14, and GPIO_15.

11.0 Halt Mode

Halt mode at the maximum VCC (1.98V) from 25°C to +85°C. FIGURE 6. Halt Current vs. Temperature at 1.98V and the host should then repeat the cycle. shares the bus with peripherals that are continuously active. tivity after system initialization.

12.0 Keypad Interface

12.1 EVENT CODE ASSIGNMENT

released, the MSB of the code is clear. TABLE 5. Keypad Matrix Code Assignments codes loaded into the FIFO buffer. TABLE 6. Example Sequence of Events FIGURE 7. Example Event Codes Loaded in FIFO Buffer

12.2 KEYPAD SCAN CYCLES

detected, the keypad is rescanned after a debounce delay. coded and written to the FIFO buffer. FIGURE 8. Keypad Scan Cycles

low at any time, while the others are driven high or undriven. are pulled high by weak pullups. other keys that use the same KP-Xx pin are ignored.

12.2.1 Timing Parameters

• Debounce Time — minimum delay between detecting a keypad event and confirming the event before asserting IRQ. The default debounce time is 3 scan cycles (about 12 milliseconds), but the host can set values in the range 1–255 cycles (4–1020 milliseconds).
• Active Time — period without detecting a state change in the keypad that triggers entry into Halt mode, during which keypad scanning is suspended. The default active time is 500 milliseconds, but the host can set it values in the range 4–1020 milliseconds. The active time must be greater than the debounce time.

12.2.2 Multiple Key Pressings

FIFO buffer in the sequence in which they were decoded.

• A multiple key-press event is given if two or more key- press events are reported but no corresponding key- release event.
• With the activity time set between the minimum and maximum time (4 msec to 1 second) it is not safe to detect two simultaneous key pressings in one input row (see Figure 9 on the left hand side.)
• If all key pressings (two or more) are located in different input rows (see Figure 9 on the right hand side) then the key pressed events will be correctly found in the FIFO buffer without any restriction. 30013609

FIGURE 9. Simultaneous Keys Pressed

• In order to securely detect and store the key codes of simultaneous key pressings in the same input row the following precautions must be taken from the host side: “As soon as the host device has detected a key pressed event the host must send the SET_ACTIVE Command with the pa- rameter set to “00”. This will prevent the LM8322 from enter- ing HALT mode. If all keyboard events are resolved (no remaining key pressed status in the LM8322 anymore) then the host must send the SET_ACTIVE Command again with the parameter setting the desired duration for the active time. This will enable the LM8322 to enter low power HALT mode once the activity time has passed without detecting any events.
• Once one or more key (pressed and/or released) events have been read from the host with the help of the READ FIFO command there are two conditions cleaning the FIFO buffer contents: — A second execution of the READ FIFO Command or, — A new key event detected from the LM8322.

12.3 EXAMPLE KEYPAD CONFIGURATION

FIGURE 10. Keypad Interface Example configuration supports 3 × 3 + 3 SF keys (total of 12 keys). command would specify 8 KP-Xx inputs and 4 KP-Yx outputs.

13.0 General-Purpose I/O Ports

and a set bit selects the output direction. WRITE_PULL_DOWN command parameters. TABLE 7. GPIO Port Control Bits

13.1 USING THE CONFIG_X PINS FOR GPIO

select the ACCESS.bus (I2C) bus address. other state when used as a GPIO pin. CONFIG_2 has two alternate functions, in addition to GPIO. output, which also would override its use as a GPIO pin.

13.2 GPIO TIMING

vals of 7.3 µs, as shown in Figure 11. FIGURE 11. GPIO Port State Change Timing

14.0 PWM Output Generation

tonomous operation after setup and launch by the host. Figure 12 shows the architecture of a script-execution engine. FIGURE 12. PWM Script Execution Engine

• PWM_WRITE — load one word into the script command file at a specified address.
• PWM_START — start execution of the script.
• PWM_STOP — stop execution of the script. Please note: The PWM_STOP command might not take im- mediate effect if the current command being executed is a command with long execution time. If a PWM_STOP com- mand is sent when the PWM engine is running a long RAMP command, the PWM will only stop after the RAMP is com- pleted. The script commands have their own fixed-length 16-bit for- mat and encoding unrelated to the variable-length, byte- based format used for host commands. A script command is sent by the host to the LM8322 as a parameter to the PWM_WRITE command. Another parameter to the PWM_WRITE command specifies an address in the script command file for receiving the command.

14.1 COMMAND QUEUE

command buffer may then receive a new command. after the host issues the PWM_START command. command asserts IRQ to the host.

14.2 PWM TIMER OPERATION

FIGURE 13. PWM Timer than or equal to the value of the ramp counter. 0x00 or 0xFF depending on the ramp direction. host after the last step is performed.

14.3 PWM SCRIPT COMMANDS

Table 8 summarizes the script commands. TABLE 8. PWM Script Commands

14.4 RAMP COMMAND

The RAMP command generates a duty-cycle ramp starting from the current value. At each step, the ramp counter is in- cremented or decremented by one, unless it has reached its its saturation value (0xFF for increment, or 0x00 for decre- ment). The time for one step is controlled by the PRESCALE bit and STEPTIME field. The minimum time for one step is 0.49 milliseconds. and the maximum time is about 1 second, which supports both very fast and very slow ramps. The IN- CREMENT field specifies the number of steps to be executed by the command. The maximum value is 126, which corre- sponds to half of full scale. There are two special cases in the instruction encoding. If all bits and fields are 0, it is interpreted as the GO TO START command. If the STEPTIME field is 0 but any other bit or field is non-zero, it is interpreted as the SET_PWM command. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 PRESCALE STEPTIME SIGN INCREMENT

Bit or Field Value Description PRESCALE 0 Divide the 32.768 kHz clock by 16 1 Divide the 32.768 kHz clock by 512 STEPTIME 1–63 Number of prescaled clock cycles per step SIGN 0 Increment ramp counter

1 Decrement ramp counter

INCREMENT 1–126 Number of steps executed by this instruction

14.5 SET_PWM COMMAND

The SET_PWM command loads the ramp counter from the 8-bit DUTYCYCLE field in the instruction. Please note: Only 0x00 and 0xFF are valid values for the duty cycle in SET_PWM command. Other values can be estab- lished by initializing the duty cycle to either 100% or 0% followed by a RAMP command. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 DUTYCYCLE Bit or Field Value Description DUTYCYCLE 0 Duty cycle is 0%. 255 Duty cycle is 100%.

14.6 GO_TO_START COMMAND

The GO_TO_START command jumps to the first command in the script command file. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

14.7 BRANCH COMMAND

The BRANCH command jumps to the specified command in the script command file, with the option of looping for a spec- ified number of repetitions. Nested loops are not allowed. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 LOOPCOUNT 0 ADDRESS Field Value Description LOOPCOUNT 0 Loop until a STOP PWM SCRIPT command is issued by the host. 1–63 Number of repetitions to perform, biased by -1. The range is 0–62 repetitions. ADDRESS 0–59 Branch destination address in the script command file. If this field is greater than 59, no looping will be performed. www.national.com 20 LM8322

14.8 END COMMAND

an interrupt to the host if the RESET bit is set to “1” or “0”. mains active with the fixed duty cycle it was last set to. exception - in this case the IRQ signal will not be asserted. RESET 0 PWM_x output is active when script execution terminates. 1 PWM_x output is Tristate when script execution terminates.

14.9 TRIGGER COMMAND

for a trigger takes at least sixteen 32.768 kHz clock cycles. stall script execution until the trigger conditions are satisfied. a TRIGGER command that waits for the trigger.

14.10 PWM SCRIPT EXAMPLE

ample. Figure 14 shows the PWM outputs for this example. FIGURE 14. PWM Outputs

14.10.1 PWM Channel 0 Script

PWM_WRITE Parameter 1 PWM_WRITE Parameter 2 PWM_WRITE Parameter 3 Script Command Description 0x00 0x01 0x40 0x00 SET_PWM Initialize channel for 0% duty cycle 0x01 0x05 0xE2 0x00 TRIGGER Wait for trigger from channel 2 0x02 0x09 0x07 0x7E RAMP Ramp up by 126 steps 0x03 0x0D 0x07 0x7E RAMP Ramp up by 126 steps 0x04 0x11 0x07 0xFE RAMP Ramp down by 126 steps 0x05 0x15 0x07 0xFE RAMP Ramp down by 126 steps 0x06 0x19 0xA1 0x82 BRANCH Loop 2 times starting at address 0x02 0x07 0x1D 0xC8 0x00 END Terminate script and assert IRQ to host

14.10.2 PWM Channel 1 Script

PWM_WRITE Parameter 1 PWM_WRITE Parameter 2 PWM_WRITE Parameter 3 Script Command Description 0x00 0x02 0x40 0xFF SET_PWM Initialize channel for 100% duty cycle 0x01 0x06 0xE2 0x00 TRIGGER Wait for trigger from channel 2 0x02 0x0A 0x0F 0xFE RAMP Ramp down by 126 steps 0x03 0x0E 0x0F 0xFE RAMP Ramp down by 126 steps 0x04 0x12 0x0F 0x7E RAMP Ramp up by 126 steps 0x05 0x16 0x0F 0x7E RAMP Ramp up by 126 steps 0x06 0x1A 0xA2 0x02 BRANCH Loop 3 times starting at address 0x02 0x07 0x1E 0xE0 0x08 TRIGGER Send trigger to channel 2 0x08 0x22 0xC8 0x00 END Terminate script and assert IRQ to host

14.10.3 PWM Channel 2 Script

PWM_WRITE Parameter 1 PWM_WRITE Parameter 2 PWM_WRITE Parameter 3 Script Command Description 0x00 0x03 0x40 0x00 SET_PWM Initialize channel for 0% duty cycle 0x01 0x07 0x03 0x7E RAMP Ramp up by 126 steps 0x02 0x0B 0x03 0x7E RAMP Ramp up by 126 steps 0x03 0x0F 0x03 0xFE RAMP Ramp down by 126 steps 0x04 0x13 0x03 0xFE RAMP Ramp down by 126 steps 0x05 0x17 0xE1 0x06 TRIGGER Send triggers to channels 0 and 1, wait for trigger from channel 1 0x06 0x1B 0x03 0x7E RAMP Ramp up by 126 steps 0x07 0x1F 0x03 0x7E RAMP Ramp up by 126 steps 0x08 0x23 0x03 0xFE RAMP Ramp down by 126 steps 0x09 0x27 0x03 0xFE RAMP Ramp down by 126 steps 0x0A 0x2B 0xC8 0x00 END Terminate script and assert IRQ to host www.national.com 22 LM8322

14.11 SELECTABLE SCRIPT EXAMPLE

Multiple scripts can be placed in a single buffer. The script which is executed is selected by the address in the parameter to the PWM_START command (0x96). Script Command Address PWM_WRITE Parameter 1 PWM_WRITE Parameter 2 PWM_WRITE Parameter 3 Script Command Description 0x00 Script 1 0x01 0x40 0x00 Set PWM_0 to 0% duty cycle 0x01 0x05 0x0F 0x33 Ramp up 51 steps 0x02 0x09 0xC0 0x00 Keep channel at 20% duty cycle 0x03 Script 2 0x0D 0x40 0xFF Set PWM_0 to 100% duty cycle 0x04 0x11 0x0F 0xD5 Ramp down 85 steps 0x05 0x15 0xC0 0x00 Keep channel at 66.6% duty cycle 0x06 Script 3 0x19 0x40 0x00 Set PWM_0 to 0% duty cycle 0x07 0x1D 0x07 0x7E Ramp up 126 steps 0x08 0x21 0x07 0x7E Ramp up 126 steps 0x09 0x25 0x07 0xFE Ramp down 126 steps 0x0A 0x29 0x07 0xFE Ramp down 126 steps 0x0B 0x2D 0xA5 0x07 Loop ten times to script address 0x07 0x0C Script 4 0x31 0xC8 0x00 Switch PWM_0 off (script 3 automatically enters here) 0x0D Script 5 0x35 0x40 0x00 Set PWM_0 to 0% duty cycle 0x0E 0x39 0x07 0x25 Ramp up 37 steps 0x0F 0x3D 0xC0 0x00 Keep channel at 14.5% duty cycle 0x10 Script 6 0x41 0x40 0x00 Set PWM_0 to 0% duty cycle 0x11 (Alternates between 25% and 75% duty cycle) 0x45 0x01 0x40 Ramp up 64 steps 0x12 0x49 0x3F 0x7E Ramp up 126 steps 0x13 0x4D 0x3F 0xFE Ramp down 126 steps 0x14 0x51 0xA0 0x12 Always branch to script address 0x12 0x15 Script 7 0x3B To set a fixed duty cycle on a PWM channel requires 3 steps (see script 1 for duty cycles from 0% to 49% and script 2 for duty cycles from 51% to 100%). To keep a PWM channel active providing a fixed duty cycle on its output, the script must terminate with the END com- mand leaving the RESET bit clear. To switch this channel off, the host must send another PWM_START command (0x96 followed by the parameter bytes) triggering the single com- mand described in script 4. This END command will set the RESET bit and the dedicated PWM output will be disabled. Script 3 will automatically enter into this command when the 10 loops of ramping up and down are executed. Script 7 can be finished by two commands:

• PWM_STOP command with parameter 0x01
• PWM_START command with parameter 0x31 (start PWM_0 from address 0x0C to run script 4) The script address is the physical address to be used from BRANCH instructions inside the script file buffer. The param- eter 1 byte contains the same address with the 2 channel bits appended and will be associated with the PWM_START com- mand. 23 www.national.com LM8322

15.0 Digital Multiplexers

signals are alternate functions of three KP-Yx pins. truth table for the multiplexers is shown in Table 9. TABLE 9. Digital Multiplexer Function Table

0 X X X

16.0 Host Interface

16.1 START AND STOP CONDITIONS

mission. Every byte is acknowledged by the receiver. FIGURE 15. Start and Stop Conditions

16.2 CONTINUOUS COMMAND STRINGS

other ACCESS.bus device from gaining control of the bus. string will include the commands shown in Table 10. TABLE 10. Minimal Command String ditional commands shown in Table 11. TABLE 11. Additional Commands

16.3 DEVICE ADDRESS

bit are broadcast by the bus master to all bus slaves. TABLE 12. Device Address Selection pullups will select 1000 101X by default.

16.4 HOST WRITE COMMANDS

reads from the slave to the host. ber of rows and columns for the keypad.

FIGURE 16. Host Write Command

16.5 HOST READ COMMANDS

byte, a second address byte, and two data bytes. to indicate a write transaction of the command to the LM8322. this case, the direction bit is changed. ment (NACK) to indicate the end of the data. FIGURE 17. Host Read Command

16.6 INTERRUPTS

• Any new key-event after the last interrupt was asserted but not yet acknowledged by reading the interrupt code.
• Termination of a PWM script (END command).
• Any error condition, which is indicated by the error code. www.national.com 26 LM8322

16.7 INTERRUPT CODE

TABLE 13. Interrupt Code PWM2END An END script command was executed by PWM channel 2. PWM1END An END script command was executed by PWM channel 1. PWM0END An END script command was executed by PWM channel 0. NOINIT The LM8322 is waiting for an initialization sequence. ERROR An error condition occurred. KEYPAD A key-press or key-release event occurred.

16.8 ERROR CODE

the error code. Table 14 shows the format of the error code. TABLE 14. Error Code

0 FIFOOVR 0 0 0 KEYOVR CMDUNK BADPAR

FIFOOVER Event occurred while the FIFO was full. KEYOVR More than two keys were pressed simultaneously. BADPAR Bad command parameter.

16.9 WAKE-UP FROM HALT MODE

period, so that it can be driven by the LM8322. FIGURE 18. LM8322 Responds with NACK, Host Retries Command

17.0 Host Commands

Function Cmd Dir Data Bytes Description READ_ID 0x80 R nnnn nnnn Read the manufacturer code (nnnn nnnn) and the device revision number (pppp pppp).pppp pppp WRITE_CFG 0x81 W nnnn nnnn Write the hardware configuration register. READ_INT 0x82 R nnnn nnnn Read the interrupt code, deassert the IRQ output, and clear the code. (If the NOINIT bit is set, it remains set and IRQ remains asserted until a WRITE_CFG command is received. RESET 0x83 W nnnn nnnn Reset the LM8322. Error if nnnn nnnn is not 0xAA. WRITE_PULL_DO WN 0x84 W nnnn nnnn Select pullup (0) or pulldown (1) direction for the corresponding general-purpose I/O (GPIO) port pins.pppp pppp WRITE_PORT_SE L 0x85 W nnnn nnnn Select input (0) or output (1) for the corresponding general- purpose I/O (GPIO) port pins.pppp pppp WRITE_PORT_ST ATE 0x86 W nnnn nnnn For pins configured as inputs, 0 selects high-impedance mode and 1 enables a weak pullup. For pins configured as outputs, each bit specifies the logic level driven on the pin.pppp pppp READ_PORT_SEL 0x87 R nnnn nnnn Read the direction of the corresponding GPIO port pins.pppp pppp READ_PORT_STA TE 0x88 R nnnn nnnn Read the state on the corresponding GPIO port pins.pppp pppp READ_FIFO 0x89 R Up to 15 event codes Read an event from the FIFO. Maximum of 14 event codes stored in the FIFO. RPT_READ_FIFO 0x8A R Up to 15 event codes Repeats a FIFO read without advancing the FIFO pointer, for example to retry a read after an error. SET_ACTIVE 0x8B W nnnn nnnn Set the time during which the LM8322 stays active before entering Halt mode. The active time must be greater than the debounce time. The default time is 500 milliseconds. The valid range is 1255. Active time = n × 4 milliseconds. READ_ERROR 0x8C R nnnn nnnn Read and clear the error code. SET_DEBOUNCE 0x8F W nnnn nnnn Set the time for rescanning the keypad after detecting a key- press or key-release event to verify the event. The default time is 12 milliseconds. The valid range is 1255. Debounce time = n × 4 milliseconds and must not exceed active time. SET_KEY_SIZE 0x90 W nnnn pppp Set keypad size. nnnn = KP-Xx pins, pppp = KP-Yx pins READ_KEY_SIZE 0x91 R nnnn pppp Read keypad size. nnnn = KP-Xx pins, pppp = KP-Yx pins READ_CFG 0x92 R nnnn nnnn Read the hardware configuration register. WRITE_CLOCK 0x93 W nnnn nnnn Write the clock configuration register. READ_CLOCK 0x94 R nnnn nnnn Read the clock configuration register. PWM_WRITE 0x95 W aaaa aann Write a command to the PWM script command file. pppp pppp nn = PWM channel number (01, 10, or 11) qqqq qqqq aaaaaa = address in script command file (059) pppp pppp = high byte of script command qqqq qqqq = low byte of script command PWM_START 0x96 W aaaa aann Start script on channel nn (01, 10, or 11) at address aaaaaa. PWM_STOP 0x97 W 0000 00nn Stop script on channel nn (01, 10, or 11). www.national.com 28 LM8322

Please note: The data bytes which follow the command can be reads (toward the host) or writes (toward the LM8322). In the case of the READ_FIFO and RPT_READ_FIFO com- mands, the number of data bytes is variable, with the last transaction indicated by returning a negative acknowledge- ment (NACK).

17.1 READ_ID COMMAND

The READ_ID command consists of a command byte (0x80) from the host and two data bytes from the LM8322. The first data byte returns the manufacturer code, and the second byte returns the device revision level. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 MANUFACTURER REVISION

17.2 WRITE_CFG COMMAND

The WRITE_CFG command consists of a command byte (0x81) and a data byte from the host. The data byte is loaded into the hardware configuration register. The default state of this register is 0x80. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 IRQPST 0 0 0 MUX2EN MUX2SEL MUX1EN MUX1SEL Bit Value Description IRQPST 0 IRQ is an open-drain output. 1 IRQ is a push-pull output. MUX2EN 0 MUX2_OUT output disabled. 1 MUX2_OUT output enabled. This overrides any other function available on this pin. MUX2SEL 0 If the MUX2 EN bit is 1, the MUX2_IN1 input drives the MUX2_OUT output. 1 If the MUX2 EN bit is 1, the MUX2_IN2 input drives the MUX2_OUT output. MUX1EN 0 MUX1_OUT output disabled. 1 MUX1_OUT output enabled. This overrides any other function available on this pin. MUX1SEL 0 If the MUX1 EN bit is 1, the MUX1_IN1 input drives the MUX1_OUT output. 1 If the MUX1 EN bit is 1, the MUX1_IN2 input drives the MUX1_OUT output. Please note: The WRITE_CFG COMMAND defines basic hardware operation characteristics. It should be placed at the beginning of the initialization sequence driven from the host device after power on. It is not recommended to change the configuration during run time. Anytime this command is used, it initializes important operating characteristics such as the the GPIO port. This means that the GPIO pins must be re- established via WRITE_PORT_SEL and WRITE_PORT_STATE commands in this case. 29 www.national.com LM8322

17.3 READ_INT COMMAND

The READ_INT command consists of a command byte (0x82) from the host and a data byte from the LM8322. The data byte is the interrupt code. Reading the interrupt code acknowl- edges the interrupt (which deasserts IRQ) and clears the interrupt code. An exception to this behavior occurs if the NOINIT bit is set, in which case IRQ will not be deasserted and the interrupt code will not be cleared until a WRITE_CFG command is received. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 0 PWM2END PWM1END PWM0END NOINIT ERROR 0 0 KEYPAD Bit Value Description PWM2END 0 No interrupt from PWM channel 2. 1 An END script command was executed by PWM channel 2. PWM1END 0 No interrupt from PWM channel 1. 1 An END script command was executed by PWM channel 1. PWM0END 0 No interrupt from PWM channel 0. 1 An END script command was executed by PWM channel 0. NOINIT 0 Normal operation. 1 LM8322 is waiting for the initialization sequence. ERROR 0 No error condition is indicated. 1 An error condition occurred. KEYPAD 0 No key-press or key-release event is indicated. 1 A key-press or key-release event occurred.

17.4 RESET COMMAND

The RESET command consists of a command byte (0x83) and one data byte from the host. The command causes a re- set, identical to an external reset. The data byte must be 0xAA, otherwise no reset will occur and an error condition will be signalled. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 www.national.com 30 LM8322

17.5 WRITE_PULL_DOWN COMMAND

The WRITE_PORT_SEL command consists of a command byte (0x84) and two data bytes from the host. The data bytes configure the pullup/pulldown device (if enabled) for the cor- responding general-purpose I/O ports as pullups (0) or pull- downs (1). The first data byte controls ports GPIO_15 through GPIO_08, and the second byte controls ports GPIO_07 through GPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 0 1 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_09 GPIO_08 GPIO_07 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description GPIO_xx 0 GPIO port pin pullup/pulldown device is a pullup. 1 GPIO port pin pullup/pulldown device is a pulldown.

17.6 WRITE_PORT_SEL COMMAND

The WRITE_PORT_SEL command consists of a command byte (0x85) and two data bytes from the host. The data bytes configure the corresponding general-purpose I/O ports as in- puts (0) or outputs (1). The first data byte controls ports GPIO_15 through GPIO_08, and the second byte controls ports GPIO_07 through GPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 0 1 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_100 GPIO_08 GPIO_07 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description GPIO_xx 0 GPIO port pin is an input. 1 GPIO port pin is an output. The GPIO_09 port pin can only be configured as an input with weak pullup/pulldown device. 31 www.national.com LM8322

17.7 WRITE_PORT_STATE COMMAND

The WRITE_PORT_STATE command consists of a com- mand byte (0x86) and two data bytes from the host. For general-purpose I/O ports configured as inputs, the data bytes select whether the inputs are high-impedance (0) or have a weak pullup (1). For ports configured as outputs, the data bytes control the state driven on the output. The first data byte controls ports GPIO_15 through GPIO_08, and the sec- ond byte controls ports GPIO_07 through GPIO_00. Bit Value Description GPIO_xx 0 If the GPIO port pin is an input, pullup/pulldown device is disabled. If the GPIO port pin is an output, it is driven low. 1 If the GPIO port pin is an input, pullup/pulldown device is enabled. If the GPIO port pin is an output, it is driven high.

17.8 READ_PORT_SEL COMMAND

The READ_PORT_SEL command consists of a command byte (0x87) from the host and two data bytes from the LM8322. The data bytes indicate the direction configured for the corresponding ports, either input (0) or output (1). The first data byte controls ports GPIO_15 through GPIO_08, and the second byte controls ports GPIO_07 through GPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 1 1 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_09 GPIO_08 GPIO_07 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description GPIO_xx 0 GPIO port pin is an input. 1 GPIO port pin is an output. www.national.com 32 LM8322

17.9 READ_PORT_STATE COMMAND

The READ_PORT_STATE command consists of a command byte (0x88) from the host and two data bytes from the LM8322. The data bytes indicate the states on the corre- sponding ports. The first data byte controls ports GPIO_15 through GPIO_08, and the second byte controls ports GPIO_07 through GPIO_00. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_09 GPIO_08 GP IO_ GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 GPIO_00 Bit Value Description GPIO_xx 0 If the GPIO port pin is an input, pullup is disabled. If the GPIO port pin is an output, it is driven low. 1 If the GPIO port pin is an input, pullup is enabled. If the GPIO port pin is an output, it is driven high.

17.10 READ_FIFO COMMAND

The READ_FIFO command consists of a command byte (0x89) sent from the host and a variable number of data bytes received from the LM8322. The LM8322 will provide data until the FIFO is empty. The last data byte is indicated by its value (0x00) and a negative acknowledgement (NACK) on the ACCESS.bus interface. The data bytes correspond to key- press and key-release events, as described in Table 5. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 1 FIFODATA 0x00 Field Value Description FIFODATA 0xxxxxxx Key-release event. 1xxxxxxx Key-press event.

17.11 RPT_READ_FIFO COMMAND

The RPT_READ_FIFO command consists of a command byte (0x8A) and from the host and a variable number of data bytes from the LM8322. This command provides the same data as a previous READ_FIFO command, but without ad- vancing the FIFO pointer. It may be used to recover from an error encountered during a READ_FIFO command. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 0 FIFODATA 0x00 Field Value Description FIFODATA 0xxxxxxx Key-release event. 1xxxxxxx Key-press event. 33 www.national.com LM8322

17.12 SET_ACTIVE COMMAND

The SET_ACTIVE command consists of a command byte (0x8B) and a data byte from the host. This command sets the time that the LM8322 stays active without detecting a key- press or key-release event before entering Halt mode. The default active time is 500 milliseconds. The host can program ACTIVETIME from 4–1020 milliseconds with a granularity of 4 milliseconds. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 1 ACTIVETIME Field Value Description ACTIVETIME 0 Halt mode is disabled. 1–255 Active time = n × 4 milliseconds.

17.13 READ_ERROR COMMAND

The READ_ERROR command consists of a command byte (0x8C) from the host and a data byte from the LM8322. After reading an interrupt code that indicates an error condition, this command is used to read an error code that indicates the cause of the error condition. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 1 0 0 0 FIFOOVR 0 0 0 KEYOVR CMDUNK BADPAR Bit Value Description FIFOOVR 0 No FIFO overrun occurred. 1 Event occurred while the FIFO was full. KEYOVR 0 No keypad overrun occurred. 1 More than two keys were pressed simultaneously. CMDUNK 0 No invalid command was encountered. 1 Not a valid command. BADPAR 0 No bad parameter was encountered. 1 Bad command parameter. www.national.com 34 LM8322

17.14 SET_DEBOUNCE COMMAND

The SET_DEBOUNCE command consists of a command byte (0x8F) and a data byte from the host. This command sets the time that the LM8322 waits before rescanning the keypad to confirm a key-press or key-release event. The default de- bounce time is 12 milliseconds. The host can program DE- BOUNCETIME from 4–1020 milliseconds with a granularity of 4 milliseconds. The DEBOUNCETIME must not exceed the active time set with the SET_ACTIVE command. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 1 1 1 DEBOUNCETIME Field Value Description DEBOUNCETIME 1–255 Active time = n × 4 milliseconds.

17.15 SET_KEY_SIZE COMMAND

The SET_KEY_SIZE command consists of a command byte (0x90) and a data byte from the host. This command specifies the keypad size in terms of the number of KP-Xx inputs and KP-Yx outputs which are used. Any unused KP-Xx and KP- Yx pins may be used for general-purpose I/O. The minimum value for either field is 3, which corresponds to a keypad con- figuration that supports 3 × 3 + 3 SF keys (total of 12 keys). The maximum number of KP-Xx inputs is 8, and the maximum number of KP-Yx outputs is 12. If the digital multiplexer MUX2 is used, the maximum number of KP-Yx outputs is 9. If the SLOWCLKOUT pin is used, the maximum number is 8. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 0 0 0 KP-X KP-Y Field Value Description KP-X 3–8 Number of KP-Xx inputs. KP-Y 3–12 Number of KP-Yx outputs.

17.16 READ_KEY_SIZE COMMAND

The READ_KEY_SIZE command consists of a command byte (0x91) from the host and a data byte from the LM8322. The host can issue the command at any time to read the con- figuration of the keypad. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 0 0 1 KP-X KP-Y Field Value Description KP-X 3–8 Number of KP-Xx inputs. KP-Y 3–12 Number of KP-Yx outputs. 35 www.national.com LM8322

17.17 READ_CFG COMMAND

The READ_CFG command consists of a command byte (0x92) from the host and a data byte from the LM8322. The data byte returns the settings in the hardware configuration register. The default state of this register is 0x80. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 0 1 0 0 0 0 0 MUX2EN MUX2SEL MUX1EN MUX1SEL Bit Value Description MUX2EN 0 MUX2_OUT output disabled. 1 MUX2_OUT output enabled. This overrides any other function available on this pin. MUX2SEL 0 If the MUX2 EN bit is 1, the MUX2_IN1 input drives the MUX2_OUT output. 1 If the MUX2 EN bit is 1, the MUX2_IN2 input drives the MUX2_OUT output. MUX1EN 0 MUX1_OUT output disabled. 1 MUX1_OUT output enabled. This overrides any other function available on this pin. MUX1SEL 0 If the MUX1 EN bit is 1, the MUX1_IN1 input drives the MUX1_OUT output. 1 If the MUX1 EN bit is 1, the MUX1_IN2 input drives the MUX1_OUT output.

17.18 WRITE_CLOCK COMMAND

The WRITE_CLOCK command consists of a command byte (0x93) and a data byte from the host. This command sets the clock configuration, as described in Table 2 , Section 9.3 CLOCK CONFIGURATION. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 0 1 1 CONFIGURATION

17.19 READ_CLOCK COMMAND

The READ_CLOCK command consists of a command byte (0x94) from the host and a data byte from the LM8322. This command reads bits 7:2 of the clock configuration, as de- scribed in Table 2 , Section 9.3 CLOCK CONFIGURATION. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 1 0 0 CONFIGURATION 1 0 www.national.com 36 LM8322

17.20 PWM_WRITE COMMAND

The PWM_WRITE command consists of a command byte (0x95) and three data bytes from the host. The command writes a 16-bit script command into a specified address in the script command file of the specified PWM channel. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 1 0 1 ADDRESS CH COMMAND Bit Value Description ADDRESS 0–59 Location in the PWM script command file. CH 01 PWM channel 0. 10 PWM channel 1. 11 PWM channel 2.

17.21 PWM_START COMMAND

The PWM_START command consists of a command byte (0x96) and a data byte from the host. This command starts execution of the script command file at the specified address for the specified channel. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 1 1 0 ADDRESS CH Bit Value Description ADDRESS 0–59 Start address in the PWM script command file. CH 01 PWM channel 0. 10 PWM channel 1. 11 PWM channel 2.

17.22 PWM_STOP COMMAND

The PWM_STOP command consists of a command byte (0x97) and a data byte from the host. This command stops execution of the script command file for the specified channel. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 CH Bit Value Description CH 01 PWM channel 0. 10 PWM channel 1. 11 PWM channel 2. 37 www.national.com LM8322

18.0 Absolute Maximum Ratings (Note

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) 2V Voltage at Any Pin -0.3V to VCC +0.3V Maximum Input Current Without Latchup ±100 mA ESD Protection Level (Human Body Model) 2 kV (Machine Model) 200V (Charge Device Model) 750V Total Current into VCC Pin (Source) 100 mA Total Current out of GND Pin (Sink) 100 mA Storage Temperature Range −65°C to +140°C

19.0 DC Electrical Characteristics

(Temperature: -40°C ≤ TA ≤ +85°C) Data sheet specification limits are guaranteed by design, test, or statistical analysis. Symbo l Parameter Conditions Min Typ Max Units VCC Operating Voltage 1.62 1.98 V IDD Supply Current (Note 2) Internal Clock, 1.9 3.0 mANo loads on pins, VCC = 1.9V, TC = 0.5µs (Note 4) IHALT Standby Mode Current (Note 5) Typical: VCC = 1.9V, TA = 25°C <9 40 µA VIL Logical 0 Input Voltage (Note 5) 0.3 x VCC V VIH Logical 1 Input Voltage (Note 5) 0.7 x VCC V Hi-Z Input Leakage (TRI-STATE Output) VCC = 1.8V -2 2 µA Port Input Hysteresis (Notes 5, 6) 100 400 mA Weak Pull-Up/Pull-Down Current 1.6V<VCC< 2.0V 150 µA Output Current Source (Push-Pull Mode) VCC = 1.62V, VOH = 0.7 x VCC -16 mA Output CurrentSink (Push-Pull Mode) VCC = 1.62V, VOL = 0.3 x VCC 16 mA Allowable Sink and Source Current per Pin (Note 16 mA CPAD Input Capacitance (Note 7) 5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics tables. Note 2: Supply current is measured with inputs connected to VCC and outputs driven low but not connected to a load. Note 3: TC = instruction cycle time (min. 0.7 µs). Note 4: In standby mode, the internal clock is switched off. Supply current in standby mode is measured with inputs connected to VCC and outputs driven low but not connected to a load. Note 5: Applied to all digital pins (including RESET) except for SLOWCLK when configured for an external clock.. Note 6: Guaranteed by design, not tested. Note 7: The sum of all I/O sink/source current must not e4xceed the maximum total current into VCC and out of GND as specified in the absolute maximem ratings. www.national.com 38 LM8322

20.0 AC Electrical Characteristics

(Temperature: -40°C ≤ TA ≤ +85°C) Data sheet specification limits are guaranteed by design, test, or statistical analysis. Parameter Conditions Min Typ Max Units System Clock (mclk) (Note 8) Internal RC 21 MHz 1.62V ≤ VCC ≤ 1.98V Processing and Command Execution Cycle (tC) (Note 8) 1.62V ≤ VCC ≤ 1.98V 0.5 μs System Clock, Processing and Command Execution Cycle Variation(Note 8) 7 % General-Purpose I/O (GPIO) Output Rise Time(Note 8) CLOAD = 50 pF 15 ns Output Fall Time(Note 8) 15 ns ACCESS.bus Input Signals(Note 9) Bus Free Time Between Stop and Start Condition (tBUFi) (Note 8) tSCLhigho SCL Setup Time (tCSTOsi) (Note 8) Before Stop Condition k 8 mclk SCL Hold Time (tCSTRhi) (Note 8) After Start Condition 8 mclk SCL Setup Time (tCSTRsi) (Note 8) Before Start Condition 8 mclk Data High Setup Time (tDHCsi) (Note 8) Before SCL Rising Edge (RE) 2 mclk Data Low Setup Time (tDLCsi) (Note 8) Before SCL RE 2 mclk SCL Low Time (tSCLlowi) (Note 8) After SCL Falling Edge (FE) 12 mclk SCL High Time (tSCLhighi) (Note 8) After SCL RE 12 mclk SDA Hold Time (tSDAhi) (Note 8) After SCL FE 0 mclk SDA Setup Time (tSDAsi) (Note 8) Before SCL RE 2 mclk ACCESS.bus Output Signals (Note 9) Bus Free Time Between Stop and Start Condition (tBUFo)(Note 9) tSCLhigho SCL Setup Time (tCSTOso) (Note 8) Before Stop Condition tSCLhigho SCL Hold Time (tCSTRho) (Note 8) After Start Condition tSCLhigho SCL Setup Time (tCSTRso) (Note 8) Before Start Condition tSCLhigho Data High Setup Time (tDHCso) (Note 8) Before SCL RE tSCLhigho Data Low Setup Time (tDLCso) (Note 8) Before SCL RE tSCLhigho SCL Low Time (tSCLlowo) (Note 8) After SCL FE 16 mclk SCL High Time (tSCLhigho) (Note 8) After SCL RE 16 mclk SDA Hold Time (tSDAho) (Note 8) After SCL FE 7 mclk SDA Valid Time (tSDAso) (Note 8) Before SCL RE 7 mclk Note 8: Guaranteed by design, not tested. Note 9: The ACCESS.bus interface implements and meets the timing necessary for interface to the I2C and SMBus protocol at logic levels. The bus drivers are designed with open-drain output for bidirectional operation. The will not meet the AC timing and current/voltage requirements of the full bus specification. 39 www.national.com LM8322

FIGURE 19. ACB Start and Stop Condition Timing

21.0 Physical Dimensions inches (millimeters) unless otherwise noted

41 www.national.com LM8322

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