LM8272 TI1 | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community LM8272 SNOS515F – OCTOBER 2000– REVISED AUGUST 2015 LM8272DualRRIO,HighOutputCurrent&UnlimitedCapLoad OpAmpinMiniaturePackage
1 Features 3 Description
The LM8272 is a Rail-to-Rail input and output Op1(VS = 12V, TA = 25°C, Typical values unless Amp which can operate with a wide supply voltagespecified). range. This device has high output current drive,• GBWP 15MHz greater than Rail-to-Rail input common mode voltage
- Wide supply voltage range 2.5 V to 24 V range, and unlimited capacitive load drive capability, while requiring only 0.95mA/channel supply current. It• Slew rate 15 V/µs is specifically designed to handle the requirements of• Supply current/channel 0.95 mA flat panel TFT panel VCOM driver applications as well
- Cap load tolerance Unlimited as being suitable for other low power and medium speed applications which require ease of use and• Output short circuit current ±13 0mA enhanced performance over existing devices.• Output current (1 V from rails) ±65 mA Greater than Rail-to-Rail input common mode voltage• Input common mode voltage 0.3 V beyond rails range with 50 dB of Common Mode Rejection allows• Input voltage noise 15 nV/√Hz high side and low side sensing among many
- Input current noise 1.4 pA/√Hz applications without concerns for exceeding the range and with no compromise in accuracy. An
2 Applications exceptionally wide operating supply voltage range of
2.5 V to 24 V removes any concerns over• TFT-LCD flat panel VCOM driver functionality under extreme conditions and offers• A/D converter buffer flexibility of use in multitude of applications. In
- High side/low side sensing addition, most device parameters are insensitive to power supply variations. This design enhancement is• Headphone amplifier yet another step in simplifying its usage. The LM8272 is offered in the 8-pin VSSOP package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM8272 VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Large Signal Step ResponseSimplified Schematic for Various Cap. Load An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNOS515F – OCTOBER 2000– REVISED AUGUST 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (August 2014) to Revision F Page Changes from Revision D (March 2013) to Revision E Page
- Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Mechanical, Packaging, and Changes from Revision C (March 2013) to Revision D Page
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5 Pin Configuration and Functions
1 OUT A O Output A
2 -IN A I Inverting Input A 3 +IN A I Non-Inverting Input A
4 V- I Negative Supply
5 +IN B I Non-Inverting Input B 6 -IN B I Inverting Input B
7 OUT B O Output B
8 V+ I Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Differential +/−10 V Output Short Circuit Duration See(3)(4) Supply Voltage (V+ - V−) 27 V Voltage at Input/Output pins V+ +0.3, V− −0.3 V Junction Temperature(5) +150 °C Storage temperature range, Tstg −65 +150 °C Soldering Information: Infrared or Convection (20 sec.) 235 °C Wave Soldering (10 sec.) 260 °C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Rating indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. (4) Output short circuit duration is infinite for VS ≤ 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5 ms. (5) The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) ±2000 V(ESD) Electrostatic discharge(1) V Machine Model (MM)(3) ±200 (1) Human body model, 1.5 kΩ in series with 100 pF. Machine Model, 0 Ω is series with 200 pF. (2) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. (3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply Voltage (V+ - V−) 2.5 24 V Operating Temperature Range(1) −40 +85 °C (1) The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
6.4 Thermal Information
THERMAL METRIC(1) UNIT
8 Pins
RθJA Junction-to-ambient thermal resistance(2) 235 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
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www.ti.com SNOS515F – OCTOBER 2000– REVISED AUGUST 2015 6.5 5V Electrical Characteristics Unless otherwise specified, all limited ensured for V+ = 5V, V− = 0V, VCM = 0.5V, VO = V+/2, and RL > 1MΩ to V−. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS TYP(1) LIMIT(2) UNIT VOS Input Offset Voltage VCM = 0.5V & VCM = 4.5V +/−5 mV+/−0.7 +/− 7 max TC VOS Input Offset Average Drift VCM = 0.5V & VCM = 4.5V(3) +/−2 — µV/°C IB Input Bias Current See (4) ±2.00 µA— ±2.70 max IOS Input Offset Current 250 nA20 400 max CMRR Common Mode Rejection Ratio VCM stepped from 0V to 5V 64 dB80 61 min +PSRR Positive Power Supply Rejection Ratio V+ from 4.5V to 13V 78 dB100 74 min CMVR Input Common-Mode Voltage Range CMRR > 50dB −0.1 V−0.3 0.0 max 5.1 V5.3 5.0 min AVOL Large Signal Voltage Gain VO = 0.5 to 4.5V, 64 dB80RL = 10kΩ to V+/2 60 min VO Output Swing RL = 10kΩ to V− 4.93 4.85 V High minISOURCE = 5mA 4.85 4.70 Output Swing RL = 10kΩ to V+ 215 250 mV Low maxISINK = 5mA 300 350 ISC Output Short Circuit Current Sourcing to V− 100 —VID = 200mV(5) mA Sinking to V+ 100 —VID = −200mV(5) IOUT Output Current VID = ±200mV, VO = 1V from rails ±55 — mA IS Supply Current (Both Channel) No load, VCM = 0.5V 2.3 mA1.8 2.8 max SR Slew Rate(6) AV = +1, VI = 5VPP 12 — V/µs fu Unity Gain Frequency VI = 10mVp, RL = 2KΩ to V+/2 7.5 — MHz GBWP Gain-Bandwidth Product f = 50KHz 13 — MHz Phim Phase Margin VI = 10mVp, RL = 2kΩ to V+/2 55 — deg en Input-Referred Voltage Noise f = 2KHz, RS = 50Ω 15 — nV/√Hz in Input-Referred Current Noise f = 2KHz 1.4 — pA/√Hz fmax Full Power Bandwidth ZL = (20pF || 10kΩ) to V+/2 700 — kHz (1) Typical Values represent the most likely parametric norm. (2) All limits are ensured by testing or statistical analysis. (3) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. (4) Positive current corresponds to current flowing into the device. (5) Short circuit test is a momentary test. Output short circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. (6) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM8272
SNOS515F – OCTOBER 2000– REVISED AUGUST 2015 www.ti.com 6.6 12V Electrical Characteristics Unless otherwise specified, all limited ensured for V+ = 12V, V− = 0V, VCM = 6V, VO = 6V, and RL > 1MΩ to V−. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS TYP(1) LIMIT(2) UNIT VOS Input Offset Voltage VCM = 0.5V & VCM = 11.5V +/−7 mV+/−0.7 +/− 9 max TC VOS Input Offset Average Drift VCM = 0.5V & VCM = 11.5V(3) +/−2 — µV/°C IB Input Bias Current See (4) ±2.00 µA— ±2.80 max IOS Input Offset Current 275 nA30 550 max CMRR Common Mode Rejection Ratio VCM stepped from 0V to 12V 74 dB88 72 min +PSRR Positive Power Supply Rejection Ratio V+ from 4.5V to 13V, VCM = 0.5V 78 dB100 74 min −PSRR Negative Power Supply Rejection Ratio 85 — dB CMVR Input Common-Mode Voltage Range CMRR > 50dB −0.1 V−0.3 0 max 12.1 V12.3 12.0 min AVOL Large Signal Voltage Gain VO = 1V to 11V 74 dB83RL = 10kΩ to V+/2 70 min VO Output Swing RL 10kΩ to V+/2 11.8 11.7 V High minISOURCE = 5mA 11.6 11.5 Output Swing RL = 10kΩ to V+/2 0.25 0.3 V Low maxISINK = 5mA .40 .45 ISC Output Short Circuit Current Sourcing to V− 130 110VID = 200mV (5) mA minSinking to V+ 130 110VID = 200mV (5) IOUT Output Current VID = ±200mV, VO = 1V from rails ±65 — mA IS Supply Current (Both Channel) No load, VCM = 0.5V 2.4 mA1.9 2.9 max SR Slew Rate(6) AV = +1, VI = 10VPP, CL = 10pF 15 — V/µs AV = +1, VI = 10VPP, CL = 0.1µF 1 — ROUT Close Loop Output Resistance AV = +1, f = 100KHz 3 — Ω fu Unity Gain Frequency VI = 10mVp, RL = 2kΩ to V+/2 8 — MHz GBWP Gain-Bandwidth Product f = 50KHz 15 — MHz Phim Phase Margin VI = 10mVp, RL = 2kΩ to V+/2 57 — Deg GM Gain Margin VI = 10mVp, RL = 2kΩ to V+/2 20 — dB −3dB BW Small Signal -3db Bandwidth AV = +1, RL = 2kΩ to V+/2 12.5 — AV = +1, RL = 600Ω to V+/2 10.5 — MHz AV = +10, RL = 600Ω to V+/2 1.0 — (1) Typical Values represent the most likely parametric norm. (2) All limits are ensured by testing or statistical analysis. (3) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. (4) Positive current corresponds to current flowing into the device. (5) Short circuit test is a momentary test. Output short circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. (6) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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www.ti.com SNOS515F – OCTOBER 2000– REVISED AUGUST 2015 Unless otherwise specified, all limited ensured for V+ = 12V, V− = 0V, VCM = 6V, VO = 6V, and RL > 1MΩ to V−. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS TYP(1) LIMIT(2) UNIT en Input-Referred Voltage Noise f = 2KHz, RS = 50Ω 15 — nV/√Hz in Input-Referred Current Noise f = 2KHz 1.4 — pA/√Hz fmax Full Power Bandwidth ZL = (20pF || 10kΩ) to V+/2 300 — kHz THD+N Total Harmonic Distortion +Noise AV = +2, RL = 2kΩ to V+/2 0.02% —VO = 8VPP, VS = ±5V CT Rej. Cross-Talk Rejection f = 5MHz, Driver RL = 10kΩ to V+/2 68 — dB Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM8272
6.7 Typical Performance Characteristics
Figure 1. VOS Distribution Figure 2. VOS vs. VCM for 3 Representative Units Figure 3. VOS vs. VCM for 3 Representative Units Figure 4. VOS vs. VCM for 3 Representative Units Figure 6. VOS vs. VS for 3 Representative Units Figure 5. VOS vs. VS for 3 Representative Units
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Figure 14. CMRR vs. FrequencyFigure 13. IS vs. VS Figure 15. +PSRR vs. Frequency Figure 16. −PSRR vs. Frequency Figure 17. Open Loop Gain/Phase Figure 18. Closed Loop Frequency Response
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Figure 26. VOUT from V+ vs. ISOURCEFigure 25. Settling Time (±1%) & Slew Rate vs. Cap Load Figure 28. Step Response for Various AmplitudesFigure 27. VOUT from V− vs. ISINK Figure 29. Step Response for Various Amplitudes Figure 30. Large Signal Step Response
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7 Application and Implementation
7.1 Block Diagram and Operational Description
offset voltage will also be effected by changes in VCM across the differential pair transition region. Figure 35. Simplified Schematic Diagram
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Figure 36. Input Stage Current vs. Differential Input Voltage
7.2 B) Output Stage:
limiting alleviates the drawback to the conventional scheme which requires one Vbe reduction in output swing. resulting in the uncharacteristic feature of stability under all capacitive loads.
7.3 C) Output Voltage Swing Close to V−:
Phase Margin reduction could result in unwanted oscillations.
adding a load resistor to the output to provide the necessary Q10 minimum Collector Current (300µA). sinking current and ensure stability. This is equivalent to about 15% increase in total quiescent power dissipation.
7.4 Driving Capactive Loads:
ideal for applications such as TFT flat panel buffers, A/D converter input amplifiers, etc. load improves the settling and overshoot performance. short circuit current value by the capacitor.
7.5 Estimating the Output Voltage Swing
Figure 37. Steady State Output Sourcing Characteristics with Load Lines
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Figure 38. Steady State Output Sinking Characteristics with Load Lines
7.6 Output Short Circuit Current and Dissipation Issues:
supply voltage conditions. Below supply voltage of 6V, output short circuit condition can be tolerated indefinitely.
- IS: Supply Current
- VS: Total Supply Voltage (V+ - V−)
- VO: Average Output Voltage
- Vr: V+ for sourcing and V− for sinking current Table 1 below shows the maximum AC component of the load power dissipated by the Op Amp for standard Sinusoidal, Triangular, and Square Waveforms:
Table 1. Normalized AC Power Dissipated in the Output Stage for Standard Waveforms
SNOS515F – OCTOBER 2000– REVISED AUGUST 2015 www.ti.com The table entries are normalized to VS 2/RL. To figure out the AC load current component of power dissipation, simply multiply the table entry corresponding to the output waveform by the factor VS 2/RL. For example, with ±12V supplies, a 600Ω load, and triangular waveform power dissipation in the output stage is calculated as:
7.7 Other Application Hints:
The use of supply decoupling is mandatory in most applications. As with most relatively high speed/high output current Op Amps, best results are achieved when each supply line is decoupled with two capacitors; a small value ceramic capacitor (∼0.01µF) placed very close to the supply lead in addition to a large value Tantalum or Aluminum (> 4.7µF). The large capacitor can be shared by more than one device if necessary. The small ceramic capacitor maintains low supply impedance at high frequencies while the large capacitor will act as the charge “bucket” for fast load current spikes at the Op Amp output. The combination of these capacitors will provide supply decoupling and will help keep the Op Amp oscillation free under any load.
7.8 LM8272 Advantages:
Compared to other Rail-to-Rail Input/Output devices, the LM8272 offers several advantages such as:
- Improved cross over distortion
- Nearly constant supply current throughout the output voltage swing range and close to either rail.
- Nearly constant Unity gain frequency (fu) and Phase Margin (Phim) for all operating supplies and load conditions.
- No output phase reversal under input overload condition.
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8 Device and Documentation Support
8.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
8.2 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
8.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
8.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LM8272
www.ti.com 29-Jul-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM8272MM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 A60 LM8272MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A60 LM8272MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A60 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
www.ti.com 29-Jul-2015 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8272MM VSSOP DGK 8 1000 210.0 185.0 35.0 LM8272MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM8272MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2015 Pack Materials-Page 2
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