LM81BIMTX-3

LM81_02 NSC | Alldatasheet

Document overview

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Technical content

Features

n 6 positive voltage inputs with scaling resistors to monitor +5V, +12V, +3.3V, +2.5V, Vccp power supplies directly n 8-bit DAC output for controlling fan speed n 2 fan speed monitoring inputs n Chassis Intrusion detector input n WATCHDOG comparison of all monitored values n SMBus 1.0 (LM81C) and 1.1 (LM81B) Serial Bus interface compatibility n LM81B has improved voltage monitoring accuracy n VID0-VID4 monitoring inputs Key Specifications j Voltage Monitoring Error +2% or ±1.2% (max) j Temperature Error −40˚C to +125˚C ± 3˚C (max) j Supply Voltage Range 2.8V to 3.8V j Supply Current 0.4 mA (typ) j ADC and DAC Resolution 8 Bits j Temperature Resolution 0.5˚C

Applications

n System Thermal and Hardware Monitoring for Servers and PCs n Office Electronics n Electronic Test Equipment and Instrumentation Typical Application DS100072-1 # Indicates Active Low (“Not”) February 2002 LM81 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor © 2002 National Semiconductor Corporation DS100072 www.national.com

Ordering Information

Temperature Range NS Package Number−40˚C ≤ TA ≤ +125˚C SMBus Revision Level Voltage Monitoring ErrorOrder Number Device Marking LM81BIMT-3 1 LM81BIMT-3 MTC24B 1.1 ±1.2% LM81BIMTX-3 2 LM81BIMT-3 MTC24B 1.1 ±1.2% LM81CIMT-3 1 LM81CIMT-3 MTC24B 1.0 +2% LM81CIMTX-3 2 LM81CIMT-3 MTC24B 1.0 +2% Note:1-Rail transport media, 62 parts per rail 2-Tape and reel transport media, 3400 parts per reel Connection Diagram DS100072-3 LM81 www.national.com 2

Name(s) Pin Number Number of Pins Type Description A0/NTEST_OUT 1 1 Digital I/0 The lowest order programmable bit of the serial bus address. This pin functions as an output during NAND Tree tests (board-level connectivity testing). Refer to SECTION 11 on NAND Tree testing. A1 2 1 Digital Input The highest order programmable bit of the serial bus address. SMBData 3 1 Digital I/O Serial Bus bidirectional Data. Open-drain output. SMBCLK 4 1 Digital Input Serial Bus Clock. FAN1-FAN2 5-6 2 Digital Inputs Schmitt Trigger fan tachometer inputs. CI 7 1 Digital I/O An active high input from an external circuit which latches a Chassis Intrusion event. This line can go high without any clamping action regardless of the powered state of the LM81. There is also an internal open-drain output on this line, controlled by Bit 6 of the Configuration Register (40h) or Bit 7 CI Clear Register (46h), to provide a minimum 20 ms reset pulse. See Section 3.3and Section 9.0. T_CRIT_A 8 1 Digital Output Critical Temperature Alarm active low open-drain output. This pin can be grounded when not used. V+ (+2.8V to +3.8V) 9 1 POWER +3.3V V + power. Bypass with the parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors. DS100072-2 LM81 www.national.com3

Pin Description(Continued) Pin Name(s) Pin Number Number of Pins Type Description INT 10 1 Digital Output Interrupt active low open-drain output. This output is enabled when Bit 1 in the Configuration Register is set to 1. The default state is disabled. DACOut/NTEST_IN 11 1 Analog Output/Digital Input 0V to +1.25V amplitude 8-bit DAC output. When forced high by an external voltage the NAND Tree Test mode is enabled which provides board-level connectivity testing. Refer to Section 11.0 on NAND Tree testing. RESET 12 1 Digital I/O Master Reset, 5 mA driver (open-drain), active low output with a 20 ms minimum pulse width. Available when enabled via Bit 4 in the Configuration register. It acts as an active low power on RESET input. GND 13 1 GROUND Internally connected to all circuitry. The ground reference for all analog inputs and the DAC output. This pin needs to be connected to a low noise analog ground plane for optimum performance of the DAC output. Vccp2 14 1 Analog Input Analog input for monitoring −12V or Vccp2. Selectable by choosing the appropriate external resistor divider values such that the input to the LM81 is scaled to +2.5V. See Section 4.0. +12Vin 15 1 Analog Input Analog input for monitoring +12V. +5Vin 16 1 Analog Input Analog input for monitoring +5V. +3.3Vin 17 1 Analog Input Analog input for monitoring +3.3V. +2.5Vin 18 1 Analog Input Analog input for monitoring +2.5V. Vccp1 19 1 Analog Input Analog input for monitoring Vccp, a processor voltage that is nominally at +2.5V. VID4-VID0 20-24 5 Digital Inputs Supply Voltage readouts from the Pentium/PRO power supplies that indicate the operating voltage or the processor (e.g. 1.5V to 2.9V). The values are read in the VID/Fan Divisor Register and the VID4 Register. TOTAL PINS 24 LM81 www.national.com 4

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (V +) +6.0V Voltage on Any Input or Output Pin: +12Vin, T_CRIT_A −0.3V to +15V A0, A1, DACOut −0.3V to (V ++ 0.3V) +2.5Vin, +3.3Vin (Note 3) All other pins −0.3V to +6V Input Current at any Pin (Note 4) ±5m A Package Input Current (Note 4) ±20 mA Maximum Junction Temperature (TJ max) 150˚C ESD Susceptibility (Note 6) Human Body Model 2000V Machine Model 200V Soldering Information Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 235˚C Storage Temperature −65˚C to +150˚C Operating Ratings(Notes 1, 2) Operating Temperature Range T MIN ≤ TA ≤ TMAX Specified Temperature Range T MIN ≤ TA ≤ TMAX Junction to Ambient Thermal Resistance (θJA (Note 5)) Supply Voltage (V+) +2.8V to +3.8V VIN Voltage Range: +12Vin −0.05V to +15V +5Vin −0.05V to +6.8V +3.3Vin −0.05V to +4.6V +2.5Vin −0.05V to +3.6V VID0 - VID4, Vccp, FAN1-FAN2 −0.05V to +6.0V All other inputs −0.05V to (V + + 0.05V) The following specifications apply for +2.8VDC ≤ V+ ≤ +3.8VDC ,R S = 500Ω , unless otherwise specified.Boldface limits apply for TA =T J =T MIN to TMAX ;all other limits TA =T J = 25˚C. (Note 8) Symbol Parameter Conditions Typical Limits LM81BIM Limits LM81CIM Units (Note 9) (Note 10) (Note 10) (Limits) POWER SUPPLY CHARACTERISTICS I + Supply Current Interface Inactive 0.4 1.4 0.9 mA (max) TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS Error −40˚C ≤ TA ≤ +125˚C ±3 ±3 ˚C (max) Resolution 9-bit mode 12-bit mode 0.5 0.0625 0.5 0.0625 ˚C (min) ˚C (min) LM81 ANALOG-TO-DIGITAL CONVERTER CHARACTERISTICS Resolution 8 bits TUE Total Unadjusted Error +2.5Vin, +3.3Vin, +5Vin (Notes 11, 12) +1.2 −1.2 +0.8 % (max) % (min) Vccp1, Vccp2 (Note 11) +1.2 −1.2 +2.4 % (max) % (min) +12Vin (Notes 11, 12) +1.2 −1.2 +3.1 +1.2 % (max) % (min) DNL Differential Non-Linearity ±1 ±1 LSB (max) PSS Power Supply Sensitivity ±0.4 %/V tC Total Monitoring Cycle Time (Note 13) 9-bit Temp Resolution 12-bit Temp Resolution 0.4 0.82 1.2 0.82 1.2 sec sec (max) sec (max) ADC INPUT CHARACTERISTICS Input Resistance (All analog inputs except Vccp1 and Vccp2) 115 90 90 kΩ (min) Vccp1 and Vccp2 DC Input Current ±1µ A LM81 www.national.com5

The following specifications apply for +2.8VDC ≤ V+ ≤ +3.8VDC ,R S = 500Ω , unless otherwise specified.Boldface limits apply for TA =T J =T MIN to TMAX ;all other limits TA =T J = 25˚C. (Note 8) Symbol Parameter Conditions Typical Limits LM81BIM Limits LM81CIM Units (Note 9) (Note 10) (Note 10) (Limits) DAC CHARACTERISTICS Resolution 8 Bits DAC Error V + = 3.3V ±5 ±62.5 ±10 ±125 ±62.5 % (max) mV (max) % (max) mV (max) DAC Error Temperature Sensitivity 100 100 ppm/˚C (max) DAC Error Power Supply Sensitivity 0.5 0.725 % (max) R L Output Load Resistance V O = 1.25V 625 625 Ω (min) C L Output Load Capacitance 20 20 pF (max) FAN RPM-TO-DIGITAL CONVERTER Fan RPM Error +25˚C ≤ TA ≤ +75˚C ±10 ±10 % (max) Full-scale Count 255 255 (max) FAN1 and FAN2 Nominal Input RPM (See Section 6.0) Divisor = 1, Fan Count = 153 (Note 14)

8800 RPM

Divisor = 2, Fan Count = 153 (Note 14)

4400 RPM

Divisor = 3, Fan Count = 153 (Note 14)

2200 RPM

Divisor = 4, Fan Count = 153 (Note 14)

1100 RPM

Internal Clock Frequency +25˚C ≤ TA ≤ +75˚C 22.5 20.2 20.2 kHz (min) 24.8 24.8 kHz (max) −10˚C ≤ TA ≤ +100˚C 22.5 19.1 19.1 kHz (min) 25.9 25.9 kHz (max) kHz (min) kHz (max) LM81 www.national.com 6

The following specifications apply for +2.8VDC ≤ V+ ≤ +3.8VDC ,R S = 500Ω , unless otherwise specified.Boldface limits apply for TA =T J =T MIN to TMAX ;all other limits TA =T J = 25˚C. (Note 8) Symbol Parameter Conditions Typical Limits LM81BIM Limits LM81CIM Units (Note 9) (Note 10) (Note 10) (Limits) DIGITAL OUTPUTS (NTEST_OUT) V OUT(1) Logical “1” Output Voltage I OUT = ±3.0 mA at V+ = +2.8V 2.4 2.4 V (min) VOUT(0) Logical “0” Output Voltage I OUT = ±3.0 mA at V+ = +3.8V 0.4 0.4 V (max) OPEN- DRAIN DIGITAL OUTPUTS (SMBData, RESET, CI, INT, T_CRIT_A) VOUT(0) Logical “0” Output Voltage I OUT = −3.0 mA 0.4 0.4 V (min) IOH High Level Output Current V OUT =V + 0.1 100 100 µA (max) RESET and Chassis Intrusion 45 20 20 ms (min) Pulse Width DIGITAL INPUTS: VID0–VID4, NTEST_IN, A0/NTEST_OUT, A1, Chassis Intrusion (CI) VIN(1) Logical “1” Input Voltage 2.0 2.0 V (min) VIN(0) Logical “0” Input Voltage 0.8 0.8 V (max) SMBus DIGITAL INPUTS (SMBCLK, SMBData) VIN(1) Logical “1” Input Voltage 2.1 1.4 V (min) VIN(0) Logical “0” Input Voltage 0.8 0.6 V (max) Tach Pulse Logic Inputs (FAN1, FAN2) VIN(1) Logical “1” Input Voltage 0 . 7xV+ 0 . 7xV+ V (min) VIN(0) Logical “0” Input Voltage 0 . 3xV+ 0 . 3xV+ V (max) ALL DIGITAL INPUTS IIN(1) Logical “1” Input Current V IN =V + −0.005 −1 −1 µA (min) IIN(0) Logical “0” Input Current V IN =0V DC 0.005 11 µA (max) C IN Digital Input Capacitance 20 pF LM81 www.national.com7

FIGURE 1. Serial Bus Timing Diagram

Note 2:All voltages are measured with respect to GND, unless otherwise specified. maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four. allowable power dissipation at any temperature is PD =( TJ max−T A)/θJA. a temperature or voltage measurement. Note 9: Typicals are at TJ =T A = 25˚C and represent most likely parametric norm. Note 10:Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11:TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC. Note 12:Guaranteed at 3/4 scale±15%. typical, at 4400 rpm, and 200 ms maximum. Note 14: The total fan count is based on 2 pulses per revolution of the fan tachometer output. Note 15:Timing specifications are tested at the specified logic levels, VILfor a falling edge and VIH for a rising edge. An x indicates that the diode exists. FIGURE 2. ESD Protection Input Structure

1.0 GENERAL DESCRIPTION

continuously converts the scaled inputs to 8-bit digital words. with a 0.5˚C LSB or 0.0625˚C LSB, respectively.

• Configuration Register: Provides control and con- figuration.
• Interrupt Status Registers:Two registers to provide status of each WATCHDOG limit or Interrupt event.
• Interrupt Mask Registers: Allows masking of indi- vidual Interrupt sources, as well as separate masking for each of the two hardware Interrupt outputs.
• CI Clear Register: Allows transmitting a 20 ms low pulse on the chassis intrusion pin (CI).
• VID/Fan Divisor Register:This register contains the state of the VID0-VID3 input lines and the divisor bits for FAN1 and FAN2 inputs.
• Serial Bus Address Register:Contains the Serial Bus address. At power on it assumes the default value of 01011XX binary, and can be altered by the state of A0 and A1.
• VID4 Register:Contains the state of the VID4 input.
• Temperature Configuration Register:Selects the in- terrupt mode and contains the 0.5˚C LSB of the tempera- ture reading.
• Extended Mode Registers: Enable and control the Extended Mode which includes the LSBs of the 12-bit temperature reading, T_CRIT, and T HYST
• Value RAM: The DAC digital input, monitoring results (temperature, voltages, fan counts), WATCHDOG limits, and Company/Stepping IDs are all contained in the Value RAM. The Value RAM consists of a total of 34 bytes, addresses 15h - 3Fh, containing: — byte 1 at address 15h a manufacturers test register — locations 16h - 18h are unassigned and do not have associated registers — byte 2 at address 19h contains the DAC Data Register — locations 1Ah - 1Fh are unassigned and do not have associated registers — the next 10 bytes at addresses 20h -29h contain all of the results, with address 26h reserved — the next 18 bytes at addresses 2Bh-3Ch are the WATCHDOG limits — the last 2 bytes at addresses 3Eh and 3Fh contain the Company ID and Stepping ID numbers, respectively When the LM81 is started, it cycles through each measure- ment in sequence, and it continuously loops through the sequence approximately once every 400 ms. Each mea- sured value is compared to values stored in WATCHDOG, or Limit registers. When the measured value violates the pro- grammed limit the LM81 will set a corresponding Interrupt in the Interrupt Status Registers. The hardware Interrupt line INT is fully programmable with separate masking of each DS100072-6

FIGURE 3. Digital Output Load Test Circuitry

a control bit to enable or disable the hardware Interrupt. ting bit 4 of Extended Mode Register 1. case is removed from the computer.

2.0 INTERFACE

FIGURE 4. LM81 Register Structure

2.1 Internal Registers of the LM81

TABLE 1. The internal registers and their corresponding internal LM81 addresses are as follows: Serial Bus address input pins. VID4 Register 49h 1000 000X The lower bit reflects the state of VID4 input.

2.2 Serial Bus Interface

separate asynchronous internal clock.

1. If the Internal Address Register is known to already be at
2. If the Internal Address Register value is unknown, or if it

always reflect the state of the A0 and A1 input pins. FIGURE 5. Serial Bus Timing

Functional Description(Continued)

3.0 USING THE LM81

3.1 Power On

When power is first applied, the LM81 performs a “power on reset” on several of its registers. The power on condition of the LM81’s registers in shown in Table 1Registers whose power on values are not shown have power on conditions that are indeterminate (this includes the value RAM ,exclu- sive of the DAC data, and WATCHDOG limits). When power is first applied the ADC is inactive. In most applications, usually the first action after power on is usually to write WATCHDOG limits into the Value RAM. Register values can be returned to their default values after power is applied to the LM81 by taking RESET low for at least 50 ns.

3.2 Resets

Configuration Register INITIALIZATION accomplishes the same function as power on reset on most registers. The Value RAM conversion results, and Value RAM WATCH- DOG limits are not Reset and will be indeterminate immedi- ately after power on. If the Value RAM contains valid con- version results and/or Value RAM WATCHDOG limits have been previously set, they will not be affected by a Configu- ration Register INITIALIZATION. Power on reset, or Configu- ration Register INITIALIZATION, clear or initialize the follow- ing registers (the initialized values are shown on Table 1:

• Configuration Register
• Interrupt Status Register 1
• Interrupt Status Register 2
• INT Mask Register 1
• INT Mask Register 2
• VID/Fan Divisor Register
• Serial Bus Address Register (Power on reset only, not reset by Configuration Register INITIALIZATION)
• VID4 Register
• Temperature Configuration Register
• Extended Mode Register 1
• Extended Mode Register 2 Configuration Register INITIALIZATION is accomplished by setting Bit 7 of the Configuration Register high. This bit automatically clears after being set.

3.3 Using the Configuration Register

The Configuration Register controls the LM81 operation. At power on, the ADC is stopped and INT_Clear is asserted, clearing the INT hardwire output. The Configuration Register starts and stops the LM81, enables and disables interrupt output, and provides the Reset function described in Section 3.2. Bit 0 of the Configuration Register controls the monitoring loop of the LM81. Setting Bit 0 low stops the LM81 monitor- ing loop and puts the LM81 in shutdown mode, reducing power consumption. Serial Bus communication can take place with any register in the LM81 although activity on the SMBData and SMBCLK lines will increase shutdown current, up to as much as maximum rated supply current, while the activity takes place. Taking Bit 0 high starts the monitoring loop, described in more detail subsequently. Bit 1 of the Configuration Register enables the INT Interrupt hardwire output when this bit is taken high. Bit 3 of the Configuration Register clears the INT output when set high, without affecting the contents of the Interrupt Status Registers. The LM81 will stop monitoring. It will re- sume upon clearing of this bit. Bit 4 of the Configuration Register provides an active low 20 ms pulse at the RESET output when set high. The CI_Clear provides an active low 20 ms pulse at the CI output pin when set high. This is intended for resetting the Chassis Intrusion circuitry. The INITIALIZATION bit resets the internal registers of the LM81 as described in Section 3.2.

3.4 Starting Conversions

The monitoring function (Analog inputs, temperature, and fan speeds) in the LM81 is started by writing to the Configu- ration Register and setting INT_Clear (Bit 3), low, and Start (bit 0), high. The LM81 then performs a “round-robin” moni- toring of all analog inputs, temperature, and fan speed inputs approximately once every 400 ms. The sequence of items being monitored corresponds to locations in the Value RAM and is: 1. Temperature 2. Vccp2 3. +12Vin 4. +5Vin 5. +3.3Vin 6. Vccp1 7. +2.5Vin 8. Fan 1 9. Fan 2 DACOut immediately changes after the DAC Data Register in the Value RAM has been updated. For a zero to full scale transition DACOut will typically settle within 100 µsec of the stop by master in the write to the DAC Data Register Serial Bus transaction. The DAC Data Register is not reset by the INITIALIZATION bit found in the Configuration Register. LM81 www.national.com 14

3.5 Reading Conversion Results

The conversion results are available in the Value RAM. updates of Interrupt Status Registers and Interrupt Output’s.

1. Start the LM81 monitoring process

3.6 Digital Communication Noise Considerations

make it impervious to noise.

4.0 ANALOG INPUTS

All analog input voltages are digitized to 8-bits of resolution. Figure 6. The resistor values LM81 for a nominal reading of 89.

4.1 Analog Input Interrupts

FIGURE 6. Input Examples. Resistor values shown in table provide approximately 1.25V at the Vccp inputs.

Functional Description(Continued) equal to its LOW limit will cause a flag to be set in its Interrupt Status Register. This flag will activate the INT out- put when its mask bit is set low. Mask bits are found in the Interrupt Mask Registers.

5.0 LAYOUT AND GROUNDING

A separate, low-impedance ground plane for analog ground, which provides a ground point for both GND pins, voltage dividers and other analog components, will provide best performance but is not mandatory. Analog components such as voltage dividers should be located physically as close as possible to the LM81. The power supply bypass, the parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass ca- pacitors connected between pin 12 and ground, should also be located as close as possible to the LM81.

6.0 FAN INPUTS

The FAN1 and FAN2 inputs accept signals from fans equipped with tachometer outputs. These are logic-level inputs with an approximate threshold of V +/2. Signal condi- tioning in the LM81 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 to V +. In the event these inputs are supplied from fan outputs which exceed 0 to V+, either resistive division or diode clamping must be included to keep inputs within an acceptable range, as shown in Figure 7.R 2i s selected so that it does not develop excessive voltage due to input leakage. R1 is selected based on R2 to provide a minimum input of 2V and a maximum of V +. R1 should be as low as possible to provide the maximum possible input up to V + for best noise immunity. Alternatively, use a shunt refer- ence or zener diode to clamp the input level. If fans can be powered while the power to the LM81 is off, the LM81 inputs will provide diode clamping. Limit input current to the Input Current at Any Pin specification shown in the ABSOLUTE MAXIMUM RATINGS section. In most cases, open collector outputs with pull-up resistors inher- ently limit this current. If this maximum current could be exceeded, either a larger pull up resistor should be used or resistors connected in series with the fan inputs. The Fan Inputs gate an internal 22.5 kHz oscillator for one period of the Fan signal into an 8-bit counter (maximum count = 255). The default divisor, located in the VID/Fan Divisor Register, is set to 2 (choices are 1, 2, 4, and 8) providing a nominal count of 153 for a 4400 rpm fan with two pulses per revolution. Typical practice is to consider 70% of normal RPM a fan failure, at which point the count will be 219. Determine the fan count according to: Note that Fan 1 and Fan 2 Divisors are programmable via the VID/Fan Divisor Register. Fan tachometer outputs that provide one pulse per revolu- tion should use a divisor setting twice that of outputs that provide two pulses per revolution. For example, a 4400 RPM fan that provides one pulse per revolution should have the divisor set to 4 such that the nominal counter output is 153. LM81 www.national.com 16

Counts are based on 2 pulses per revolution tachometer outputs. FIGURE 7. Alternatives for Fan Inputs

7.0 DAC OUTPUT

verter) with an output range of 0 to 1.25 volts (4.88 mV LSB). output, insuring that full fan speed is the default condition. pins inputs, thus disabling any response from the LM81. LM81 input to prevent negative excursions. Figure 8. R4 is used FIGURE 8. Amplifier circuit for connection between DAC output and fan.

8.0 TEMPERATURE MEASUREMENT SYSTEM

8.1 Temperature Data Format

with an LSB (Least Significant Bit) equal to 1˚C. FIGURE 9. 9-bit Temperature-to-Digital Transfer FIGURE 10. 12-bit Temperature-to-Digital Transfer

8.2 Temperature Interrupts

and operates in the following way: T_CRIT_A is disabled. indefinitely until reset by reading Interrupt Status Register 1. HIHYST the interrupt will not be activated. and operates in the following way: T_CRIT_A is disabled. indefinitely until reset by reading Interrupt Status Register 1. *Note:Interrupt resets occur only when interrupt Status Register 1 is read. FIGURE 11. Normal Repetitive Interrupt Response *Note:Interrupt resets occur only when interrupt Status Register 1 is read. FIGURE 12. One-Time Interrupt Response Diagram *Note:Interrupt resets occur only when interrupt Status Register 1 is read. FIGURE 13. Normal Comparator Mode

9.0 THE LM81 INTERRUPT STRUCTURE

External Interrupts can come from the following source.

• Chassis Intrusion:This is an active high interrupt from any type of device that detects and captures chassis intrusion violations. This could be accomplished me- chanically, optically, or electrically, and circuitry external to the LM81 is expected to latch the event. The design of the LM81 allows this input to go high even with no power applied to the LM81, and no clamping or other interfer- ence with the line will occur. This line can also be pulled low for at least 20 ms by the LM81 to reset a typical Chassis Intrusion circuit. Accomplish this reset by setting Bit 7 of CI Clear Register (45h) high. The bit in the Register is self-clearing. All interrupts are indicated in the two Interrupt Status Regis- ters. The INT output has two mask registers, and individual DS100072-22

FIGURE 17. Interrupt Structure

Functional Description(Continued) masks for each Interrupt. As described in Section 3.3, the hardware Interrupt line can also be enabled/disabled in the Configuration Register. T_CRIT_A interrupt is dedicated to temperature and is indi- cated in Extended Mode Register 1. Extended Mode Regis- ter 1 controls T_CRIT_A.

9.1 Interrupt Clearing

Reading a Status Register will output the contents of the Register, and reset the Register. A subsequent read done before the analog “round-robin” monitoring loop is complete will indicate a cleared Register. Allow at least 820 ms to allow all Registers to be updated between reads. In summary, the Interrupt Status Register clears upon being read, and re- quires at least 400 ms to be updated. When the Interrupt Status Register clears, the hardware interrupt line will also clear until the Registers are updated by the monitoring loop. The hardware Interrupt line (INT) is cleared with the INT_Clear bit, which is Bit 3 of the Configuration Register. When this bit is high, the LM81 monitoring loop will stop. It will resume when the bit is low.

10.0 RESET I/O

RESET is intended to provide a master reset to devices connected to this line. INT Mask Register 2, Bit 7, must be set high to enable this function. Setting Bit 4 in the Configu- ration Register high outputs a least 20 ms low on this line, at the end of which Bit 4 in the Configuration Register automati- cally clears. Again, the label for this pin is only its suggested use. In applications where the RESET capability is not needed it can be used for any type of digital control that requires a 20 ms active low open-drain output. RESET operates as an input when not activated by the Configuration Register. Setting this line low will reset all of the registers in the LM81 to their power on default state. All Value RAM locations will not be affected except for the DAC Data Register.

11.0 NAND TREE TESTS

A NAND tree is provided in the LM81 for Automated Test Equipment (ATE) board level connectivity testing. DACOut/ NTEST_IN, T_CRIT_A, V + and GND pins are excluded from NAND tree testing. Taking DACOut/NTEST_IN high before the first write to the configuration register activates the NAND Tree test mode. After the first write to the configura- tion register the NAND Tree test mode cannot be reacti- vated. To perform a NAND tree test all pins included in the NAND tree should be driven to 1 forcing the A0/ NTEST_OUT high. Each individual pin starting with A1 and concluding with SMBData (excluding DACOut/NTEST_IN, T_CRIT_A, V + and GND) can be taken low with the resulting toggle observed on the A0/NTEST_OUT pin. Allow for a typical propagation delay of 500 ns. DS100072-29 LM81 www.national.com23

Functional Description(Continued)

12.0 FAN MANUFACTURERS

Manufacturers of cooling fans with tachometer outputs are listed below: NMB Tech 9730 Independence Ave. Chatsworth, California 91311 818 341-3355 818 341-8207 Model Num- ber Frame Size Airflow CFM 2408NL 2.36 in sq. X 0.79 in 9-16 (60 mm sq. X 20 mm) 2410ML 2.36 in sq. X 0.98 in 14-25 (60 mm sq. X 25 mm) 3108NL 3.15 in sq. X 0.79 in 25-42 (80 mm sq. X 20 mm) 3110KL 3.15 in sq. X 0.98 in 25-40 (80 mm sq. X 25 mm) Mechatronics Inc. P.O. Box 20 Mercer Island, WA 98040 800 453-4569 Various sizes available with tach output option. Sanyo Denki America, Inc. 468 Amapola Ave. Torrance, CA 90501 310 783-5400 Model Number Frame Size Airflow CFM 109P06XXY601 2.36 in sq. X 0.79 in 11-15 (60 mm sq. X 20 mm) 109R06XXY401 2.36 in sq. X 0.98 in 13-28 (60 mm sq. X 25 mm) 109P08XXY601 3.15 in sq. X 0.79 in 23-30 (80 mm sq. X 20 mm) 109R08XXY401 3.15 in sq. X 0.98 in 21-42 (80 mm sq. X 25 mm) LM81 www.national.com 24

Functional Description(Continued)

13.0 REGISTERS AND RAM

13.1 Address Register

The main register is the ADDRESS Register. The bit designations are as follows: Bit Name Read/ Write

Description

Write Address of RAM and Registers. See the tables below for detail. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address Pointer (Power On default 00h) A7 A6 A5 A4 A3 A2 A1 A0

13.2 Address Pointer Index (A7–A0)

Registers and RAM A6–A0 in Hex Power On Value of Registers: Notes <7:0> in Binary Configuration Register 40h 0000 1000 Interrupt Status Register 1 41h 0000 0000 Interrupt Status Register 2 42h 0000 0000 Interrupt Mask Register 1 43h 0000 0000 Interrupt Mask Register 2 44h 0000 0000 CI Clear Register 46h 0000 0000 VID/Fan Divisor Register 47h <7:4> = 0101; <3:0> = VID3–VID0 Serial Bus Address Register 48h <7:2> =0010 11;<1:0> =(A1)(A0) VID4 Register 49h <7:1> =1000 000; <0>=VID4 Temperature Configuration Register 4Bh 0000 0001 Extended Mode Register 1 4Ch 0100 0100 Extended Mode Register 2 4Dh 0000 0000 Value RAM 19h–3Dh Address 19h default=1111 1111 Company ID 3Eh 0000 0001 This default designates National Semiconductor. Stepping 3Fh 0000 0011 Revisions of this device will start with 1 and increment by one. LM81 www.national.com25

Functional Description(Continued)

13.3 Configuration Register — Address 40h

Power on default –<7:0> = 00001000 binary Bit Name Read/ Write 0 Start Read/Write A one enables startup of monitoring operations, a zero puts the part in standby mode. Note:The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike “INT_Clear” bit. At start up, limit checking functions and scanning begin. Note, all limits should be set in the Value RAM before setting this bit HIGH.

1 INT Enable

Read/Write A one enables the INT Interrupt output.

2 Reserved Read/Write

3 INT_Clear Read/Write A one disables the INT output without affecting the contents of Interrupt Status

Registers. The device will stop monitoring. It will resume upon clearing of this bit. 4 RESET Read/Write A one outputs at least a 20 ms active low reset signal at RESET. This bit is cleared once the pulse has gone inactive.

5 Reserved Read/Write

6 CI_Clear Read/Write A one outputs a minimum 20 ms active low pulse on the CI pin. The register bit self clears after the pulse has been output. This bit is mirrored in the CI Clear Register bit 7 INITIALIZATION Read/Write A one restores power on default value to the Configuration Register, Interrupt Status Registers, Interrupt Mask Registers, CI Clear Register, VID/Fan Divisor Register, VID4, Temperature Configuration Register, and the Extended Mode Registers. This bit clears itself since the power on default is zero. LM81 www.national.com 26

Functional Description(Continued)

13.4 Interrupt Status Register 1 — Address 41h

Power on default –<7:0> = 0000 0000 binary Bit Name Read/Write Description 0 +2.5Vin Read Only A one indicates a High or Low limit has been exceeded. 1 Vccp1 Read Only A one indicates a High or Low limit has been exceeded. 2 +3.3Vin Read Only A one indicates a High or Low limit has been exceeded. 3 +5Vin Read Only A one indicates a High or Low limit has been exceeded.

4 Temperature Read Only A one indicates a HIGH or HIHYST temperature error, see

SECTION 8.2.

5 Reserved Read Only

6 FAN1 Read Only A one indicates the fan count limit has been exceeded. 7 FAN2 Read Only A one indicates the fan count limit has been exceeded.

13.5 Interrupt Status Register 2 — Address 42h

Power on default – <7:0> = 0000 0000 binary Bit Name Read/Write Description 0 +12Vin Read Only A one indicates a High or Low limit has been exceeded. 1 Vccp2 Read Only A one indicates a High or Low limit has been exceeded.

2 Reserved Read Only

3 Reserved Read Only

4 CI Read Only A one indicates CI (Chassis Intrusion) has gone high.

6 Reserved Read Only

7 TLOW Read Only A one indicates LOW temperature error in EXTENDED MODE ONLY , see

SECTION 8.2.

13.6 Interrupt Mask Register 1 — Address 43h

Power on default –<7:0> = 0000 0000 binary Bit Name Read/ Write 0 +2.5Vin Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 1 Vccp1 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 2 +3.3Vin Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 3 +5Vin Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 4 Temperature Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 6 FAN1 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 7 FAN2 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. LM81 www.national.com27

Functional Description(Continued)

13.7 Interrupt Mask Register 2 — Address 44h

Power on default –<7:0> = 0000 0000 binary Bit Name Read/ Write 0 +12Vin Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 1 Vccp2 Read/Write A one disables the corresponding interrupt status bit for INT interrupt.

3 Reserved Read/Write

4 Chassis Intrusion Read/Write A one disables the corresponding interrupt status bit for INT interrupt.

6 Reserved Read/Write

7 RESET Enable

Read/Write <7> = 1 in INT Mask Register 2 enables the RESET in the Configuration Register.

13.8 Reserved Register — Address 45h

Power on default –<7:0> = 00h. Read/Write for backwards compatibility.

13.9 CI Clear Register — Address 46h

Power on default –<7:0> = 0000 0000 binary Bit Name Read/ Write 7 CI Clear Read/Write A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The register bit self clears after the pulse has been output. This bit is mirrored in Configuration Register bit 6. LM81 www.national.com 28

Functional Description(Continued)

13.10 VID/Fan Divisor Register — Address 47h

Power on default –<7:4> is 0101, and<3:0>is mapped to VID<3:0> Bit Name Read/Write Description 0-3 VID <3:0> Read Only The VID <3:0> inputs from the Pentium/PRO power supplies that indicate the 4-5 FAN1 RPM Control Read/Write FAN1 Speed Control. <5:4> = 00 - divide by 1; <5:4> = 01 - divide by 2; <5:4> = 10 - divide by 4; <5:4> = 11 - divide by 8. 6-7 FAN2 RPM Control Read/Write FAN2 Speed Control. <7:6> = 00 - divide by 1; <7:6> = 01 - divide by 2; <7:6> = 10 - divide by 4; <7:6> = 11 - divide by 8.

13.11 Serial Bus Address Register — Address 48h

Power on default – Serial Bus address<6:0> = 010 11(A1)(A0) and<7> = 0 binary Bit Name Read/Write Description 0-1 Serial Bus Address Read Only Serial Bus address <1:0> =A 1A 0 2-6 Serial Bus Address Read/Write Serial Bus address <6:2> = 010 11

7 Reserved Read/Write

13.12 VID4 Register — Address 49h

Power on default –<7:1> = 100 000,<0> = VID4. Bit Name Read/Write Description

0 VID4 Read Only VID4 input from Pentium/PRO power supply that indicate the operating voltage of

13.13 Temperature Configuration Register — Address 4Bh

Power on default –<7:0> = 0000 0001 binary Bit Name Read/Write Description 0-1 Temperature Interrupt Mode Select Bits Read/Write The state of these bits select the interrupt mode for INT as described below. <1:0> =0 0o r<1:0> = 11: Repetitive Interrupt Mode <1:0> = 01: One-Time Interrupt Mode <1:0> = 10: Comparator Mode 2-6 Reserved Read/Write

7 Temperature

Read Only For 8-bit plus sign temperature resolution:<7> = LSB ( 0.5˚C) LM81 www.national.com29

Functional Description(Continued)

13.14 Extended Mode Register 1 — Address 4Ch

Power on default –<7:0> = 0100 0100 binary Bit Name Read/Write Description

0 Extended Mode

Read/Write A one enables the Extended Interrupt Modes, the T_CRIT_A output and all the functions listed in the Extended Mode Registers. Bit 7 of the Interrupt Status register will be activated to reflect the interrupt status of the LOW limit comparison result.

1 LOW Limit Mask

Read/Write A mask bit for the LOW limit Interrupt. A one disables the interrupt from propagating to the INT pin. 2-3 T_CRIT_A Interrupt Mode Select Read/Write The state of these bits select the interrupt mode for T_CRIT_A as described below. <3:2> =0 0o r<3:2> = 11: Repetitive Interrupt Mode <3:2> = 01: One-Time Interrupt Mode <3:2> = 10: Comparator Mode

4 T_CRIT_A

Read/Write A one enables the T_CRIT_A pin.

5 T_CRIT_A

Read/Write A one sets the T_CRIT_A pin active HIGH. A zero sets the T_CRIT_A pin active LOW.

6 T_CRIT_A Mask

Read/Write A one prevents the T_CRIT_A interrupt from propagating to the INT output pin.

7 T_CRIT_A Status

Read A one indicates that a T_CRIT_A interrupt has occurred.

13.15 Extended Mode Register 2 — Address 4Dh

Power on default –<7:0> = 0000 0000 binary Bit Name Read/Write Description 0-2 Hysteresis Offset Value Read/Write T HYST value. 3 12-bit Temperature Resolution Enable Read/Write A one sets the temperature resolution to 12 bits. 4-7 12-bit Temperature Data Read Only 12-bit temperature data least significant bits. Bit 7 mirrors bit 7 in the temperature configuration register (4Bh) and has a weight of 0.5˚C; bits 6-4 have a weight of 0.25, 0.125, and 0.0625˚C, respectively. LM81 www.national.com 30

Functional Description(Continued)

13.16 Value RAM — Address 15h–3Fh

Address A6–A0 Description 15h Manufacturers Test Register 19h DAC data register; power on default <7:0>=1111 1111 binary 20h +2.5Vin reading 21h Vccp1 reading 22h +3.3Vin reading 23h +5Vin reading 24h +12Vin reading 25h Vccp2 reading 26h Reserved reading 27h Temperature reading (8 MSBs) 28h FAN1 reading Note:This location stores the number of counts of the internal clock per revolution. 29h FAN2 reading Note:This location stores the number of counts of the internal clock per revolution. 2Ah Reserved 2Bh +2.5Vin High Limit 2Ch +2.5Vin Low Limit 2Dh Vccp1 High Limit 2Eh Vccp1 Low Limit 2Fh +3.3Vin High Limit 30h +3.3Vin Low Limit 31h +5Vin High Limit 32h +5Vin Low Limit 33h +12Vin High Limit 34h +12Vin Low Limit 35h Vccp2 High Limit 36h Vccp2 Low Limit 37h T_CRIT Limit (Extended Mode) 38h LOW Limit (Extended Mode) 39h HIGH Temperature Limit 3Ah HIHYST Temperature Limit 3Bh FAN1 Fan Count Limit Note:It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Ch FAN2 Fan Count Limit Note:It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Dh Reserved 3Eh Company Identification. The number in this register identifies National Semiconductor (0000 0001) 3Fh Stepping Register LM81 revision number (0000 0011) Note:Setting all ones to the high limits for voltages and fans (01111111binary for temperature) means interrupts willnever be generated except the case when voltages go below the low limits. For voltage input high limits, the device is doing a greater than comparison. For low limits, however, it is doing a less than or equal to comparison. LM81 www.national.com31

FIGURE 19. In this PC application the LM81 monitors temperature, fan speed for 2 fans, and 6 power supply voltages. It also monitors an optical chassis intrusion detector. The LM81 provides a DAC output that can be used to control fan speed.

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