LM80CIMT-5

LM80_01 NSC | Alldatasheet

Document overview

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Technical content

Features

n 7 positive voltage inputs n 2 programmable fan speed monitoring inputs n 10 mV LSB and 2.56V input range accepts outputs from linear temperature sensors such as the LM50 n Chassis Intrusion Detector input n WATCHDOG comparison of all monitored values n Separate input to show status in Interrupt Status Register of additional external temperature sensors such as the LM56 or LM75 n I 2C Serial Bus interface compatibility n Shutdown mode to minimize power consumption n Programmable RST_OUT/OS pin: RST_OUT provides a Reset output; OS provides an Interrupt Output activated by an Overtemperature Shutdown event Key Specifications j Voltage monitoring Error ±1% (max) j Temperature Error −25˚C to +125˚C ± 3˚C (max) j Supply Voltage Range 2.8V to 5.75V j Supply Current Operating: 0.2 mA typ Shutdown: 15 µA typ j ADC Resolution 8 Bits j Temperature Resolution 0.5˚C

Applications

n System Thermal and Hardware Monitoring for Servers and PCs n Office Electronics n Electronic Test Equipment and Instrumentation Typical Application I2C ® is a registered trademark of the Philips Corporation. DS100040-1 # Indicates Active Low (“Not”) June 2001 LM80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor © 2001 National Semiconductor Corporation DS100040 www.national.com

Ordering Information

−25˚C ≤ TA ≤ +125˚C Specified Power Supply Voltage Order Number Device Marking LM80CIMT-3 1 LM80CIMTX-3 2 LM80CIMT-3 MTC24B 3.3V LM80CIMT-5 1 LM80CIMTX-5 2 LM80CIMT-5 MTC24B 5.0V Note:1-Rail transport media, 62 parts per rail 2-Tape and reel transport media, 3400 parts per reel Connection Diagram Block Diagram Pin Descriptions Pin Name(s) Pin Number Number of Pins Type Description INT_IN 1 1 Digital Input This is an active low input that propagates the INT_IN signal to the INT output of the LM80 via Interrupt Mask Register 1 Bit 7 and INT enable Bit 1 of the Configuration Register. SDA 2 1 Digital I/O Serial Bus bidirectional Data. Open-drain output. SCL 3 1 Digital Input Serial Bus Clock. DS100040-2 DS100040-3 LM80 www.national.com 2

Pin Descriptions(Continued) Pin Name(s) Pin Number Number of Pins Type Description FAN1-FAN2 4-5 2 Digital Inputs 0 to V + fan tachometer inputs. BTI 6 1 Digital Input Board Temperature Interrupt driven by O.S. outputs of additional temperature sensors such as LM75. Provides internal pull-up of 10 kΩ . CI (Chassis Intrusion) 7 1 Digital I/O An active high input from an external circuit which latches a Chassis Intrusion event. This line can go high without any clamping action regardless of the powered state of the LM80. The LM80 provides an internal open drain on this line, controlled by Bit 5 of the Configuration Register, to provide a minimum 10 ms reset of this line. GND 8 1 GROUND Internally connected to all of the digital circuitry. V + (+2.8V to +5.75V) 9 1 POWER +3.3V or +5V V + power. Bypass with the parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors. INT 10 1 Digital Output Non-Maskable Interrupt (open source)/Interrupt Request (open drain). The mode is selected with Bit 5 of the Configuration Register and the output is enabled when Bit 1 of the Configuration Register is set to 1. The default state is disabled. GPO (Power Switch Bypass) 11 1 Digital Output An active low open drain output intended to drive an external P-channel power MOSFET for software power control. NTEST_IN/ RESET_IN 12 1 Digital Input An active-low input that enables NAND Tree board-level connectivity testing. Refer to Section 10.0 on NAND Tree testing. Whenever NAND Tree connectivity is enabled the LM80 is also reset to its power on state. RST_OUT/OS 13 1 Digital Output Master Reset, 5 mA driver (open drain), active low output with a 10 ms minimum pulse width. Available when enabled via Bit 4 in Configuration Register and Bit 7 of the Fan Divisor/RST_OUT/OS Register. Bit 6 of the Fan Divisor/RST_OUT/OS Register enables this output as an active low Overtemperature Shutdown (OS). GNDA 14 1 GROUND Internally connected to all analog circuitry. The ground reference for all analog inputs. This pin needs to be taken to a low noise analog ground plane for optimum performance. IN6-IN0 15-21 7 Analog Inputs 0V to 2.56V full scale range Analog Inputs. A0/NTEST_OUT 22 1 Digital I/O The lowest order bit of the Serial Bus Address. This pin functions as an output when doing a NAND Tree test. A1-A2 23-24 2 Digital Inputs The two highest order bits of the Serial Bus Address. TOTAL PINS 24 LM80 www.national.com3

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (V +) 6.5V Voltage on Any Input or Output Pin −0.3V to (V++0.3V) Ground Difference (GND - GNDA) ±300 mV Input Current at any Pin (Note 3) ±5m A Package Input Current (Note 3) ±20 mA Maximum Junction Temperature (TJ max) 150˚C ESD Susceptibility(Note 5) Human Body Model 2000V Machine Model 125V Soldering Information Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 235˚C Storage Temperature −65˚C to +150˚C Operating Ratings(Notes 1, 2) Operating Temperature Range T MIN ≤ TA ≤ TMAX LM80CIMT-3, LM80CIMT-5 −25˚C ≤ TA ≤ +125˚C Specified Temperature Range T MIN ≤ TA ≤ TMAX LM80CIMT-3, LM80CIMT-5 −25˚C ≤ TA ≤ +125˚C Junction to Ambient Thermal Resistance (θJA(Note 4) ) Supply Voltage (V+) +2.8V to +5.75V Ground Difference (|GND − GNDA|) ≤ 100 mV VIN Voltage Range: −0.05V to V + + 0.05V The following specifications apply for +2.8 VDC ≤V+ ≤ +3.8 VDC for LM80CIMT-3, +4.25 VDC ≤V+ ≤ +5.75 VDC for LM80CIMT-5, IN0-IN6 RS =2 5Ω , unless otherwise specified.Boldface limits apply for TA =T J =T MIN to TMAX ;all other limits TA =T J = 25˚C.(Note 7) Symbol Parameter Conditions Typical Limits Units (Note 8) (Note 9) (Limits) POWER SUPPLY CHARACTERISTICS I + Supply Current Interface Inactive and V+= 5.75V 0.2 2.0 mA (max) Interface Inactive and V+= 3.8V 0.18 1.5 mA (max) Shutdown Mode 15 µA TEMPERATURE-to-DIGITAL CONVERTER CHARACTERISTICS Temperature Error −25˚C ≤ TA ≤ +125˚C ±3 ˚C (max) Resolution 0.5 ˚C (min) ANALOG-to-DIGITAL CONVERTER CHARACTERISTICS Resolution (8 bits with full-scale at 2.56V) 10 mV TUE Total Unadjusted Error (Note 10) ±1 % (max) DNL Differential Non-Linearity ±1 LSB (max) PSS Power Supply Sensitivity ±1 %/V tC Total Monitoring Cycle Time (Note 11) 9-bit Temp resolution 12-bit Temp resolution 1.0 1.5 sec (max) sec (max) MULTIPLEXER/ADC INPUT CHARACTERISTICS On Resistance 0.5 10 kΩ (max) Input Current (On Channel Leakage Current) ±1µ A Off Channel Leakage Current ±1µ A LM80 www.national.com 4

The following specifications apply for +2.8 VDC ≤V+ ≤ +3.8 VDC for LM80CIMT-3, +4.25 VDC ≤V+ ≤ +5.75 VDC for LM80CIMT-5, IN0-IN6 RS =2 5Ω , unless otherwise specified.Boldface limits apply for TA =T J =T MIN to TMAX ;all other limits TA =T J = 25˚C.(Note 7) Symbol Parameter Conditions Typical Limits Units (Note 8) (Note 9) (Limits) FAN RPM-to-DIGITAL CONVERTER Fan RPM Error +25˚C ≤ TA ≤ +75˚C ±10 % (max) Full-scale Count 255 (max) FAN1 and FAN2 Nominal Input RPM (See Section 6.0) Divisor = 1, Fan Count = 153 (Note 12)

8800 RPM

Divisor = 2, Fan Count = 153 (Note 12)

4400 RPM

Divisor = 3, Fan Count = 153 (Note 12)

2200 RPM

Divisor = 4, Fan Count = 153 (Note 12)

1100 RPM

Internal Clock Frequency +25˚C ≤ TA ≤ +75˚C 22.5 20.2 kHz (min) 24.8 kHz (max) −10˚C ≤ TA ≤ +100˚C 22.5 19.1 kHz (min) 25.9 kHz (max) −25˚C ≤ TA ≤ +125˚C 22.5 18 kHz (min) 27 kHz (max) DIGITAL OUTPUTS: A0/NTEST_OUT, INT VOUT(1) Logical “1” Output Voltage I OUT = +5.0 mA at V+ = +4.25V, IOUT = +3.0 mA at V+ = +2.8V

2.4 V (min)

VOUT(0) Logical “0” Output Voltage I OUT = −5.0 mA at V+ = +5.75V, IOUT = −3.0 mA at V+ = +3.8V

0.4 V (max)

OPEN DRAIN OUTPUTS: GPO, RST_OUT/OS, CI VOUT(0) Logical “0” Output Voltage I OUT =− 5.0 mA at V+ = +5.75V, IOUT = −3.0 mA at V+ = +3.8V

0.4 V (min)

IOH High Level Output Current V OUT =V + 0.1 100 µA (max) RST_OUT/OS, CI 30 10 ms (min) Pulse Width OPEN DRAIN SERIAL BUS OUTPUT: SDA V OUT(0) Logical “0” Output Voltage I OUT = −3.0 mA at V = +5.75V, IOUT = −3.0 mA at V+ = +3.8V IOH High Level Output Current V OUT =V + 0.1 100 µA (max) DIGITAL INPUTS: A0/NTEST_Out, A1-A2, BTI, CI (Chassis Intrusion), INT_IN, and NTEST_IN/Reset_IN VIN(1) Logical “1” Input Voltage 2.0 V (min) VIN(0) Logical “0” Input Voltage 0.8 V (max) SERIAL BUS INPUTS (SCL, SDA) and FAN TACH PULSE INPUTS (FAN1, FAN2) V IN(1) Logical “1” Input Voltage 0 . 7xV+ V (min) VIN(0) Logical “0” Input Voltage 0 . 3xV+ V (max) ALL DIGITAL INPUTS Except for BTI IIN(1) Logical “1” Input Current V IN =V + −0.005 −1 µA (min) IIN(0) Logical “0” Input Current V IN =0V DC 0.005 1 µA (max) C IN Digital Input Capacitance 20 pF LM80 www.national.com5

FIGURE 1. Serial Bus Timing Diagram

Note 3:When the input voltage (VIN) at any pin exceeds the power supplies (VIN< (GND or GNDA) or VIN>V +), the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four. allowable power dissipation at any temperature is PD =( TJmax−T A)/θJA. Note 8: Typicals are at TJ=TA =25˚C and represent most likely parametric norm. Note 9:Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10:TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC. 800 ms typical and 900 ms maximum. Fan tachometer readings take 20 ms typical, at 4400 rpm, and 200 ms max. Note 12:The total fan count is based on 2 pulses per revolution of the fan tachometer output. Note 13:Timing specifications are tested at the Serial Bus Input logic levels, VIN(0)=0 . 3xV+ for a falling edge and VIN(1)= 0 . 7xV+ for a rising edge. An x indicates that the diode exists. FIGURE 2. ESD Protection Input Structure

1.0 GENERAL DESCRIPTION

fan control and fan monitoring for personal computers. lutions of 0.5˚C LSB or 0.0625˚C LSB, respectively. Figure 4. These include: status of each WATCHDOG limit or Interrupt event. both hardware Interrupt outputs. 6-7 control the function of the RST_OUT/OS output. of the temperature reading for a 12-bit resolution. bytes in the upper locations. latches when the case is removed from the computer. FIGURE 3. Digital Output Load Test Circuitry

2.0 INTERFACE

FIGURE 4. LM80 Register Structure

2.1 Internal Registers of the LM80

TABLE 1. The internal registers and their corresponding internal LM80 address is as follows:

4400 RPM)

2.2 Serial Bus Interface

1. If the Internal Address Register is known to be at the
2. If the Internal Address Register value is unknown, write

data byte read from the LM80. the pins defined by the same names. FIGURE 5. Serial Bus Timing

3.0 USING THE LM80

3.1 Power On

Table 1. Registers whose power on DOG limits into the Value RAM.

3.2 Resets

Reset and will be indeterminate immediately after power on. automatically clears after being set. NTEST_IN/Reset_IN pin low for at least 50 ns.

3.3 Using the Configuration Register

provides the Reset function described inSection 3.2. hardwire output when this bit is taken high. pin is open source or open drain. the RST_OUT/OS output (when this pin is in the RST mode). activating an external power control MOSFET.

3.4 Starting Conversions

3.4 STARTING CONVERSION The monitoring function

3.5 Reading Conversion Results

The conversion results are available in the Value RAM. least 2.0 seconds between reading groups of values.

1. Start the LM80 monitoring process

4.0 ANALOG INPUTS

analog input has no detrimental effect on other channels. inputs to limit the input current.

5.0 LAYOUT AND GROUNDING

be located physically as close as possible to the LM80. be located as close as possible to the LM80. FIGURE 6. Input Examples. Resistor values shown in table provide approximately 1.9V at the analog inputs.

6.0 FAN INPUTS

Figure 7. R2 is selected so zener diode to clamp the input level. resistors connected in series with the fan inputs. the Fan Divisor/RST_OUT/OS Register. pulse per revolution with a nominal RPM of 4400.

Counts are based on 2 pulses per revolution tachometer outputs. FIGURE 7. Alternatives for Fan Inputs

7.0 TEMPERATURE MEASUREMENT SYSTEM

and Overtemperature setpoints, and Hysteresis values.

7.1 Temperature Data Format

FIGURE 8. 9-bit Temperature-to-Digital Transfer FIGURE 9. 12-bit Temperature-to-Digital Transfer

Functional Description(Continued) By default Temperature Register data is represented by a 9-bit two’s complement digital word with the LSB having a resolution of 0.5˚C: Temperature Digital Output Binary Hex +125˚C 0 1111 1010 0 FAh +25˚C 0 0011 0010 0 32h +1.5˚C 0 0000 0011 0 03h +0˚C 0 0000 0000 0 00h −0.5˚C 1 1111 1111 1 FFh −25˚C 1 1100 1110 1 CEh −55˚C 1 1001 0010 1 92h Temperature Register data can also be represented by a 12-bit two’s complement digital word with a LSB of 0.0625˚C: Temperature Digital Output Binary Hex +125˚C 0111 1100 0000 7 D0h +25˚C 0001 1001 0000 1 90h +1.0˚C 0000 0001 0000 0 10h +0.0625˚C 0000 0000 0001 0 01h 0˚C 0000 0000 0000 00h −0.0625˚C 1111 1111 1111 F FFh −1.0˚C 1111 1111 0000 F F0h −25˚C 1110 0111 0000 E 70h −55˚C 1100 1001 0000 C 90h The 8 MSBs of the Temperature reading can be found at Value RAM address 28 h. The remainder of the Temperature reading can be found in the OS Configuration/Temperature Resolution Register bits 7-4. In 9-bit format bit 7 is the only valid bit.

7.2 Temperature Interrupts

There are four Value RAM WATCHDOG limits for the Tem- perature reading that affect the INT and OS outputs of the LM80. They are: Hot Temperature Limit, Hot Temperature Hysteresis Limit, OS Limit, OS Hysteresis Limit. There are three interrupt modes of operation: “One-Time Interrupt” mode, “Default Interrupt” mode, and “Comparator Mode”. The OS output of the LM80 can be programmed for “One-Time Interrupt” mode and “Comparator” mode. INT can be programmed for “Default Interrupt” mode and “One-Time” Interrupt. “Default Interrupt mode”operates in the following way: Exceeding T hot causes an Interrupt that will remain active indefinitely until reset by reading Interrupt Status Register 1 or cleared by the INT_Clear bit in the Configuration register. Once an Interrupt event has occurred by crossing T hot, then reset, an Interrupt will occur again once the next temperature conversion has completed. The interrupts will continue to occur in this manner until the temperature goes below T hot hyst, at which time the Interrupt output will automatically clear. “One-Time Interrupt” modeoperates in the following way: Exceeding Thot causes an Interrupt that will remain active indefinitely until reset by reading Interrupt Status Register 1 or cleared by the INT_Clear bit in the Configuration register. Once an Interrupt event has occurred by crossing T hot, then reset, an Interrupt will not occur again until the temperature goes below T hot hyst. “Comparator” mode operates in the following way: Ex- ceeding Tos causes the OS output to go Low (default). OS will remain Low until the temperature goes below Tos. Once the temperature goes below Tos, OS will go High. LM80 www.national.com17

Functional Description(Continued) DS100040-17 Temperature Interrupt Response Diagram. This diagram does not reflect all the possible variations in the operation of the OS and INT outputs nor the OS and Hot Temp bits. The interrupt outputs are cleared by reading the appropriate Interrupt Status Register. LM80 www.national.com 18

8.0 THE LM80 INTERRUPT STRUCTURE

8.1 INTERRUPT INPUTS

External Interrupts can come from the following sources.

• BTI - This is an active low Interrupt intended to come from the O.S. output of LM75 temperature sensors. The LM75 O.S. output goes active when its temperature ex- ceeds a programmed threshold. Up to 8 LM75’s can be connected to a single Serial Bus bus with their O.S. output’s wire or’d to the BTI input of the LM80. If the temperature of any LM75 exceeds its programmed limit, it drives BTI low. This generates an Interrupt to notify the host of a possible overtemperature condition. Provides an internal pull-up of 10 kΩ .
• CI (Chassis Intrusion) -This is an active high interrupt from any type of device that detects and captures chassis intrusion violations. This could be accomplished me- chanically, optically, or electrically, and circuitry external to the LM80 is expected to latch the event. The design of the LM80 allows this input to go high even with no power applied to the LM80, and no clamping or other interfer- ence with the line will occur. This line can also be pulled low for at least 10 ms by the LM80 to reset a typical Chassis Intrusion circuit. Accomplish this reset by setting Bit 5 of Configuration Register high. The bit in the Reg- ister is self-clearing. DS100040-18

FIGURE 10. Interrupt Structure

Functional Description(Continued)

• INT_IN - This active low Interrupt merely provides a way to chain the INT (Interrupt) from other devices through the LM80 to the processor.

8.2 INTERRUPT OUTPUTS

All Interrupts are indicated in the two Interrupt Status Reg- isters. INT output has two mask registers, and individual masks for each Interrupt. As described in Section 3.3, this hardware Interrupt line can also be enabled/disabled in the Configura- tion Register. The Configuration Register is also used to set the mode of the INT Interrupt line. OS is dedicated to the Temperature reading WATCHDOG. In the “Fan Divisor/RST_OUT/OS Register” the OS enable bit (Bit-6), must be set high and the RST enable bit (Bit -7) must be set low to enable the OS function on the RST_OUT/OS pin. OS pin has two modes of operation: “One-Time Inter- rupt” and “Comparator”. “One-Time Interrupt” mode is se- lected by taking bit-2 of the “OS Configuration/Temperature Resolution Register” high. If bit-2 is taken low “Comparator” mode is selected. Unlike the OS pin, the OS bit in “Interrupt Status Register 2” functions in “Default Interrupt” and “One-Time Interrupt” modes. The OS bit can be masked to INT pin by taking bit-5 in the “Interrupt Mask Register 2” low. A description of “Comparator”, “Default Interrupt” and “One-Time Interrupt” modes can be found in Section 7.1.

8.3 INTERRUPT CLEARING

Reading an Interrupt Status Register will output the contents of the Register, and reset the Register. A subsequent read done before the analog “round-robin” monitoring loop is complete will indicate a cleared Register. Allow at least 1.5 seconds to allow all Registers to be updated between reads. In summary, the Interrupt Status Register clears upon being read, and requires at least 1.5 seconds to be updated. When the Interrupt Status Register clears, the hardwire interrupt line will also clear until the Registers are updated by the monitoring loop. The hardware Interrupt lines are cleared with the INT_Clear bit, which is Bit 3 of the Configuration Register, without affecting the contents of the Interrupt (INT) Status Registers. When this bit is high, the LM80 monitoring loop will stop. It will resume when the bit is low.

9.0 RST and GPO OUTPUTS

In PC applications the open drain GPO provides a gate drive signal to an external P-channel MOSFET power switch. This external MOSFET then would keep power turned on regard- less of the state of front panel power switches when software power control is used. In any given application this signal is not limited to the function described by its label. For ex- ample, since the LM80 incorporates temperature sensing, the GPO output could also be utilized to control power to a cooling fan. Take GPO active low by setting Bit 6 in the Configuration Register low. RST is intended to provide a master reset to devices con- nected to this line. The RST_OUT/OS Control bit in Fan Divisor/RST_OUT/OS Register, Bit 7, must be set high to enable this function. Setting Bit 4 in the Configuration Reg- ister high outputs a least 10 ms low on this line, at the end of which Bit 4 in the Configuration Register automatically clears. Again, the label for this pin is only its suggested use. In applications where the RST capability is not needed it can be used for any type of digital control that requires a 10 ms active low open drain output.

10.0 NAND TREE TESTS

A NAND tree is provided in the LM80 for Automated Test Equipment (ATE) board level connectivity testing. If the user applies a logic zero to the NTEST_IN/Reset_IN input pin, the device will be in the NAND tree test mode. A0/NTEST_OUT will become the NAND tree output pin. To perform a NAND tree test all pins included in the NAND tree should be driven to 1. Beginning with IN0 and working clockwise around the chip, each pin can be toggled and a resulting toggle can be observed on A0/NTEST_OUT. The following pins are ex- cluded from the NAND tree test: GNDA (analog ground), GND (digital ground), V + (power supply), A0/NTEST_OUT, NTEST_IN/Reset_IN and RST_OUT/OS. Allow for a typical propagation delay of 500 ns. LM80 www.national.com 20

Functional Description(Continued)

11.0 FAN MANUFACTURERS

Manufacturers of cooling fans with tachometer outputs are listed below: NMB Tech 9730 Independence Ave. Chatsworth, California 91311 818 341-3355 818 341-8207 Model Num- ber Frame Size Airflow CFM 2408NL 2.36 in sq. X 0.79 in 9-16 (60 mm sq. X 20 mm) 2410ML 2.36 in sq. X 0.98 in 14-25 (60 mm sq. X 25 mm) 3108NL 3.15 in sq. X 0.79 in 25-42 (80 mm sq. X 20 mm) 3110KL 3.15 in sq. X 0.98 in 25-40 (80 mm sq. X 25 mm) Mechatronics Inc. P.O. Box 20 Mercer Island, WA 98040 800 453-45698 Various sizes available with tach output option. Sanyo Denki America, Inc. 468 Amapola Ave. Torrance, CA 90501 310 783-5400 Model Number Frame Size Airflow CFM 109P06XXY601 2.36 in sq. X 0.79 in 11-15 (60 mm sq. X 20 mm) 109R06XXY401 2.36 in sq. X 0.98 in 13-28 (60 mm sq. X 25 mm) 109P08XXY601 3.15 in sq. X 0.79 in 23-30 (80 mm sq. X 20 mm) 109R08XXY401 3.15 in sq. X 0.98 in 21-42 (80 mm sq. X 25 mm) LM80 www.national.com21

Functional Description(Continued)

12.0 REGISTERS AND RAM

12.1 Address Register

The main register is the ADDRESS Register. The bit designations are as follows: Bit Name Read/ Write

Description

Read/Write Address of RAM and Registers. See the tables below for detail. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address Pointer (Power On default 00h) A7 A6 A5 A4 A3 A2 A1 A0

12.2 Address Pointer Index (A7–A0)

Registers and RAM A6–A0 in Hex Power On Value of Registers: <7:0> in Binary Configuration Register 00h 0000 1000 Interrupt Status Register 1 01h 0000 0000 Interrupt Status Register 2 02h 0000 0000 Interrupt Mask Register 1 03h 0000 0000 Interrupt Mask Register 2 04h 0000 0000 Fan Divisor/RST_OUT/OS 05h 0001 0100 OS Configuration/Temperature Resolution Register 06h 0000 0001 Value RAM 20h–3Fh LM80 www.national.com 22

Functional Description(Continued)

12.3 Configuration Register — Address 00h

Power on default<7:0> = 00001000 binary Bit Name Read/ Write 0 Start Read/Write A one enables startup of monitoring operations, a zero puts the part in standby mode. Note:The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike “INT_Clear” bit.At start up, limit checking functions and scanning begin. Note, all limits should be set in the Value RAM before setting this bit HIGH.

1 INT Enable

Read/Write A one enables the INT Interrupt output.

2 INT polarity

Read/Write A one selects an active high open source output while a zero selects an active low open drain output.

3 INT_Clear Read/Write A one disables the INT and RST_OUT/OS outputs without affecting the contents of

Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit.

4 RESET Read/Write A one outputs at least a 10 ms active low reset signal at RESET, if<7> = 1 and

<6> = 0 in the Fan Divisor/RST_OUT/OS Register. This bit is cleared once the pulse has gone inactive. 5 Chassis Clear Read/Write A one clears the CI (Chassis Intrusion) pin. This bit clears itself after the CI pins cleared. 6 GPO Read/Write A one in this bit drives a one on GPO (General Purpose Output) pin. 7 INITIALIZATION Read/Write A one restores power on default value to the Configuration Register, Interrupt Status Registers, Interrupt Mask Registers, Fan Divisor/RST_OUT/OSRegister, and the OS Configuration/Temperature Resolution Register. This bit clears itself since the power on default is zero. LM80 www.national.com23

Functional Description(Continued)

12.4 Interrupt Status Register 1 — Address 01h

Power on default<7:0> = 0000 0000 binary Bit Name Read/Write Description 0 IN0 Read Only A one indicates a High or Low limit has been exceeded. 1 IN1 Read Only A one indicates a High or Low limit has been exceeded. 2 IN2 Read Only A one indicates a High or Low limit has been exceeded. 3 IN3 Read Only A one indicates a High or Low limit has been exceeded. 4 IN4 Read Only A one indicates a High or Low limit has been exceeded. 5 IN5 Read Only A one indicates a High or Low limit has been exceeded. 6 IN6 Read Only A one indicates a High or Low limit has been exceeded.

7 INT_IN

Read Only A one indicates that a Low has been detected on the INT_IN.

12.5 Interrupt Status Register 2 — Address 02h

Power on default<7:0> = 0000 0000 binary Bit Name Read/Write Description 0 Hot Temperature Read Only A one indicates a High or Low limit has been exceeded. Only “One-Time Interrupt” and “Default Interrupt” modes are supported. The mode is set by bit-6 of the Interrupt Mask Register 2.

1 BTI

Read Only A one indicates that an interrupt has occurred from the Board Temperature Interrupt (BTI) input pin. BTI can be tied to the OS output of multiple LM75 chips. 2 FAN1 Read Only A one indicates that a fan count limit has been exceeded. 3 FAN2 Read Only A one indicates that a fan count limit has been exceeded.

4 CI (Chassis

Intrusion) Read Only A one indicates CI (Chassis Intrusion) has gone high.

5 OS bit

Read Only A one indicates a High or a Low OS Temperature limit has been exceed. Only “One-Time Interrupt” and “Default Interrupt” modes are supported (see Sections 7.2 and 8.2). The mode is set by bit-7 of the Interrupt Mask Register 2.

6 Reserved Read Only

7 Reserved Read Only

12.6 Interrupt Mask Register 1 — Address 03h

<7:0> = 0000 0000 binary Bit Name Read/ Write 0 IN0 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 1 IN1 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 2 IN2 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 3 IN3 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 4 IN4 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 5 IN5 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 6 IN6 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 7 INT_IN Read/Write A one disables the corresponding interrupt status bit for INT interrupt. LM80 www.national.com 24

Functional Description(Continued)

12.7 Interrupt Mask Register 2 — Address 04h

Power on default<7:0> = 0000 0000 binary Bit Name Read/ Write 0 Hot Temperature Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 1 BTI Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 2 FAN1 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 3 FAN2 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. Intrusion) Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 5 OS bit Read/Write A one disables the corresponding interrupt status bit for INT interrupt.

6 Hot Temperature

Read/Write A zero selects the default interrupt mode which gives the user an interrupt if the temperature goes above the hot limit. The interrupt will be cleared once the status register is read, but it will again be generated when the next conversion has completed. It will continue to do so until the temperature goes below the hysteresis limit. A one selects the one time interrupt mode which only gives the user one interrupt when it goes above the hot limit. The interrupt will be cleared once the status register is read. Another interrupt will not be generated until the temperature goes below the hysteresis limit. It will also be cleared if the status register is read. No more interrupts will be generated until the temperature goes above the hot limit again. The corresponding bit will be cleared in the status register every time it is read but may not set again when the next conversion is done. (See in Section 7.0)

7 OS bit Interrupt

Read/Write A zero selects the default interrupt mode which gives the user an interrupt if the temperature goes above the hot limit. The interrupt will be cleared once the status register is read, but it will again be generated when the next conversion has completed. It will continue to do so until the temperature goes below the hysteresis limit. A one selects the one time interrupt mode which only gives the user one interrupt when it goes above the hot limit. The interrupt will be cleared once the status register is read. Another interrupt will not be generated until the temperature goes below the hysteresis limit. It will also be cleared if the status register is read. No more interrupts will be generated until the temperature goes above the hot limit again. The corresponding bit will be cleared in the status register every time it is read but may not set again when the next conversion is done. (See Section in Section 7.0) LM80 www.national.com25

Functional Description(Continued)

12.8 Fan Divisor Register/RST_OUT/OS — Address 05h

Power on –<7:4> is 0101, and<3:0>is mapped to VID<3:0> Bit Name Read/Write Description

0 FAN1 Mode

Read/Write A one selects the level sensitive input mode while a zero selects Fan count mode for the FAN1 input pin.

1 FAN2 Mode

Read/Write A one selects the level sensitive input mode while a zero selects Fan count mode for the FAN2 input pin. 2-3 FAN1 RPM Control Read/Write FAN1 Speed Control. <3:2> = 00 - divide by 1; <3:2> = 01 - divide by 2; <3:2> = 10 - divide by 4; <3:2> = 11 - divide by 8. If level sensitive input is selected:>2< = 1 selects and active-low input (An interrupt will be generated if the FAN2 input is Low),>2< = 0 selects an active-high input (an interrupt will be generated if the FAN2 input is High). 4-5 FAN2 RPM Control Read/Write FAN2 Speed Control. <5:4> = 00 - divide by 1; <5:4> = 01 - divide by 2; <5:4> = 10 - divide by 4; <5:4> = 11 - divide by 8. If level sensitive input is selected:<2> = 1 selects and active-low input (An interrupt will be generated if the FAN2 input is Low),<2> = 0 selects an active-high input (an interrupt will be generated if the FAN2 input is High). 6 OS pin enable Read/Write A one enables OS mode on the RST_OUT/OS output pin, while Bit 7 of this register is set to zero. If bits 6 and 7 of this register are set to zero the RST_OUT/OS pin is disabled. 7 RST enable Read/Write A one sets the RST_OUT/OS pin in the RST mode. In the RST mode, bit 7 of the Fan Divisor/RST_OUT/OS Register has to be set to one. If bits 6 and 7 of this register are set to zero the RST_OUT/OS pin is disabled.

12.9 OS Configuration/Temperature Resolution Register — Address 06h

Power on default Serial Bus address<7:0> = 0000 0001 binary Bit Name Read/Write Description 0 OS status Read only Status of the OS.This bit mirrors the state of the RST_OUT/OS pin when in the OS mode. 1 OS Polarity Read/Write A zero selects OS to be active-low, while a one selects OS to be active high. OS is an open-drain output. 2 OS mode select Read/Write A one selects the one time interrupt mode for OS, while a zero selects comparator mode for OS. (See in Section 7.0)

3 Temperature

Read/Write A zero selects the default 8-bit plus sign resolution temperature conversions while a one selects 11-bit plus sign resolution temperature conversions. 8-bit plus sign conversions time is approximately 100 ms, while 11-bit plus sign conversion time is approximately 2 seconds. 4-7 Temp [3:0] Read/Write The lower nibble (4 LSBs) of the 11-bit plus sign temperature data. <4> = Temp [0] (nibble LSB, 0.0625˚C),<5> = Temp [1],<6> = Temp [2],<7> = Temp 3 (nibble MSB, 0.5˚C). For 8-bit plus sign temperature resolution,<7> = Temp [0] (LSB, 0.5˚C) while<4:6> are undefined. LM80 www.national.com 26

Functional Description(Continued)

12.10 Value RAM — Address 20h–3Fh

Address A7–A0 Description 20h IN0 reading 21h IN1 reading 22h IN2 reading 23h IN3 reading 24h IN4 reading 25h IN5 reading 26h IN6 reading 27h Temperature reading 28h FAN1 reading Note:This location stores the number of counts of the internal clock per revolution. 29h FAN2 reading Note:This location stores the number of counts of the internal clock per revolution. 2Ah IN0 High Limit 2Bh IN0 Low Limit 2Ch IN1 High Limit 2Dh IN1 Low Limit 2Eh IN2 High Limit 2Fh IN2 Low Limit 30h IN3 High Limit 31h IN3 Low Limit 32h IN4 High Limit 33h IN4 Low Limit 34h IN5 High Limit 35h IN5 Low Limit 36h IN6 High Limit 37h IN6 Low Limit 38h Hot Temperature Limit (High) 39h Hot Temperature Hysteresis Limit (Low) 3Ah OS Temperature Limit (High) 3Bh OS Temperature Hysteresis Limit (Low) 3Ch FAN1 Fan Count Limit Note:It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Dh FAN2 Fan Count Limit Note:It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Eh-3Fh Reserved Note:Setting all ones to the high limits for voltages and fans (01111111binary for temperature) means interrupts willnever be generated except the case when voltages go below the low limits. For voltage input high limits, the device is doing a greater than comparison. For low limits, however, it is doing a less than or equal to comparison. LM80 www.national.com27

FIGURE 11. In this PC application the LM80 monitors temperature, fan speed for 2 fans, and 7 power supply voltages. It also monitors an optical chassis intrusion detector.

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