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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 LM80SerialInterfaceACPI-CompatibleMicroprocessorSystemHardwareMonitor Check forSamples: LM80 1FEATURES KEY SPECIFICATIONS 2• Temperature Sensing • VoltageMonitoringError±1% (Max)

  • 7 PositiveVoltageInputs • Temperature Error(−25°C to+125°C) ±3°C (Max)• 2 Programmable Fan Speed MonitoringInputs
  • Supply VoltageRange 2.8to5.75V• 10 mV LSB and 2.56VInputRange Accepts Outputs From LinearTemperature Sensors • Supply Current:Operating0.2mA typ Such as theLM50 • Supply Current:Shutdown 15 µA typ
  • Chassis IntrusionDetectorInput • ADC Resolution8 Bits
  • WATCHDOG Comparison ofallMonitored • Temperature Resolution0.5ºC Values
  • SeparateInputtoShow StatusinInterrupt DESCRIPTION StatusRegisterofAdditionalExternal The LM80 provides 7 positivevoltage inputs, Temperature Sensors such as theLM56 or temperaturemeasurement, fan speed measurement, and hardware monitoringon an I2C interface.TheLM75 LM80 performs WATCHDOG comparisons of all• I2C SerialBus InterfaceCompatibility measured valuesand an open-draininterruptoutput• Shutdown Mode toMinimizePower becomes active when any values exceed Consumption programmed limits.A Chassis Intrusioninput is providedto monitorand resetan externalcircuit• Programmable RST_OUT/ OS pin:RST_OUT designedtolatcha chassisintrusionevent.Providesa Reset Output;OS Providesan InterruptOutput Activatedby an The LM80 is especiallysuitedto interfaceto both OvertemperatureShutdown Event linearand digitaltemperaturesensors.The 10 mV LSB and 2.56 voltinputrange isidealforaccepting APPLICATIONS inputsfrom a linearsensorsuch as the LM50. The BTI is used as an input from eitherdigitalor• System Thermal and Hardware Monitoringfor thermostatsensorssuch as LM75 and LM56.Serversand PCs The LM80 's 2.8V to5.75V supplyvoltagerange,low• OfficeElectronics supplycurrent,and I2C interfacemake itidealfora• ElectronicTestEquipment and wide range of applications.These includehardwareInstrumentation monitoringand protectionapplicationsin personal computers, electronictest equipment, and office electronics. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com TypicalApplication # IndicatesActiveLow (“Not”)

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 Connection Diagram Block Diagram Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS Pin Pin Number Type DescriptionName(s) Number ofPins INT_IN 1 1 DigitalInput Thisisan activelowinputthatpropagatestheINT_INsignaltotheINT outputoftheLM80 viaInterruptMask Register1 Bit7 and INT enableBit 1 oftheConfigurationRegister. SDA 2 1 DigitalI/O SerialBus bidirectionalData.Open-drainoutput. SCL 3 1 DigitalInput SerialBus Clock. FAN1-FAN2 4-5 2 DigitalInputs 0 toV+ fantachometerinputs. BTI 6 1 DigitalInput Board TemperatureInterruptdrivenby O.S.outputsofadditional temperaturesensorssuch as LM75. Providesinternalpull-upof10 kΩ. CI (Chassis 7 1 DigitalI/O An activehighinputfroman externalcircuitwhichlatchesa Chassis Intrusion) Intrusionevent.Thislinecan go highwithoutany clampingaction regardlessofthepowered stateoftheLM80. The LM80 providesan internalopen drainon thisline,controlledby Bit5 oftheConfiguration Register,toprovidea minimum 10 ms resetofthisline. GND 8 1 GROUND Internallyconnectedtoallofthedigitalcircuitry. V+ (+2.8Vto 9 1 POWER +3.3V or+5V V+ power.Bypass withtheparallelcombinationof10 μF +5.75V) (electrolyticortantalum)and 0.1μF (ceramic)bypasscapacitors. INT 10 1 DigitalOutput Non-MaskableInterrupt(opensource)/InterruptRequest(opendrain). The mode isselectedwithBit5 oftheConfigurationRegisterand the outputisenabledwhen Bit1 oftheConfigurationRegisterissetto1. The defaultstateisdisabled. GPO (Power Switch 11 1 DigitalOutput An activelowopen drainoutputintendedtodrivean externalP-channel Bypass) power MOSFET forsoftwarepower control. NTEST_IN/ 12 1 DigitalInput An active-lowinputthatenablesNAND Treeboard-levelconnectivity RESET_IN testing.RefertoNAND TREE TESTS on NAND Treetesting.Whenever NAND TreeconnectivityisenabledtheLM80 isalsoresettoitspower on state. RST_OUT/ OS 13 1 DigitalOutput MasterReset,5 mA driver(opendrain),activelowoutputwitha 10 ms minimum pulsewidth.Availablewhen enabledviaBit4 inConfiguration Registerand Bit7 oftheFan Divisor/RST_OUT/ OS Register.Bit6 ofthe Fan Divisor/RST_OUT/ OS Registerenablesthisoutputas an activelow OvertemperatureShutdown (OS). GNDA 14 1 GROUND Internallyconnectedtoallanalogcircuitry.The groundreferenceforall analoginputs.Thispinneeds tobe takentoa lownoiseanalogground planeforoptimum performance. IN6-IN0 15-21 7 AnalogInputs 0V to2.56VfullscalerangeAnalogInputs. A0/NTEST_OUT 22 1 DigitalI/O The lowestorderbitoftheSerialBus Address.Thispinfunctionsas an outputwhen doinga NAND Treetest. A1-A2 23-24 2 DigitalInputs The two highestorderbitsoftheSerialBus Address. TOTAL PINS 24 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 AbsoluteMaximum Ratings(1)(2) PositiveSupplyVoltage(V+) 6.5V Voltageon Any InputorOutputPin −0.3Vto(V++0.3V) Ground Difference(GND -GNDA) ±300 mV InputCurrentatany Pin(3) ±5 mA Package InputCurrent(3) ±20 mA Maximum JunctionTemperature(TJ max) 150°C ESD Susceptibility(4) Human Body Model 2000V Machine Model 125V SolderingInformation Infrared(15seconds) 235°C StorageTemperature −65°C to+150°C Forsolderingspecificationshttp://www.ti.com/lit/SNOA549 (1) Allvoltagesaremeasured withrespecttoGND, unlessotherwisespecified (2) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (3) When theinputvoltage(VIN)atany pinexceedsthepower supplies(VIN< (GND orGNDA) orVIN>V +),thecurrentatthatpinshouldbe limitedto5 mA. The 20 mA maximum package inputcurrentratinglimitsthenumber ofpinsthatcan safelyexceed thepower supplies withan inputcurrentof5 mA tofour. (4) The human body model isa 100 pF capacitordischargedthrougha 1.5kΩ resistorintoeach pin.The machine model isa 200 pF capacitordischargeddirectlyintoeach pin. OperatingRatings(1)(2) OperatingTemperatureRange TMIN ≤ TA ≤ TMAX LM80CIMT-3, LM80CIMT-5 −25°C ≤ TA ≤ +125°C SpecifiedTemperatureRange TMIN ≤ TA ≤ TMAX LM80CIMT-3, LM80CIMT-5 −25°C ≤ TA ≤ +125°C JunctiontoAmbientThermalResistance Package Number: PW 95°C/W(θJA (3)) SupplyVoltage(V+) +2.8V to+5.75V Ground Difference(|GND − GNDA|) ≤ 100 mV VIN VoltageRange −0.05VtoV+ + 0.05V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND, unlessotherwisespecified (3) The maximum power dissipationmust be deratedatelevatedtemperaturesand isdictatedby TJmax, θJA and theambienttemperature, TA.The maximum allowablepower dissipationatany temperatureisPD = (TJmax −T A)/θJA. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com DC ElectricalCharacteristics The followingspecificationsapplyfor+2.8VDC ≤V+ ≤ +3.8VDC forLM80CIMT-3, +4.25VDC ≤V+ ≤ +5.75VDC forLM80CIMT-5, IN0-IN6R S = 25Ω,unlessotherwisespecified.BoldfacelimitsapplyforTA = TJ = TMIN toTMAX ;allotherlimitsTA = TJ = 25°C.(1) UnitsSymbol Parameter Conditions Typical(2) Limits(3) (Limits) POWER SUPPLY CHARACTERISTICS I+ SupplyCurrent InterfaceInactiveand V+= 5.75V 0.2 2.0 mA (max) InterfaceInactiveand V+= 3.8V 0.18 1.5 mA (max) Shutdown Mode 15 μA TEMPERATURE-to-DIGITAL CONVERTER CHARACTERISTICS TemperatureError −25°C ≤ TA ≤ +125°C ±3 °C (max) Resolution 0.5 °C (min) ANALOG-to-DIGITAL CONVERTER CHARACTERISTICS Resolution(8bitswithfull-scaleat2.56V) 10 mV TUE TotalUnadjustedError See (4) ±1 % (max) DNL DifferentialNon-Linearity ±1 LSB (max) PSS Power SupplySensitivity ±1 %/V tC TotalMonitoringCycleTime See (5) 9-bitTemp resolution 1.0 1.5 sec (max) 12-bitTemp resolution 2 sec (max) MULTIPLEXER/ADC INPUT CHARACTERISTICS On Resistance 0.5 10 kΩ (max) InputCurrent(On ChannelLeakage Current) ±1 μA OffChannelLeakage Current ±1 μA FAN RPM-to-DIGITAL CONVERTER Fan RPM Error +25°C ≤ TA ≤ +75°C ±10 % (max) Full-scaleCount 255 (max) FAN1 and FAN2 NominalInput Divisor= 1,Fan Count = 153(6) 8800 RPM RPM (See FAN INPUTS ) Divisor= 2,Fan Count = 153(6) 4400 RPM Divisor= 3,Fan Count = 153(6) 2200 RPM Divisor= 4,Fan Count = 153(6) 1100 RPM InternalClockFrequency +25°C ≤ TA ≤ +75°C 20.2 kHz (min)22.5 24.8 kHz (max) 19.1 kHz (min)−10°C ≤ TA ≤ +100°C 22.5 25.9 kHz (max) 18 kHz (min)−25°C ≤ TA ≤ +125°C 22.5 27 kHz (max) (1) Each inputand outputisprotectedby a nominal6.5Vbreakdown voltagezenerdiodetoGND; as shown below,inputvoltagemagnitude up to0.3Vabove V+ or0.3VbelowGND willnotdamage theLM80. Thereareparasiticdiodesthatexistbetween theinputsand the power supplyrails.ErrorsintheADC conversioncan occurifthesediodesareforwardbiasedby more than50 mV. As an example,if V+ is4.50VDC ,inputvoltagemust be ≤ 4.55VDC ,toensureaccurateconversions. (2) TypicalsareatTJ=TA=25°C and representmost likelyparametricnorm. (3) LimitsarespecifiedtoAOQL (AverageOutgoingQualityLevel). (4) TUE (TotalUnadjustedError)includesOffset,Gain and LinearityerrorsoftheADC. (5) TotalMonitoringCycleTime includestemperatureconversion,7 analoginputvoltageconversionsand 2 tachometerreadings.Each inputvoltageconversiontakes100 ms typicaland 112 ms maximum. 8-plussignTemperatureresolutiontakes100 ms typicaland 112 ms maximum, while11-bitplussigntakes800 ms typicaland 900 ms maximum. Fan tachometerreadingstake20 ms typical,at4400 rpm,and 200 ms max. (6) The totalfancountisbased on 2 pulsesperrevolutionofthefantachometeroutput.

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 DC ElectricalCharacteristics(continued) The followingspecificationsapplyfor+2.8VDC ≤V+ ≤ +3.8VDC forLM80CIMT-3, +4.25VDC ≤V+ ≤ +5.75VDC forLM80CIMT-5, IN0-IN6R S = 25Ω,unlessotherwisespecified.BoldfacelimitsapplyforTA = TJ = TMIN toTMAX ;allotherlimitsTA = TJ = 25°C.(1) UnitsSymbol Parameter Conditions Typical(2) Limits(3) (Limits) DIGITAL OUTPUTS: A0/NTEST_OUT, INT VOUT(1) Logical“1”OutputVoltage IOUT = +5.0mA atV+ = +4.25V, 2.4 V (min) IOUT = +3.0mA atV+ = +2.8V VOUT(0) Logical“0”OutputVoltage IOUT = −5.0mA atV+ = +5.75V, 0.4 V (max) IOUT = −3.0mA atV+ = +3.8V OPEN DRAIN OUTPUTS: GPO, RST_OUT/ OS, CI VOUT(0) Logical“0”OutputVoltage IOUT =− 5.0mA atV+ = +5.75V, 0.4 V (min) IOUT = −3.0mA atV+ = +3.8V IOH HighLevelOutputCurrent VOUT = V+ 0.1 100 μA (max) RST_OUT/ OS, 30 10 ms (min)CI PulseWidth OPEN DRAIN SERIAL BUS OUTPUT: SDA VOUT(0) Logical“0”OutputVoltage IOUT = −3.0mA atV+ = +5.75V, 0.4 V (min) IOUT = −3.0mA atV+ = +3.8V IOH HighLevelOutputCurrent VOUT = V+ 0.1 100 μA (max) DIGITAL INPUTS: A0/NTEST_Out, A1-A2,BTI,CI (ChassisIntrusion),INT_IN,and NTEST_IN/Reset_IN VIN(1) Logical“1”InputVoltage 2.0 V (min) VIN(0) Logical“0”InputVoltage 0.8 V (max) SERIAL BUS INPUTS (SCL,SDA) and FAN TACH PULSE INPUTS (FAN1, FAN2) VIN(1) Logical“1”InputVoltage 0.7× V+ V (min) VIN(0) Logical“0”InputVoltage 0.3× V+ V (max) ALL DIGITAL INPUTS Except forBTI IIN(1) Logical“1”InputCurrent VIN = V+ −0.005 −1 μA (min) IIN(0) Logical“0”InputCurrent VIN = 0 VDC 0.005 1 μA (max) C IN DigitalInputCapacitance 20 pF BTI DigitalInput IIN(1) Logical“1”InputCurrent VIN = V+ −1 −10 μA (min) IIN(0) Logical“0”InputCurrent VIN = 0 VDC 500 2000 μA (max) C IN DigitalInputCapacitance 20 pF Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com AC ElectricalCharacteristics The followingspecificationsapplyfor+2.8VDC ≤V+ ≤ +3.8VDC forLM80CIMT-3, +4.25VDC ≤V+ ≤ +5.75VDC forLM80CIMT-5, unlessotherwisespecified.BoldfacelimitsapplyforTA = TJ = TMIN toTMAX ;allotherlimitsTA = TJ = 25°C.(1) Symbol Typical(2) Limits(3) UnitsParameter Conditions (Limits) SERIAL BUS TIMING CHARACTERISTICS t1 SCL (Clock)Period 2.5 μs (min) t2 Data InSetupTime toSCL High 100 ns (min) t3 Data Out StableAfterSCL Low 0 ns (min) t4 SDA Low SetupTime toSCL Low (start) 100 ns (min) t5 SDA HighHoldTime AfterSCL High(stop) 100 ns (min) (1) TimingspecificationsaretestedattheSerialBus Inputlogiclevels,VIN(0)= 0.3× V+ fora fallingedge and VIN(1)=0.7× V+ fora rising edge,when theSCL and SDA edge ratesaresimilar. (2) TypicalsareatTJ=TA=25°C and representmost likelyparametricnorm. (3) LimitsarespecifiedtoAOQL (AverageOutgoingQualityLevel). Figure1. SerialBus Timing Diagram Figure2. ESD ProtectionInputStructure Pin Name D1 D2 D3 Pin Name D1 D2 D3 INT_IN x(1) x x NTEST_IN/ x Reset_IN CI x x IN0-IN6 x x x GPO x x BTI x x x FAN1 –FAN2 x INT x x x SCL x A1-A2 x x x SDA x x A0/NTEST_Out x x x RST_OUT/ OS x (1) An x indicatesthatthediodeexists.

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 TestCircuit Figure3. DigitalOutput Load TestCircuitry Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION GENERAL DESCRIPTION The LM80 provides7 analoginputs,a temperaturesensor,a Delta-SigmaADC (Analog-to-DigitalConverter),2 fan speed counters,WATCHDOG registers,and a varietyof inputsand outputson a singlechip.A two wire SerialBus interfaceisprovided.The LM80 performspower supply,temperature,fancontroland fanmonitoring forpersonalcomputers. The LM80 continuouslyconvertsanaloginputsto 8-bitdigitalwords witha 10 mV LSB (LeastSignificantBit) weighting,yieldinginputrangesof0 to2.56V.The Analog inputsare intendedtobe connectedtotheseveral power suppliespresentin a a typicalcomputer.Temperature can be convertedto a 9-bitor 12-bittwo's complement word withresolutionsof0.5°C LSB or0.0625°C LSB, respectively. Fan inputscan be programmed toaccepteitherfanfailureindicatoror tachometersignals.Fan failuresignals can be programmed tobe eitheractivehighoractivelow.Fan inputsmeasure theperiodoftachometerpulses from the the fans,providinga highercount forlowerfan speeds.The fan inputsare digitalinputswithand acceptablerangeof0 toV+ voltsand a transitionlevelofapproximatelyV+/2volts.Fullscalefancountsare255 (8-bitcounter),which representa stopped or very slow fan.Nominal speed based on a count of 153, are programmable from 1100 to8800 RPM. Signalconditioningcircuitryisincludedtoaccommodate slow riseand falltimes. The LM80 providesa number ofinternalregisters,as detailedinFigure4.These include:

  • ConfigurationRegister: Providescontroland configuration.
  • InterruptStatusRegisters: Two registerstoprovidestatusofeach WATCHDOG limitorInterruptevent.
  • InterruptMask Registers: Allowsmasking ofindividualInterruptsources,as wellas separatemasking for each ofbothhardwareInterruptoutputs.
  • Fan Divisor/RST_OUT/ OS Registers: Bits0-5 ofthisregistercontainthedivisorbitsforFAN1 and FAN2 inputs.Bits6-7controlthefunctionoftheRST_OUT/ OS output.
  • OS Configuration/TemperatureResolution Register:The configurationof the OS (Overtemperature Shutdown)iscontrolledby thelower3 bitsofthisregister.Bit3 enables12-bittemperatureconversions.Bits 4-7reflectthelowerfourbitsofthetemperaturereadingfora 12-bitresolution.
  • Value RAM: The monitoringresults:temperature,voltages,fan counts,and Fan Divisor/RST_OUT/ OS RegisterlimitsareallcontainedintheValueRAM. The ValueRAM consistsofa totalof32 bytes.The first10 bytesare allof the results,the next 20 bytesare the Fan Divisor/RST_OUT/ OS Registerlimits,and are locatedat20h-3Fh,includingtwo unused bytesintheupperlocations. When theLM80 isstarted,itcyclesthrougheach measurement insequence,and itcontinuouslyloopsthrough the sequence approximatelyonce every second. Each measured value is compared to values storedin WATCHDOG, or Limitregisters.When the measured valueviolatesthe programmed limitthe LM80 willseta correspondingInterruptintheInterruptStatusRegisters.Two hardwareInterruptlines,INT and RST_OUT/ OS are available.INT isfullyprogrammable withmasking of each Interruptsource,and masking of each output. RST_OUT/ OS is dedicatedto the temperaturereadingWATCHDOG registers.In addition,the Fan Divisor registerhas controlbitstoenableordisablethehardwareInterrupts. AdditionaldigitalinputsareprovidedforchainingofINT,outputsofmultipleexternalLM75 temperaturesensors viatheBTI (BoardTemperatureInterrupt)input,and a CI (ChassisIntrusion)input.The ChassisIntrusioninputis designedtoacceptan activehighsignalfroman externalcircuitthatlatcheswhen thecase isremoved fromthe computer.

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 INTERFACE Figure4. LM80 RegisterStructure Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com InternalRegistersoftheLM80 Table1.The internalregistersand theircorrespondinginternalLM80 address isas follows: Register LM80 InternalHex Power on Value Notes Address (Thisisthedata tobe writtentothe Address Register) ConfigurationRegister 00h 0000 1000 InterruptStatusRegister1 01h 0000 0000 InterruptStatusRegister2 02h 0000 0000 InterruptMask Register1 03h 0000 0000 InterruptMask Register2 04h 0000 0000 Fan Divisor/RST_OUT/ OS 05h 0001 0100 FAN1 and FAN2 divisor= 2 (countof153 = 4400 RPM) Register OS/ Configurationand 06h 0000 0001 TemperatureResolution Register ValueRAM 20h-3Fh SerialBus Interface SerialBus Timing Figure5. SerialBus WritetotheInternalAddress Registerfollowedby theData Byte Figure6. SerialBus WritetotheInternalAddress RegisterOnly

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 Figure7. SerialBus Read from a RegisterwiththeInternalAddress RegisterPresettoDesiredLocation The SerialBus controllinesconsistsoftheSDA (serialdata),SCL (serialclock)and A0-A1 (address)pins.The LM80 can onlyoperateas a slave.The SCL lineonlycontrolstheserialinterface,allotherclockfunctionswithin LM80 such as theADC and fancountersaredone witha separateasynchronousinternalclock. When usingtheSerialBus Interfacea writewillalwaysconsistoftheLM80 SerialBus InterfaceAddress byte, followedby theInternalAddressRegisterbyte,thenthedatabyte.Therearetwo casesfora read: 1. IftheInternalAddressRegisterisknown tobe atthedesiredAddress,simplyreadtheLM80 withtheSerial Bus InterfaceAddressbyte,followedby thedatabytereadfromtheLM80. 2. IftheInternalAddress Registervalueisunknown, writetotheLM80 withtheSerialBus InterfaceAddress byte,followedby the InternalAddress Registerbyte.Then restartthe SerialCommunication witha Read consistingoftheSerialBus InterfaceAddressbyte,followedby thedatabytereadfromtheLM80. The defaultpower on SerialBus addressfortheLM80 is:0101(A2)(A1)(A0)binary,where A0-A2 reflectthestate ofthepinsdefinedby thesame names. Allofthesecommunicationsare depictedintheSerialBus InterfaceTimingDiagrams as shown inSerialBus Timing. USING THE LM80 Power On When power isfirstapplied,the LM80 performsa “power on reset” on severalof itsregisters.The power on conditionof registersisshown inTable 1. Registerswhose power on valuesare not shown have power on conditionsthatareindeterminate(thisincludesthevalueRAM and WATCHDOG limits).The ADC isinactive.In most applications,usuallythe firstactionafterpower on would be to writeWATCHDOG limitsintothe Value RAM. Resets ConfigurationRegisterINITIALIZATIONaccomplishesthe same functionas power on reset.The Value RAM conversionresults,and ValueRAM WATCHDOG limitsarenotReset and willbe indeterminateimmediatelyafter power on.IftheValueRAM containsvalidconversionresultsand/orValueRAM WATCHDOG limitshave been previouslyset,they willnot be affectedby a ConfigurationRegisterINITIALIZATION.Power on reset,or ConfigurationRegisterINITIALIZATION,clearorinitializethefollowingregisters(theinitializedvaluesareshown inTable1):

  • ConfigurationRegister
  • InterruptStatusRegister1
  • InterruptStatusRegister2
  • InterruptMask Register1
  • InterruptMask Register2
  • Fan Divisor/RST_OUT/ OS Register
  • OS Configuration/TemperatureResolutionRegister
  • Value Ram (RegistersatAddress 20h - 3Fh, which include:Temperaturereading,IN0-IN6readings,FAN1 and FAN2 readings,and WATCHDOG limits) Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com ConfigurationRegisterINITIALIZATIONisaccomplishedby settingBit7 oftheConfigurationRegisterhigh.This Bitautomaticallyclearsafterbeingset. The LM80 can be resettoit's“power on state”by takingNTEST_IN/Reset_INpinlowforatleast50 ns. Using theConfigurationRegister The ConfigurationRegisterprovidesallcontrolovertheLM80. At power on,theADC isstoppedand INT_Clear isasserted,clearingtheINT and RST_OUT/ OS hardwireoutputs.The ConfigurationRegisterstartsand stops the LM80, enablesand disablesINT outputs,clearsand setsCI and GPO I/Opins,initiatesresetpulseon RST_OUT/ OS pin,and providestheResetfunctiondescribedinResets. Bit0 oftheConfigurationRegistercontrolsthemonitoringloopoftheLM80. SettingBit0 low stopstheLM80 monitoringloopand putstheLM80 inshutdown mode, reducingpower consumption.SerialBus communication ispossiblewithany registerintheLM80 althoughactivityon theselineswillincreaseshutdown current,up toas much as maximum ratedsupplycurrent,whiletheactivitytakesplace.TakingBit0 highstartsthemonitoring loop,describedinmore detailsubsequently. Bit1 oftheConfigurationRegisterenablestheINT Interrupthardwireoutputwhen thisbitistakenhigh. Bit2 oftheConfigurationRegisterdefineswhethertheINT pinisopen sourceoropen drain. Bit3 clearstheINT outputwhen takenhigh.The LM80 monitoringfunctionwillstopuntilbit3 istakenlow.The contentoftheInterrupt(INT)StatusRegisterswillnotbe affected. Bit4,when takenhigh,willinitiatea 10 ms RESET signalon theRST_OUT/ OS output(when thispinisinthe RST mode). When bit5 istakenhightheCI (ChassisIntrusion)pinisreset. Bit6 oftheconfigurationregistersetsorclearstheGPO output.Thispincan be used insoftwarepower control by activatingan externalpower controlMOSFET. StartingConversions

3.4 STARTING CONVERSION The monitoringfunction(Analoginputs,temperature,and fan speeds) in the

LM80 isstartedby writingtotheConfigurationRegisterand settingINT_Clear(Bit3),low,and Start(Bit0),high. The LM80 then performsa round-robinmonitoringof allanalog inputs,temperature,and fan speed inputs approximatelyonce a second.Ifthetemperatureresolutionissetto12 bitsone completemonitoringfunctionwill takeapproximately2 seconds.The sequence of itemsbeingmonitoredcorrespondsto locationsinthe Value RAM (exceptfortheTemperaturereading)and is: 1. Temperature 2. IN0 3. IN1 4. IN2 5. IN3 6. IN4 7. IN5 8. IN6 9. Fan 1 10. Fan 2 Reading Conversion Results The conversionresultsareavailableintheValueRAM. Conversionscan be readatany timeand willprovidethe resultofthelastconversion.Because theADC stops,and startsa new conversionwhenever theconversionis read,readsofany singlevalueshouldnotbe done more oftenthanonce every120 ms. When readingallvalues withthe temperatureresolutionset to 9-bits,allowat least1.5 seconds between readinggroups of values. Reading more frequentlythan once every1.5 seconds can alsopreventcompleteupdatesof InterruptStatus Registersand InterruptOutputs.Ifthetemperatureresolutionissetto12-bit,allowatleast2.0seconds between readinggroupsofvalues.

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 A typicalsequence ofeventsupon power on oftheLM80 wouldconsistof: 1. SetWATCHDOG Limits 2. SetInterruptMasks 3. StarttheLM80 monitoringprocess ANALOG INPUTS The 8-bitADC has a 10 mV LSB, yieldinga 0V to2.55V (2.56- 1LSB) inputrange.Thisistrueforallanalog inputs.InPC monitoringapplicationstheseinputswould most oftenbe connectedtopower supplies.The 2.5, 3.3,± 5 and ± 12 voltinputsshouldbe attenuatedwithexternalresistorstoany desiredvaluewithintheinput range.Care shouldbe takennottoexceed thepower supplyvoltage(V+)atany time. A typicalapplication,such as isshown inFigure8,mightselecttheinputvoltagedividertoprovide1.9V atthe analoginputsoftheLM80. Thisissufficientlyhighforgood resolutionofthevoltage,yetleavesheadroom for upward excursionsfrom thesupplyofabout25%. To simplifytheprocessofresistorselection,setthevalueof R2 first.Selecta valueforR2 orR4 between 10 kΩ and 100 kΩ Thisislow enough toavoiderrorsdue toinput leakagecurrentsyet high enough to both protectthe inputsunder overdriveconditionsas wellas minimize loadingofthesource.Then selectR1 orR3 toprovidea 1.9Vinputas show inFigure8. Resistorvaluesshown intableprovideapproximately1.9Vattheanaloginputs. Figure8. InputExamples ForpositiveinputvoltagestheequationforcalculatingR1 isas follows: R1 = [(VS − VIN)/VIN]R2 (1) FornegativeinputvoltagestheequationforCalculatingR3 isas follows: R3 = [(VS − VIN)/(VIN − 5V)]R4 (2) The analoginputshave internaldiodesthatclamp inputsexceedingthe power supplyand ground.Exceeding any analog inputhas no detrimentaleffecton otherchannels.The inputdiodes willalso clamp voltages appearingattheinputsofan un-poweredLM80. Externalresistorsshouldbe includedtolimitinputcurrentsto thevaluesgivenintheABSOLUTE MAXIMUM RATINGS forInputCurrentAt Any Pin.Inputswiththeattenuator networkswillusuallymeet theserequirements.Ifitispossibleforinputswithoutattenuatorstobe turnedon while LM80 ispowered off,additionalresistorsofabout10 kΩ shouldbe added inserieswiththeinputstolimitthe inputcurrent. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com VoltageMeasurements R1 or R3 R2 or R4 VoltageatAnalog Inputs (VS) (ADC code 190) +2.5V 23.7kΩ 75 kΩ +1.9V +3.3V 22.1kΩ 30 kΩ +1.9V +5.0V 24 kΩ 14.7kΩ +1.9V +12V 160 kΩ 30.1kΩ +1.9V −12V 160 kΩ 35.7kΩ +1.9V −5V 36 kΩ 16.2kΩ +1.9V LAYOUT AND GROUNDING Analoginputswillprovidebestaccuracywhen referredtotheAGND pinora supplywithlow noise.A separate, low-impedanceground plane foranalog ground,which providesa ground pointforthe voltagedividersand analogcomponents,willprovidebestperformancebut isnot mandatory.Analog components such as voltage dividersshouldbe locatedphysicallyas closeas possibletotheLM80. The power supplybypass,the parallelcombinationof 10 μF (electrolyticor tantalum)and 0.1 μF (ceramic) bypass capacitorsconnectedbetween pin9 and ground,shouldalsobe locatedas closeas possibleto the LM80. FAN INPUTS Inputsareprovidedforsignalsfromfansequippedwithtachometeroutputs.These arelogic-levelinputswithan approximatethresholdofV+/2.SignalconditioningintheLM80 accommodates theslowriseand falltimestypical offantachometeroutputs.The maximum inputsignalrange is0 toV+.Intheeventtheseinputsare supplied from fan outputswhich exceed 0 to V+, eitherresistivedivisionor diodeclampingmust be includedto keep inputswithinan acceptablerange,as shown inAlternativesforFan Inputs. R2 isselectedso thatitdoes not developexcessiveerrorvoltagedue toinputleakage.R1 isselectedbased on R2 toprovidea minimum inputof 2V and a maximum ofV+.R1 shouldbe as low as possibletoprovidethemaximum possibleinputup toV+ for bestnoiseimmunity.Alternatively,use a shuntreferenceorzenerdiodetoclamp theinputlevel. Iffanscan be powered whilethepower totheLM80 isoff,theLM80 inputswillprovidediodeclamping.Limit inputcurrenttotheInputCurrentatAny Pin specificationshown intheAbsoluteMaximum Ratingssection.In most cases,open collectoroutputswithpull-upresistorsinherentlylimitthiscurrent.Ifthismaximum current couldbe exceeded,eithera largerpullup resistorshouldbe used or resistorsconnectedinserieswiththefan inputs. The Fan Inputsgate an internal22.5 kHz oscillatorforone periodof the Fan signalintoan 8-bitcounter (maximum count= 255).The defaultdivisor,locatedintheVID/FanDivisorRegister,issetto2 (choicesare1,2, 4,and 8)providinga nominalcountof153 fora 4400 rpm fanwithtwo pulsesperrevolution.Typicalpracticeis toconsider70% ofnormalRPM a fanfailure,atwhichpointthecountwillbe 219. Determinethefancountaccordingto: (3) Note thatFan 1 and Fan 2 DivisorsareprogrammableviatheFan Divisor/RST_OUT/ OS Register. FAN1 and FAN2 inputscan alsobe programmed tobe levelsensitivedigitalinputs. Fans thatprovideonlyone pulseperrevolutionwould requirea divisorsettwiceas highas fansthatprovidetwo pulses,thusmaintaininga nominalfan countof 153. Thereforethe divisorshouldbe setto 4 fora fan that provides1 pulseperrevolutionwitha nominalRPM of4400.

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 AlternativesforFan Inputs Fan withTach Pull-Upto+5V Fan withTach Pull-Upto+12V, or Totem-Pole Output and ResistorAttenuator Fan withTach Pull-Upto+12V and Diode Clamp Fan withStrong Tach Pull-Upor Totem Pole Output and Diode Clamp Countsarebased on 2 pulsesperrevolutiontachometeroutputs. RPM Time per Revolution Counts for“Divideby 2” Comments (Default)inDecimal 4400 13.64ms 153 counts TypicalRPM 3080 19.48ms 219 counts 70% RPM 2640 22.73ms 255 counts 60% RPM (maximum counts) Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com Counts fortheGiven Speed Time per RevolutionforMode Select Nominal RPM Time per Revolution 70% RPMinDecimal 70% RPM Divideby 1 8800 6.82ms 153 6160 9.74ms Divideby 2 4400 13.64ms 153 3080 19.48ms Divideby 4 2200 27.27ms 153 1540 38.96ms Divideby 8 1100 54.54ms 153 770 77.92ms (4) Temperature Measurement System The LM80 bandgap typetemperaturesensorand ADC perform9-bitora 12-bittwo's-complementconversionsof the temperature.An 8-bitdigitalcomparatoris also incorporatedthatcompares the readingsto the user- programmableHot and Overtemperaturesetpoints,and Hysteresisvalues. (Non-LinearScaleforClarity) Figure9. 9-bitTemperature-to-DigitalTransferFunction (Non-LinearScaleforClarity) Figure10. 12-bitTemperature-to-DigitalTransferFunction

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 Temperature Data Format Temperaturedatacan be readfromtheTemperature,Thot,Thot hyst,Tos,and Tos hystsetpointregisters;and written totheThot,Thot hyst,Tos,and Tos hyst setpointregisters.These registersare locatedinregisteraddresses38h - 3Bh, and each setpointisrepresentedby an 8-bit,two'scomplement word withan LSB (LeastSignificantBit) equalto1°C: Temperature DigitalOutput Binary Hex +125°C 0111 1101 7Dh +25°C 0001 1001 19h +1.0°C 0000 0001 01h +0°C 0000 0000 00h −1.0°C 1111 1111 FFh −25°C 1110 0111 E7h −55°C 1100 1001 C9h By defaultTemperatureRegisterdata isrepresentedby a 9-bittwo'scomplement digitalword withthe LSB havinga resolutionof0.5°C: Temperature DigitalOutput Binary Hex +125°C 0 1111 1010 0 FAh +25°C 0 0011 0010 0 32h +1.5°C 0 0000 0011 0 03h +0°C 0 0000 0000 0 00h −0.5°C 1 1111 1111 1 FFh −25°C 1 1100 1110 1 CEh −55°C 1 1001 0010 1 92h TemperatureRegisterdata can alsobe representedby a 12-bittwo'scomplement digitalword witha LSB of 0.0625°C: Temperature DigitalOutput Binary Hex +125°C 0111 1100 0000 7 D0h +25°C 0001 1001 0000 1 90h +1.0°C 0000 0001 0000 0 10h +0.0625°C 0000 0000 0001 0 01h 0°C 0000 0000 0000 00h −0.0625°C 1111 1111 1111 F FFh −1.0°C 1111 1111 0000 F F0h −25°C 1110 0111 0000 E 70h −55°C 1100 1001 0000 C 90h The 8 MSBs of the Temperaturereadingcan be found at Value RAM address 27 h. The remainderof the Temperaturereadingcan be found inthe OS Configuration/TemperatureResolutionRegisterbits7-4.In 9-bit formatbit7 istheonlyvalidbit. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com Temperature Interrupts There arefourValueRAM WATCHDOG limitsfortheTemperaturereadingthataffecttheINT and OS outputsof theLM80. They are:Hot TemperatureLimit,Hot TemperatureHysteresisLimit,OS Limit,OS HysteresisLimit. There are three interruptmodes of operation:“One-Time Interrupt” mode, “DefaultInterrupt” mode, and “Comparator Mode ”. The OS outputof the LM80 can be programmed for“One-Time Interrupt” mode and “Comparator”mode. INT can be programmed for“DefaultInterrupt”mode and “One-Time”Interrupt. “DefaultInterruptmode ” operatesinthe followingway: ExceedingThot causes an Interruptthatwillremain activeindefinitelyuntilresetby readingInterruptStatusRegister1 or clearedby the INT_Clearbitin the Configurationregister.Once an Interrupteventhas occurredby crossingThot,thenreset,an Interruptwilloccur againonce thenexttemperatureconversionhas completed.The interruptswillcontinuetooccurinthismanner untilthetemperaturegoes belowThothyst,atwhichtimetheInterruptoutputwillautomaticallyclear. “One-Time Interrupt” mode operatesinthefollowingway: ExceedingThot causes an Interruptthatwillremain activeindefinitelyuntilresetby readingInterruptStatusRegister1 or clearedby the INT_Clearbitin the Configurationregister.Once an Interrupteventhas occurredby crossingThot, then reset,an Interruptwillnot occuragainuntilthetemperaturegoes belowThothyst. “Comparator” mode operatesinthefollowingway: ExceedingTos causes theOS outputtogo Low (default). OS willremain Low untilthe temperaturegoes below Tos. Once the temperaturegoes below Tos, OS willgo High. A. Thisdiagramdoes notreflectallthepossiblevariationsintheoperationoftheOS and INT outputsnor theOS and Hot Temp bits.The interruptoutputsareclearedby readingtheappropriateInterruptStatusRegister. Figure11. Temperature InterruptResponse Diagram

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 THE LM80 INTERRUPT STRUCTURE Figure12. InterruptStructure Figure12 depictstheInterruptStructureoftheLM80. The LM80 can generateInterruptsas a resultofeach ofits internalWATCHDOG registerson theanalog,temperature,and faninputs. InterruptInputs ExternalInterruptscan come from thefollowingsources.Whilethelabelsuggestsa specifictypeor sourceof Interrupt,thislabelisnota restrictionofitsusage,and itcouldcome fromany desiredsource:

  • BTI - Thisisan activelow Interruptintendedtocome from theO.S. outputofLM75 temperaturesensors. The LM75 O.S. outputgoes activewhen itstemperatureexceeds a programmed threshold.Up to8 LM75's can be connectedtoa singleSerialBus bus withtheirO.S.output'swireor'dtotheBTI inputoftheLM80. If thetemperatureofany LM75 exceeds itsprogrammed limit,itdrivesBTI low.Thisgeneratesan Interruptto notifythehostofa possibleovertemperaturecondition.Providesan internalpull-upof10 kΩ.
  • CI (ChassisIntrusion)- Thisisan activehighinterruptfromany typeofdevicethatdetectsand captures chassisintrusionviolations.Thiscouldbe accomplishedmechanically,optically,or electrically,and circuitry externaltotheLM80 isexpectedtolatchtheevent.The designoftheLM80 allowsthisinputtogo higheven withno power appliedtotheLM80, and no clampingor otherinterferencewiththelinewilloccur.Thisline can alsobe pulledlow foratleast10 ms by theLM80 toreseta typicalChassisIntrusioncircuit.Accomplish thisresetby settingBit5 ofConfigurationRegisterhigh.The bitintheRegisterisself-clearing.
  • INT_IN - Thisactivelow Interruptmerelyprovidesa way to chaintheINT (Interrupt)from otherdevices throughtheLM80 totheprocessor. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com InterruptOutputs AllInterruptsareindicatedinthetwo InterruptStatusRegisters.

  • INT outputhas two mask registers,and individualmasks foreach Interrupt.As describedin Using the ConfigurationRegister, thishardware Interruptlinecan also be enabled/disabledin the Configuration Register.The ConfigurationRegisterisalsoused tosetthemode oftheINT Interruptline.
  • OS isdedicatedtotheTemperaturereadingWATCHDOG. Inthe“Fan Divisor/RST_OUT/ OS Register” the OS enablebit(Bit-6),must be sethighand theRST enablebit(Bit-7)must be setlow to enabletheOS functionon the RST_OUT/ OS pin.OS pin has two modes of operation:“One-Time Interrupt” and “Comparator”. “One-Time Interrupt” mode isselectedby takingbit-2of the “OS Configuration/Temperature ResolutionRegister”high.Ifbit-2istakenlow“Comparator”mode isselected.UnliketheOS pin,theOS bitin “InterruptStatusRegister2”functionsin“DefaultInterrupt” and “One-Time Interrupt”modes. The OS bitcan be masked toINT pinby takingbit-5inthe“InterruptMask Register2” low.A descriptionof“Comparator”, “DefaultInterrupt”and “One-Time Interrupt”modes can be foundinTemperatureData Format. InterruptClearing Reading an InterruptStatusRegisterwilloutputthe contentsof the Register,and resetthe Register.A subsequent read done beforethe analog “round-robin” monitoringloop is complete willindicatea cleared Register.Allowat least1.5 seconds to allowallRegistersto be updated between reads.In summary, the InterruptStatusRegisterclearsupon beingread,and requiresat least1.5 seconds to be updated.When the InterruptStatusRegisterclears,thehardwireinterruptlinewillalsoclearuntiltheRegistersare updatedby the monitoringloop.The hardware Interruptlinesare clearedwith the INT_Clear bit,which is Bit 3 of the ConfigurationRegister,withoutaffectingthe contentsof the Interrupt(INT) StatusRegisters.When thisbitis high,theLM80 monitoringloopwillstop.Itwillresume when thebitislow. RST and GPO OUTPUTS InPC applicationstheopen drainGPO providesa gatedrivesignaltoan externalP-channelMOSFET power switch.ThisexternalMOSFET then would keep power turnedon regardlessof the stateof frontpanelpower switcheswhen softwarepower controlisused.Inany givenapplicationthissignalisnotlimitedtothefunction describedby itslabel.For example,sincethe LM80 incorporatestemperaturesensing,the GPO outputcould alsobe utilizedto controlpower to a coolingfan.Take GPO activelow by settingBit6 inthe Configuration Registerlow. RST isintendedtoprovidea masterresettodevicesconnectedtothisline.The RST_OUT/ OS ControlbitinFan Divisor/RST_OUT/ OS Register,Bit7,must be sethightoenablethisfunction.SettingBit4 intheConfiguration Registerhighoutputsa least10 ms low on thisline,at the end of which Bit4 inthe ConfigurationRegister automaticallyclears.Again,the labelforthispin isonlyitssuggesteduse. In applicationswhere the RST capabilityisnotneeded itcan be used forany typeofdigitalcontrolthatrequiresa 10 ms activelow open drain output. NAND TREE TESTS A NAND treeisprovidedintheLM80 forAutomated TestEquipment(ATE) boardlevelconnectivitytesting.Ifthe userappliesa logiczerototheNTEST_IN/Reset_INinputpin,thedevicewillbe intheNAND treetestmode. A0/NTEST_OUT willbecome the NAND treeoutputpin.To performa NAND treetestallpinsincludedinthe NAND treeshouldbe drivento1.BeginningwithIN0 and workingclockwisearound thechip,each pincan be toggledand a resultingtogglecan be observedon A0/NTEST_OUT. The followingpinsare excludedfrom the NAND tree test:GNDA (analog ground),GND (digitalground),V + (power supply),A0/NTEST_OUT, NTEST_IN/Reset_INand RST_OUT/ OS. Allowfora typicalpropagationdelayof500 ns.

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 FAN MANUFACTURERS Manufacturersofcoolingfanswithtachometeroutputsarelistedbelow: NMB Tech 9730 IndependenceAve. Chatsworth,California91311 818 341-3355 818 341-8207 Model Number Frame Size AirflowCFM 2408NL 2.36insq.X 0.79in 9-16 (60mm sq.X 20 mm) 2410ML 2.36insq.X 0.98in 14-25 (60mm sq.X 25 mm) 3108NL 3.15insq.X 0.79in 25-42 (80mm sq.X 20 mm) 3110KL 3.15insq.X 0.98in 25-40 (80mm sq.X 25 mm) MechatronicsInc. P.O.Box 20 MercerIsland,WA 98040 800 453-45698 Varioussizesavailablewithtachoutputoption. Sanyo Denki America,Inc. 468 Amapola Ave. Torrance,CA 90501 310 783-5400 Model Number Frame Size AirflowCFM 109P06XXY601 2.36insq.X 0.79in 11-15 (60mm sq.X 20 mm) 109R06XXY401 2.36insq.X 0.98in 13-28 (60mm sq.X 25 mm) 109P08XXY601 3.15insq.X 0.79in 23-30 (80mm sq.X 20 mm) 109R08XXY401 3.15insq.X 0.98in 21-42 (80mm sq.X 25 mm) Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com REGISTERS AND RAM Address Register The main registeristheADDRESS Register.The bitdesignationsareas follows: Bit Name Read/Write Description 7-0 AddressPointer Read/Write AddressofRAM and Registers.See thetablesbelowfordetail. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 AddressPointer(PowerOn default00h) A7 A6 A5 A4 A3 A2 A1 A0 Address PointerIndex(A7–A0) Registersand RAM A6 –A0 inHex Power On Value ofRegisters: <7:0> inBinary ConfigurationRegister 00h 0000 1000 InterruptStatusRegister1 01h 0000 0000 InterruptStatusRegister2 02h 0000 0000 InterruptMask Register1 03h 0000 0000 InterruptMask Register2 04h 0000 0000 Fan Divisor/RST_OUT/ OS 05h 0001 0100 OS Configuration/TemperatureResolution 06h 0000 0001 Register ValueRAM 20h–3Fh ConfigurationRegister— Address 00h Power on default<7:0> = 00001000 binary Bit Name Read/Write Description 0 Start Read/Write A one enablesstartupofmonitoringoperations,a zeroputsthepartinstandbymode. Note:The outputsofInterruptpinswillnotbe clearediftheuserwritesa zerotothislocationafter an interrupthas occurredunlike“INT_Clear”bit.Atstartup,limitcheckingfunctionsand scanning begin.Note,alllimitsshouldbe setintheValueRAM beforesettingthisbitHIGH. 1 INT Enable Read/Write A one enablestheINT Interruptoutput. 2 INT polarityselectRead/Write A one selectsan activehighopen sourceoutputwhilea zeroselectsan activelowopen drain output. 3 INT_Clear Read/Write A one disablestheINT and RST_OUT/ OS outputswithoutaffectingthecontentsofInterruptStatus Registers.The devicewillstopmonitoring.Itwillresume upon clearingofthisbit. 4 RESET Read/Write A one outputsatleasta 10 ms activelowresetsignalatRESET, if<7> = 1 and <6> = 0 intheFan Divisor/RST_OUT/ OS Register.Thisbitisclearedonce thepulsehas gone inactive. 5 ChassisClear Read/Write A one clearstheCI (ChassisIntrusion)pin.ThisbitclearsitselfaftertheCI pinscleared. 6 GPO Read/Write A one inthisbitdrivesa one on GPO (GeneralPurposeOutput)pin. 7 INITIALIZATION Read/Write A one restorespower on defaultvaluetotheConfigurationRegister,InterruptStatusRegisters, InterruptMask Registers,Fan Divisor/RST_OUT/ OSRegister,and theOS Configuration/TemperatureResolutionRegister.Thisbitclearsitselfsincethepower on defaultis zero.

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 InterruptStatusRegister1— Address 01h Power on default<7:0> = 0000 0000 binary Bit Name Read/Write Description 0 IN0 Read Only A one indicatesa HighorLow limithas been exceeded. 1 IN1 Read Only A one indicatesa HighorLow limithas been exceeded. 2 IN2 Read Only A one indicatesa HighorLow limithas been exceeded. 3 IN3 Read Only A one indicatesa HighorLow limithas been exceeded. 4 IN4 Read Only A one indicatesa HighorLow limithas been exceeded. 5 IN5 Read Only A one indicatesa HighorLow limithas been exceeded. 6 IN6 Read Only A one indicatesa HighorLow limithas been exceeded. 7 INT_IN Read Only A one indicatesthata Low has been detectedon theINT_IN. InterruptStatusRegister2— Address 02h Power on default<7:0> = 0000 0000 binary Bit Name Read/Write Description 0 Hot Temperature Read Only A one indicatesa HighorLow limithas been exceeded.Only“One-Time Interrupt”and “DefaultInterrupt”modes aresupported.The mode issetby bit-6oftheInterruptMask Register2.

1 BTI Read Only A one indicatesthatan interrupthas occurredfromtheBoard TemperatureInterrupt(BTI)

inputpin.BTI can be tiedtotheOS outputofmultipleLM75 chips. 2 FAN1 Read Only A one indicatesthata fancountlimithas been exceeded. 3 FAN2 Read Only A one indicatesthata fancountlimithas been exceeded. 4 CI (Chassis Read Only A one indicatesCI (ChassisIntrusion)has gone high. Intrusion) 5 OS bit Read Only A one indicatesa Highora Low OS Temperaturelimithas been exceed.Only“One-Time Interrupt”and “DefaultInterrupt”modes aresupported(seeTemperatureInterruptsand InterruptOutputs).The mode issetby bit-7oftheInterruptMask Register2.

6 Reserved Read Only

7 Reserved Read Only

InterruptMask Register1— Address 03h Power on default<7:0> = 0000 0000 binary Bit Name Read/Write Description 0 IN0 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 1 IN1 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 2 IN2 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 3 IN3 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 4 IN4 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 5 IN5 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 6 IN6 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 7 INT_IN Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com InterruptMask Register2— Address 04h Power on default<7:0> = 0000 0000 binary Bit Name Read/Write Description 0 Hot Temperature Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 1 BTI Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 2 FAN1 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 3 FAN2 Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 4 CI (Chassis Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. Intrusion) 5 OS bit Read/Write A one disablesthecorrespondinginterruptstatusbitforINT interrupt. 6 Hot Temperature Read/Write A zero selectsthe defaultinterruptmode which givesthe user an interruptifthe temperatureInterruptmode goes above thehotlimit.The interruptwillbe clearedonce thestatusregisterisread,butitwillselect againbe generatedwhen thenextconversionhas completed.Itwillcontinuetodo so untilthe temperaturegoes belowthehysteresislimit. A one selectstheone timeinterruptmode whichonlygivestheuserone interruptwhen itgoes above thehotlimit.The interruptwillbe clearedonce thestatusregisterisread.Anotherinterrupt willnotbe generateduntilthetemperaturegoes below thehysteresislimit.Itwillalsobe cleared ifthe statusregisterisread.No more interruptswillbe generateduntilthe temperaturegoes above thehotlimitagain.The correspondingbitwillbe clearedinthestatusregistereverytimeit isreadbutmay notsetagainwhen thenextconversionisdone (See Figure12). 7 OS bitInterrupt Read/Write A zero selectsthe defaultinterruptmode which givesthe user an interruptifthe temperaturemode select goes above thehotlimit.The interruptwillbe clearedonce thestatusregisterisread,butitwill againbe generatedwhen thenextconversionhas completed.Itwillcontinuetodo so untilthe temperaturegoes belowthehysteresislimit. A one selectstheone timeinterruptmode whichonlygivestheuserone interruptwhen itgoes above thehotlimit.The interruptwillbe clearedonce thestatusregisterisread.Anotherinterrupt willnotbe generateduntilthetemperaturegoes below thehysteresislimit.Itwillalsobe cleared ifthe statusregisterisread.No more interruptswillbe generateduntilthe temperaturegoes above thehotlimitagain.The correspondingbitwillbe clearedinthestatusregistereverytimeit isreadbutmay notsetagainwhen thenextconversionisdone (See Figure12). Fan DivisorRegister/RST_OUT/ OS — Address 05h Power on – <7:4> is0101,and <3:0>ismapped toVID <3:0> Bit Name Read/Write Description 0 FAN1 Mode Select Read/Write A one selectsthelevelsensitiveinputmode whilea zeroselectsFan countmode fortheFAN1 inputpin. 1 FAN2 Mode Select Read/Write A one selectsthelevelsensitiveinputmode whilea zeroselectsFan countmode fortheFAN2 inputpin. 2-3 FAN1 RPM Control Read/Write FAN1 Speed Control. <3:2> = 00 -divideby 1; <3:2> = 01 -divideby 2; <3:2> = 10 -divideby 4; <3:2> = 11 -divideby 8. Iflevelsensitiveinputisselected:>2< = 1 selectsand active-lowinput(An interruptwillbe generatediftheFAN2 inputisLow),>2< = 0 selectsan active-highinput(an interruptwillbe generatediftheFAN2 inputisHigh). 4-5 FAN2 RPM Control Read/Write FAN2 Speed Control. <5:4> = 00 -divideby 1; <5:4> = 01 -divideby 2; <5:4> = 10 -divideby 4; <5:4> = 11 -divideby 8. Iflevelsensitiveinputisselected:<2> = 1 selectsand active-lowinput(An interruptwillbe generatediftheFAN2 inputisLow),<2> = 0 selectsan active-highinput(an interruptwillbe generatediftheFAN2 inputisHigh).

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www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013 Bit Name Read/Write Description 6 OS pinenable Read/Write A one enablesOS mode on theRST_OUT/ OS outputpin,whileBit7 ofthisregisterissetto zero.Ifbits6 and 7 ofthisregisteraresettozerotheRST_OUT/ OS pinisdisabled. 7 RST enable Read/Write A one setstheRST_OUT/ OS pinintheRST mode. IntheRST mode, bit7 oftheFan Divisor/RST_OUT/ OS Registerhas tobe settoone.Ifbits6 and 7 ofthisregisteraresetto zerotheRST_OUT/ OS pinisdisabled. OS Configuration/TemperatureResolutionRegister— Address 06h Power on defaultSerialBus address<7:0> = 0000 0001 binary Bit Name Read/Write Description 0 OS status Read only StatusoftheOS.ThisbitmirrorsthestateoftheRST_OUT/ OS pinwhen intheOS mode. 1 OS Polarity Read/Write A zeroselectsOS tobe active-low,whilea one selectsOS tobe activehigh.OS isan open- drainoutput. 2 OS mode select Read/Write A one selectstheone timeinterruptmode forOS, whilea zeroselectscomparatormode for OS. (See inTemperatureMeasurement System) 3 Temperature Read/Write A zeroselectsthedefault8-bitplussignresolutiontemperatureconversionswhilea one selects ResolutionControl 11-bitplussignresolutiontemperatureconversions.8-bitplussignconversionstimeis approximately100 ms, while11-bitplussignconversiontimeisapproximately2 seconds. 4-7 Temp [3:0] Read/Write The lowernibble(4LSBs) ofthe11-bitplussigntemperaturedata.<4> = Temp [0](nibbleLSB, 0.0625°C),<5> = Temp [1],<6> = Temp [2],<7> = Temp 3 (nibbleMSB, 0.5°C).For8-bitplus signtemperatureresolution,<7> = Temp [0](LSB,0.5°C) while<4:6> areundefined. Value RAM — Address 20h–3Fh Address A7 –A0 Description 20h IN0 reading 21h IN1 reading 22h IN2 reading 23h IN3 reading 24h IN4 reading 25h IN5 reading 26h IN6 reading 27h Temperaturereading 28h FAN1 reading Note:Thislocationstoresthenumber ofcountsoftheinternalclockperrevolution. 29h FAN2 reading Note:Thislocationstoresthenumber ofcountsoftheinternalclockperrevolution. 2Ah IN0 HighLimit 2Bh IN0 Low Limit 2Ch IN1 HighLimit 2Dh IN1 Low Limit 2Eh IN2 HighLimit 2Fh IN2 Low Limit 30h IN3 HighLimit 31h IN3 Low Limit 32h IN4 HighLimit 33h IN4 Low Limit 34h IN5 HighLimit 35h IN5 Low Limit 36h IN6 HighLimit 37h IN6 Low Limit 38h Hot TemperatureLimit(High) Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LM80

SNIS102F –JUNE 1999–REVISED MARCH 2013 www.ti.com Address A7 –A0 Description 39h Hot TemperatureHysteresisLimit(Low) 3Ah OS TemperatureLimit(High) 3Bh OS TemperatureHysteresisLimit(Low) 3Ch FAN1 Fan Count Limit Note:Itisthenumber ofcountsoftheinternalclockfortheLow Limitofthefanspeed. 3Dh FAN2 Fan Count Limit Note:Itisthenumber ofcountsoftheinternalclockfortheLow Limitofthefanspeed. 3Eh-3Fh Reserved NOTE Settingallones tothehighlimitsforvoltagesand fans(01111111 binaryfortemperature) means interruptswillnever be generatedexceptthecase when voltagesgo belowthelow limits. For voltageinputhighlimits,thedeviceisdoinga greaterthancomparison.For low limits, however,itisdoinga lessthanorequaltocomparison. TypicalApplication Figure13. TypicalApplicationDiagram In this PC applicationthe LM80 monitors temperature,fan speed for 2 fans, and 7 power supplyvoltages.Italsomonitorsan opticalchassisintrusiondetector.

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ProductFolderLinks:LM80

www.ti.com SNIS102F –JUNE 1999–REVISED MARCH 2013

REVISION HISTORY

Changes from RevisionE (March 2013)toRevisionF Page Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LM80

www.ti.com 1-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM80CIMT-3/NOPB NRND TSSOP PW 24 61 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -25 to 125 LM80 CIMT-3 LM80CIMTX-3/NOPB NRND TSSOP PW 24 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -25 to 125 LM80 CIMT-3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 1-Nov-2013 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM80CIMTX-3/NOPB TSSOP PW 24 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2

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