LM79CCVF

LM79 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 31

Technical content

Features

n 5 positive voltage inputs n 2 op amps for negative voltage monitoring n 3 fan speed monitoring inputs n Input for additional temperature sensors n Chassis Intrusion Detector input n WATCHDOG comparison of all monitored values n POST code storage RAM n ISA and I2C ™ Serial Bus interfaces Key Specifications j Voltage monitoring accuracy ±1% (max) j Temperature Accuracy −10˚C to +100˚C ±3˚C (max) j Supply Voltage 5V j Supply Current Operating: 1 mA typ Shutdown: 10 µA typ j ADC Resolution 8 Bits

Applications

n System Hardware Monitoring for Servers and PCs n Office Electronics n Electronic Test Equipment and Instrumentation

Ordering Information

Temperature Range Package−10˚C ≤ TA ≤ +100˚C Order Number Device Marking LM79CCVF LM79CCVF VGZ44A # Indicates Active Low (“Not”) Connection Diagram I2C ® is a registered trademark of the Phillips Corporation. DS100036-2 February 2000 LM79 Microprocessor System Hardware Monitor © 2001 National Semiconductor Corporation DS100036 www.national.com

www.national.com 2

Name(s) Pin Number Number of Pins Type Description IORD 1 1 Digital Input An active low standard ISA bus I/O Read Control. IOWR 2 1 Digital Input An active low standard ISA bus I/O Write Control. SYSCLK 3 1 Digital Input The reference clock for the ISA bus. Typically ranges from 4.167 MHz to 8.33 MHz. The minimum clock frequency this input can handle is 1 Hz. D7–D0 4–11 8 Digital I/O Bi-directional ISA bus Data lines. D0 corresponds to the low order bit, with D7 the high order bit. VCC (+5V) 12 1 POWER +5V V CC power. Bypass with the parallel combination of 10 µF (electolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors. GNDD 13 1 GROUND Internally connected to all digital circuitry. SMI__IN 14 1 Digital Input Chainable SMI (System Management Interrupt) Input. This is an active low input that propagates the SMI signal to the SMI output of the LM79 via SMI Mask Register Bit 6 and SMI enable Bit 1 of the Configuration Register. Chassis Intrusion 15 1 Digital I/O An active high input from an external circuit which latches a Chassis Intrusion event. This line can go high without any clamping action regardless of the powered state of the LM79. The LM79 provides an internal open drain on this line, controlled by Bit 7 of NMI Mask Register 2, to provide a minimum 20 ms reset of this line. DS100036-3 LM79 www.national.com3

Pin Description(Continued) Pin Name(s) Pin Number Number of Pins Type Description Power Switch Bypass 16 1 Digital Output An active low open drain output intended to drive an external P-channel power MOSFET for software power control. FAN3–FAN1 17–19 3 Digital Input 0V to +5V amplitude fan tachometer input. SCL 20 1 Digital Input Serial Bus Clock. SDA 21 1 Digital I/O Serial Bus bidirectional Data. RESET 22 1 Digital Output Master Reset, 5 mA driver (open drain), active low output with a 20 ms minimum pulse width. Available when enabeld via Bit 7 in SMI Mask Register 2. VID4/NTEST 23 1 Digital Input/Test Output By default an input for the VID4 power supply readout for the system processor (Pentium/PRO). Can be programmed as a NAND Tree totem-pole output that provides board-level connectivity testing. Refer to Section 11.0on NAND Tree testing. GNDA 24 1 GROUND Internally connected to all analog circuitry. The ground reference for all analog inputs. −IN6 25 1 Analog Input Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG INPUTS”. FB6 26 1 Analog Output Output of inverting op amp for Input 6. Refer to Section 4.0, “ANALOG INPUTS”. FB5 27 1 Analog Output Output of inverting op amp for Input 5. Refer to Section 4.0, “ANALOG INPUTS”. −IN5 28 1 Analog Input Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG INPUTS”. IN4–IN0 29–33 5 Analog Input 0V to 4.096V FSR Analog Inputs. VID3–VID0 34–37 4 Digital Input Inputs for the power supply readouts for system microprocessor (Pentium/PRO). This value is read in the VID/Fan Divisor Register. BTI 38 1 Digital Input Board Temperature Interrupt driven by O.S. outputs of additional temperature sensors such as LM75. Provides internal pull-up of 10 kΩ . NMI/IRQ 39 1 Digital Output Non-Maskable Interrupt (open source)/Interrupt Request (open drain). The mode is selected with Bit 5 of the Configuration Register and the output is enabled when Bit 2 of the Configuration Register is set to 1. The default state is disabled and IRQ mode. SMI 40 1 Digital Output System Management Interrupt (open drain). This output is enabled when Bit 1 in the Configuration Register is set to 1. The default state is disabled. A2–A0 41–43 3 Digital Input The three lowest order bits of the 16-bit ISA Address Bus. A0 corresponds to the lowest order bit. CS 44 1 Digital Input Chip Select input from an external decoder which decodes high order address bits on the ISA Address Bus. This is an active low input. TOTAL PINS 44 LM79 www.national.com 4

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (V CC ) 6.5V Voltage on Any Input or Output Pin −0.3V to (VCC +0.3V) Ground Difference (GNDD–GNDA) ±300 mV Input Current at any Pin (Note 3) ±5m A Package Input Current (Note 3) ±20 mA Maximum Junction Temperature (TJ max) 150˚C ESD Susceptibility(Note 5) Human Body Model 2000V Machine Model 175V Soldering Information Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C Storage Temperature −65˚C to +150˚C Operating Ratings(Notes 1, 2) Operating Temperature Range T MIN ≤ TA ≤ TMAX Specified Temperature Range T MIN ≤ TA ≤ TMAX Junction to Ambient Thermal Resistance (θJA(Note 4) ) Supply Voltage (VCC ) +4.25V to +5.75V Ground Difference (IGNDD–GNDAI) ≤100 mV VIN Voltage Range −0.05V to V CC + 0.05V The following specifications apply for +4.25 VDC ≤VCC ≤ +5.75 VDC ,fSYSCLK = 8.33 MHz, RS =2 5Ω , unless otherwise speci- fied.Boldface limits apply for TA =T J =T MIN to TMAX ;all other limits TA =T J = 25˚C. (Note 7) Symbol Parameter Conditions Typical Limits Units (Note 8) (Note 9) (Limits) POWER SUPPLY CHARACTERISTICS I CC Supply Current Interface Inactive 1.0 2 mA (max) Shutdown Mode 10 µA TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS Accuracy −10˚C ≤ TA ≤ +100˚C ±3 ˚C (max) Resolution 1 ˚C (min) ANALOG-TO-DIGITAL CONVERTER CHARACTERISTICS Resolution (8 bits with full-scale at 4.096V) 16 mV TUE Total Unadjusted Error (Note 10) ±1 % (max) DNL Differential Non-Linearity ±1 LSB (max) PSS Power Supply Sensitivity ±1 %/V tC Total Monitoring Cycle Time (Note 11) 1.0 1.5 sec (max) OP AMP CHARACTERISTICS Output Current (Sourcing) 50 µA Input Offset Voltage I OUT =5 0µ A ±1m V Input Bias Current ±0.1 nA PSRR 60 dB DC Open Loop Gain 70 dB Gain Bandwidth Product 500 kHz MULTIPLEXER/ADC INPUT CHARACTERISTICS On Resistance 400 2000 Ω (max) Off Channel Leakage Current ±0.1 nA Input Current (On Channel Leakage Current) ±0.1 nA FAN RPM-TO-DIGITAL CONVERTER Accuracy +25˚C ≤ TA ≤ +75˚C ±10 % (max) Full-scale Count 255 (max) LM79 www.national.com5

The following specifications apply for +4.25 VDC ≤VCC ≤ +5.75 VDC ,fSYSCLK = 8.33 MHz, RS =2 5Ω , unless otherwise speci- fied.Boldface limits apply for TA =T J =T MIN to TMAX ;all other limits TA =T J = 25˚C. (Note 7) Symbol Parameter Conditions Typical Limits Units (Note 8) (Note 9) (Limits) FAN RPM-TO-DIGITAL CONVERTER FAN1 and FAN2 Nominal Input RPM (See Section 6.0) Divisor = 1, Fan Count = 153 (Note 12)

8800 RPM

Divisor = 2, Fan Count = 153 (Note 12)

4400 RPM

Divisor = 3, Fan Count = 153 (Note 12)

2200 RPM

Divisor = 4, Fan Count = 153 (Note 12)

1100 RPM

FAN3 Design Nominal Input RPM Fan Count = 153 (Note 12) 4400 RPM Internal Clock Frequency +25˚C ≤ TA ≤ +75˚C 22.5 20.2 kHz (min) 24.8 kHz (max) −10˚C ≤ TA ≤ +100˚C 22.5 19.1 kHz (min) 25.9 kHz (max) DIGITAL OUTPUTS (VID4/NTEST, NMI/IRQ) VOUT(1) Logical “1” Output Voltage I OUT = ±5.0 mA 2.4 V (min) VOUT(0) Logical “0” Output Voltage I OUT = ±5.0 mA 0.4 V (max) ISA D0–D7 DIGITAL OUTPUTS V OUT(1) Logical “1” Output Voltage I OUT = ±12.0 mA 2.4 V (min) VOUT(0) Logical “0” Output Voltage I OUT = ±12.0 mA 0.4 V (max) IOUT TRI-STATE ® Output Current V OUT =0V DC 0.005 1 µA (max) VOUT =V CC −0.005 −1 µA (min) OPEN DRAIN DIGITAL OUTPUTS (Power Switch Bypass, SDA, RESET, SMI, Chassis Intrusion) VOUT(0) Logical “0” Output Voltage I OUT = −5.0 mA 0.4 V (min) IOH High Level Output Current V OUT =V CC 0.1 100 µA (max) RESET and Chassis Intrusion 45 20 ms (min) Pulse Width DIGITAL INPUTS: SMI__IN, VID0–VID3, VID4/NTEST, BTI, CS, A0, A1, A2, Mode Control and Interface Inputs (IORD, IOWR, SYSCLK), Data Lines (D0–D7), Chassis Intrusion, and Tach Pulse Logic Inputs (FAN1, FAN2, FAN3) V IN(1) Logical “1” Input Voltage 2.0 V (min) VIN(0) Logical “0” Input Voltage 0.8 V (max) SERIAL BUS DIGITAL INPUTS (SCL, SDA) V IN(1) Logical “1” Input Voltage 0 . 7xVCC V (min) VIN(0) Logical “0” Input Voltage 0 . 3xVCC V (max) ALL DIGITAL INPUTS EXCEPT FOR BTI IIN(1) Logical “1” Input Current V IN =V CC −0.005 −1 µA (min) IIN(0) Logical “0” Input Current V IN =0V DC 0.005 1 µA (max) C IN Digital Input Capacitance 20 pF BIT DIGITAL INPUT IIN(1) Logical “1” Input Current V IN =V CC 1 10 µA (max) IIN(0) Logical “0” Input Current V IN =0V DC −500 −2000 µA (max) C IN Digital Input Capacitance 20 pF LM79 www.national.com 6

FIGURE 1. ISA Bus Write Timing Diagram

FIGURE 2. ISA Bus Read Timing Diagram

Note 3:When the input voltage (VIN) at any pin exceeds the power supplies (VIN< (GNDD or GNDA) or VIN >VCC ), the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four. allowable power dissipation at any temperature is PD =( TJmax−T A)/θJA. FIGURE 3. Serial Bus Timing Diagram

1.0 GENERAL DESCRIPTION

circuitry is included to accommodate slow rise and fall times. Figure 6. These include:

• Configuration Register: Provides control and con- figuration.
• Interrupt Status Registers:Two registers to provide status of each WATCHDOG limit or Interrupt event.
• Interrupt Mask Registers: Allows masking of indi- vidual Interrupt sources, as well as separate masking for each of both hardware Interrupt outputs.
• VID/Fan Divisor Registers: A register to read the status of the VID0-VID3 input lines. The high bits of this register contain the divisor bits for FAN1 and FAN2 in- puts.
• Serial Bus Address Register: Contains the Serial Bus address. At power on it assumes the default value of 0101101 binary, and can be altered via the ISA or Serial Bus interface.
• Chip Reset/VID4/Device ID Register:Allows resetting of all the registers to the default power-on reset value. The state of VID4 is reflected in this register. The identity of the divice being used can be determined by reading the state of the D7 of this register. An LM79 would be identified when D7 is set high.
• POST RAM: FIFO RAM to store up to 32 bytes of 8-bit POST codes. Overflow of the POST RAM will set an Interrupt. The POST RAM, located at base address x0h and x4h, allows for easy decoding to address 80h and 84h, the normal addresses for outputting of POST codes. Interrupt will only be set when writing to port x0h or x4h. The POST RAM can be read via ports 85h and 86h.
• Value RAM: The monitoring results: temperature, volt- ages, fan counts, and WATCHDOG limits are all con- tained in the Value RAM. The Value RAM consists of a total of 64 bytes. The first 11 bytes are all of the results, the next 19 bytes are the WATCHDOG limits, and are located at 20h-3Fh, including two unused bytes in the upper locations. The next 32 bytes, located at 60h-7Fh, mirror the first 32 bytes with identical contents. The only difference in the upper bytes are that they auto-increment the LM79 Internal Address Register when read from or written to via the ISA bus (auto-increment is not available for Serial Bus communications). When the LM79 is started, it cycles through each measure- ment in sequence, and it continuously loops through the sequence approximately once every second. Each mea- sured value is compared to values stored in WATCHDOG, or Limit registers. When the measured value violates the pro- grammed limit the LM79 will set a corresponding Interrupt in the Interrupt Status Registers. Two hardware Interrupt lines, SMI and NMI/IRQ, are fully programmable with separate masking of each Interrupt source, and masking of each output. In addition, the Configuration Register has control bits to enable or disable the hardware Interrupts. Additional digital inputs are provided for chaining of SMI (System Management Interrupt), outputs of multiple external LM75 temperature sensors via the BTI (Board Temperature Interrupt) input, and a Chassis Intrusion input. The Chassis DS100036-8

FIGURE 5. Digital Output Load Circuitry

Functional Description(Continued) Intrusion input is designed to accept an active high signal from an external circuit that latches when the case is re- moved from the computer.

2.0 INTERFACE

The LM79 only decodes the three lowest address bits on the ISA bus. Referring to the ISA bus timing diagrams in and , the Chip Select Input, CS, should be taken low by external address decoder circuitry to access the LM79. The LM79 decodes the following base addresses: -Port x0h: Power On Self Test codes from ISA bus. -Port x4h: Power On Self Test codes from ISA bus. -Port x5h: The LM79s Internal Address Register -Port x6h: Data Register IORD is the standard ISA bus signal that indicates to the LM79 that it may drive data on to the ISA data bus. IOWR is the standard ISA command to the LM79 that it may latch data from the ISA bus. SYSCLK is the standard ISA SYSCLK, typically 8.33 MHz. This clock is used only for timing of the ISA interface of the LM79. All other clock functions within LM79 such as the ADC and fan counters are done with a separate asynchronous internal clock. A typical application designed to utilize the POST RAM would decode the LM79 to the address space starting at 80h, which is where POST codes are output to. Otherwise, the LM79 can be decoded into a different desired address space. To communicate with an LM79 Register, first write the ad- dress of that Register to Port x5h. Read or write data from or to that register via Port x6h. A write will take IOWR low, while a read will take IORD low. If the Serial Bus Interface and ISA bus interface are used simultaneously there is the possibility of collision. To prevent this from occurring in applications where both interfaces are used, read port x5h and if the Most Significant Bit, D7, is high, ISA communication is limited to reading port x5h only until this bit is low. A Serial Bus communication occurring while ISA is active will not be a problem, since even a single bit of Serial Bus communication requires 10 microseconds, in comparison to less than a microsecond for an entire ISA communication. LM79 www.national.com 12

FIGURE 6. LM79 Register Structure

2.1 Internal Registers of the LM79

TABLE 1. The internal registers and their corresponding internal LM79 address is as follows: Register 2 after a read or write to Port x6h. Register 2 after a read or write to Port x6h. Register 2 after a read or write to Port x6h. state of the VID0-VID3 inputs. stops when address 1Fh is reached. Value RAM 60h-7Fh Auto-increment after a read or write to Port x6h.

1. Write to Port x5h the LM79 Internal Address (from col-

with an Serial Bus communication.

1. Read or write the corresponding registers data with

2.2 Serial Bus Interface

1. If the Internal Address Register is known to be at the
2. If the Internal Address Register value is unknown, write

data byte read from the LM79. Bus communications as it does for ISA communications. situation should be limited to reading port x5h only. FIGURE 7. Serial Bus Timing

Functional Description(Continued)

3.0 USING THE LM79

3.1 Power On

When power is first applied, the LM79 performs a “power on reset” on several of its registers. The power on condition of registers in shown in Table I. Registers whose power on values are not shown have power on conditions that are indeterminate (this includes the value RAM and WATCH- DOG limits). The ADC is inactive. In most applications, usu- ally the first action after power on would be to write WATCH- DOG limits into the Value RAM.

3.2 Resets

Configuration Register INITIALIZATION accomplishes the same function as power on reset on most registers. The POST RAM, Value RAM conversion results, and Value RAM WATCHDOG limits are not Reset and will be indeterminate immediately after power on. If the Value RAM contains valid conversion results and/or Value RAM WATCHDOG limits have been previously set, they will not be affected by a Configuration Register INITIALIZATION. Power on reset, or Configuration Register INITIALIZATION, clear or initialize the following registers (the initialized values are shown on Table 1):

• Configuration Register
• Interrupt Status Register 1
• Interrupt Status Register 2
• SMI Mask Register 1
• SMI Mask Register 2
• NMI Mask Register 1
• NMI Mask Register 2
• VID/Fan Divisor Register
• Serial Bus Address Register (Power on reset only, not reset by Configuration Register INITIALIZATION) Configuration Register INITIALIZATION is accomplished by setting Bit 7 of the Configuration Register high. This bit automatically clears after being set. The LM79 allows the user to perform an unconditional com- plete Power-on reset by writing a one to Bit 5 of the Chip Reset/VID4/Device ID Register. The LM79 allows an uncon- ditional complete Power-on reset to be initiated by taking the IOWR and IORD signal lines low simultaneously, for at least 50 ns, while CS is high. The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that an Power-on reset does not occur unintention- ally. In systems where the serial bus is only being used it may be advantageous to take both IOWR and IORD to the system reset pulse. In this way whenever the system is reset the LM79 will also be reset to its initial Power-on state.

3.3 Using the Configuration Register

The Configuration Register provides all control over the LM79. At power on, the ADC is stopped and INT__Clear is asserted, clearing the SMI and NMI/IRQ hardwire outputs. The Configuration Register starts and stops the LM79, en- ables and disables interrupt outputs and modes, and pro- vides the Reset function described in Section 3.2. Bit 0 of the Configuration Register controls the monitoring loop of the LM79. Setting Bit 0 low stops the LM79 monitor- ing loop and puts the LM79 in shutdown mode, reducing power consumption. ISA and Serial Bus communication is possible with any register in the LM79 although activity on these lines will increase shutdown current, up to as much as maximum rated supply current, while the activity takes place. Taking Bit 0 high starts the monitoring loop, described in more detail subsequently. Bit 1 of the Configuration Register enables the SMI Interrupt hardwire output when this bit is taken high. Similarly, Bit 2 of the Configuration Register enables the NMI/IRQ Interrupt hardwire output when taken high. The NMI/IRQ mode is determined by Bit 5 in the Configuration Register. When Bit 5 is low the output is an active low IRQ output. Taking Bit 5 high inverts this output to provide an active high NMI output. The Power Switch Bypass provides an active low at the open drain Power Switch Bypass output when set high. This is intended for use in software power control by activating an external power control MOSFET.

3.4 Starting Conversion

The monitoring function (Analog inputs, temperature, and fan speeds) in the LM79 is started by writing to the Configu- ration Register and setting INT__Clear (Bit 3), low, and Start (bit 0), high. The LM79 then performs a “round-robin” moni- toring of all analog inputs, temperature, and fan speed inputs approximately once a second. The sequence of items being monitored corresponds to locations in the Value RAM and is: 1. Temperature 2. IN0 3. IN1 4. IN2 5. IN3 6. IN4 7. -IN5 8. -IN6 9. Fan 1 10. Fan 2 11. Fan 3

3.5 Reading Conversion Results

The conversion results are available in the Value RAM. Conversions can be read at any time and will provide the result of the last conversion. Because the ADC stops, and starts a new conversion whenever it is read, reads of any single value should not be done more often then once every 120 ms. When reading all values, allow at least 1.5 seconds between reading groups of values. Reading more frequently than once every 1.5 seconds can also prevent complete updates of Interrupt Status Registers and Interrupt Output’s. A typical sequence of events upon power on of the LM79 would consist of: 1. Set WATCHDOG Limits 2. Set Interrupt Masks 3. Start the LM79 monitoring process

4.0 ANALOG INPUTS

The 8-bit ADC has a 16 mV LSB, yielding a 0V to 4.08V (4.096–1LSB) input range. This is true for all analog inputs. In PC monitoring applications these inputs would most often be connected to power supplies. The 2.5V and 3.3V supplies can be directly connected to the inputs. The 5V and 12V inputs should be attenuated with external resistors to any desired value within the input range. LM79 www.national.com 16

IN is from 30 kΩ to 300 kΩ . analog input has no detrimental effect on other channels.

5.0 LAYOUT AND GROUNDING

physically as close as possible to the LM79. be located as close as possible to the LM79.

6.0 FAN INPUTS

Figure 9. R2 is selected so zener diode to clamp the input level. resistors connected in series with the fan inputs. pulse per revolution with a nominal RPM of 4400.

FIGURE 8. Input Examples. Resistor Values Shown Provide Approximately 3V at the Analog Inputs

Counts are based on 2 pulses per revolution tachometer outputs. FIGURE 9. Alternatives for Fan Inputs

7.0 TEMPERATURE MEASUREMENT SYSTEM

setpoint and Hysteresis values.

7.1 Temperature Data Format

7.2 Temperature Interrupts

being reset by reading Interrupt Status Register 1. OI while in Comparator mode). FIGURE 10. Temperature-to-Digital Transfer Function *Note:Interrupt resets occur only when interrupt Status Register 1 is read. loops before the Temperature Interrupt resets. FIGURE 11. Temperature Interrupt Response Diagram

8.0 THE LM79 INTERRUPT STRUCTURE

bytes written to POST RAM) will also cause an Interrupt.

• BTI: This is an active low Interrupt intended to come from the O.S. output of LM75 temperature sensors. The LM75 O.S. output goes active when its temperature ex- ceeds a programmed threshold. Up to 8 LM75’s can be connected to a single Serial Bus bus with their O.S. output’s wire or’d to the BTI input of the LM79. If the temperature of any LM75 exceeds its programmed limit, it drives BTI low. This generates an Interrupt to notify the host of a possible overtemperature condition. Provides an internal pull-up of 10 kΩ . DS100036-21

FIGURE 12. Interrupt Structure

Functional Description(Continued)

• Chassis Intrusion:This is an active high interrupt from any type of device that detects and captures chassis intrusion violations. This could be accomplished me- chanically, optically, or electrically, and circuitry external to the LM79 is expected to latch the event. The design of the LM79 allows this input to go high even with no power applied to the LM79, and no clamping or other interfer- ence with the line will occur. This line can also be pulled low for at least 20 ms by the LM79 to reset a typical Chassis Intrusion circuit. Accomplish this reset by setting Bit 7 of NMI Mask Register 2 high. The bit in the Register is self-clearing.
• SMI__IN: This active low Interrupt merely provides a way to chain the SMI Interrupt from other devices through the LM79 to the processor. All Interrupts are indicated in the two Interrupt Status Reg- isters. The NMI/IRQ and SMI outputs have individual mask registers, and individual masks for each Interrupt. As de- scribed in Section 3.3, these two hardware Interrupt lines can also be enabled/disabled in the Configuration Register. The Configuration Register is also used to set the mode of the NMI/IRQ Interrupt line.

8.1 Interrupt Clearing

Reading the Interrupt Status Register will output the con- tents of the Register, and reset the Register. A subsequent read done before the analog “round-robin” monitoring loop is complete will indicate a cleared Register. Allow at least 1.5 seconds to allow all Registers to be updated between reads. In summary, the Interrupt Status Register clears upon being read, and requires at least 1.5 seconds to be updated. When the Interrupt Status Register clears, the hardware interrupt line will also clear until the Registers are updated by the monitoring loop. The hardware Interrupt lines are cleared with the INT__Clear bit, which is Bit 3 of the Configuration Register. When this bit is high, the LM79 monitoring loop will stop. It will resume when the bit is low.

9.0 RESET AND Power Switch Bypass OUTPUTS

In PC applications the open drain Power Switch Bypass provides a gate drive signal to an external P-channel MOS- FET power switch. This external MOSFET then would keep power turned on regardless of the state of front panel power switches when software power control is used. In any given application this signal is not limited to the function described by its label. For example, since the LM79 incorporates tem- perature sensing, the Power Switch Bypass output could also be utilized to control power to a cooling fan. Take Power Switch Bypass active low by setting Bit 6 in the Configuration Register high. RESET is intended to provide a master reset to devices connected to this line. SMI Mask Register 2, Bit 7, must be set high to enable this function. Setting Bit 4 in the Configu- ration Register high outputs a least 20 ms low on this line, at the end of which Bit 4 in the Configuration Register automati- cally clears. Again, the label for this pin is only its suggested use. In applications where the RESET capability is not needed it can be used for any type of digital control that requires a 20 ms active low open drain output.

10.0 POST RAM

The POST RAM is located at address x0h and x4h, which typical address decoders will decode to 80h or 84h, where the BIOS will output Power On Self Test codes. A write to the POST RAM auto-increments the internal pointer of the LM79. Up to 32 bytes may be stored. An excess of 32 bytes will generate an Interrupt and stop incrementing. The POST RAM is read as like any other register at Ports x5h and x6h, with the POST RAM located at the LM79 Internal Address from 00h to 1Fh. Reading the POST RAM via x6h will also auto-increment, but this is a separate pointer than the one used for ports 80h and 84h.

11.0 NAND TREE TESTS

A NAND tree is provided in the LM79 for Automated Test Equipment (ATE) board level connectivity testing. NAND tree tests are accomplished after power on reset when the Con- figuration Register is in reset state, with the Start Bit, Bit 0 of the Configuration Register low, and the INT__Clear (Bit 3) high. In this mode, forcing the SMI output low before the first write to the configuration register takes all pins except Power Switch Bypass, RESET, -IN5, -IN6, VCC , GNDA, and GNDD to a high impedance (either TRI-STATE or open drain) state. All high impedance pins can then be taken to 0 and V CC to accomplish NAND tree tests. To perform a NAND tree test all pins included in the NAND tree should be driven to 1. Each individual pin (excluding the aforementioned exceptions) can be toggled and the resulting toggle observed on the NTEST pin. Allow for a typical propa- gation delay of 200 ns. LM79 www.national.com 22

Functional Description(Continued)

12.0 FAN MANUFACTURERS

Manufacturers of cooling fans with tachometer outputs are listed below: NMB Tech 9730 Independence Ave. Chatsworth, California 91311 818 341-3355 818 341-8207 Model Num- ber Frame Size Airflow CFM 2408NL 2.36 in sq. X 0.79 in 9-16 (60 mm sq. X 20 mm) 2410ML 2.36 in sq. X 0.98 in 14-25 (60 mm sq. X 25 mm) 3108NL 3.15 in sq. X 0.79 in 25-42 (80 mm sq. X 20 mm) 3110KL 3.15 in sq. X 0.98 in 25-40 (80 mm sq. X 25 mm) Mechatronics Inc. P.O. Box 20 Mercer Island, WA 98040 800 453-4569 Various sizes available with tach output option. Sanyo Denki America, Inc. 468 Amapola Ave. Torrance, CA 90501 310 783-5400 Model Number Frame Size Airflow CFM 109P06XXY601 2.36 in sq. X 0.79 in 11-15 (60 mm sq. X 20 mm) 109R06XXY401 2.36 in sq. X 0.98 in 13-28 (60 mm sq. X 25 mm) 109P08XXY601 3.15 in sq. X 0.79 in 23-30 (80 mm sq. X 20 mm) 109R08XXY401 3.15 in sq. X 0.98 in 21-42 (80 mm sq. X 25 mm) LM79 www.national.com23

Functional Description(Continued) REGISTERS AND RAM

13.1 Address Register (Port x5h)

The main register is the ADDRESS Register located at Port x5h. The bit designations are as follows: Bit Name Read/ Write

Description

Read/Write Address of RAM and Registers. See the tables below for detail.

7 Busy Read

A one indicates the device is busy because of a Serial Bus transaction or another ISA bus transaction. With checking this bit, multiple ISA drivers can use LM79 without interfering with each other or a Serial Bus driver. It is the user’s responsibility not to have a Serial Bus and ISA bus operations at the same time. This bit is: Set:with a write to Port x5h or when a Serial Bus transaction is in progress. Reset:with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus transaction is finished. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Busy Address Pointer (Power On default 00h) (Power On default 0) A6 A5 A4 A3 A2 A1 A0 Address Pointer Index (A6–A0) Registers and RAM A6–A0 in Hex Power On Value of Registers: Notes <7:0> in Binary Configuration Register 40h 0000 1000 Interrupt Status Register 1 41h 0000 0000 Auto-increment to the address of Interrupt Status Register 2 after a read or write to Port x6h. Interrupt Status Register 2 42h 0000 0000 SMI Mask Register 1 43h 0000 0000 Auto-increment to the address of SMI Mask Register 2 after a read or write to Port x6h. SMI Mask Register 2 44h 0000 0000 NMI Mask Register 1 45h 0000 0000 Auto-increment to the address of NMI Mask Register 2 after a read or write to Port x6h. NMI Mask Register 2 46h 0100 0000 VID/Fan Divisor Register 47h <7:4> = 0101; <3:0> = VID3–VID0 Serial Bus Address Register 48h 0010 1101 Chip Reset/VID4/Device ID Register 49h <7:1> =1100 000; <0> = VID4 D7 identifies this device as the LM79. D0 reflects the state of VID4. POST RAM 00–1Fh Auto-increment to the next location after a read or write to Port x6h and stop at 1Fh. Value RAM 20–3Fh Value RAM 60–7Fh Auto-increment to the next location after a read or write to Port x6h and stop at 7Fh. LM79 www.national.com 24

Functional Description(Continued)

13.2 Data Register (Port x6h)

Power on default<7:0> = 00h Bit Name Read/ Write 7–0 Data Read/Write Data to be read from or to be written to RAM and Register.

13.3 Configuration Register — Address 40h

Power on default<7:0> = 00001000 binary Bit Name Read/ Write 0 Start Read/Write A one enables startup of monitoring operations, a zero puts the part in standby mode. Note:The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike “INT__Clear” bit. 1 SMI Enable Read/Write A one enables the SMI Interrupt output.

2 NMI/IRQ

Read/Write A one enables the NMI/IRQ Interrupt output. 3 INT__Clear Read/Write A one disables the SMI and NMI/IRQ outputs without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit.

4 RESET Read/Write A one outputs at least a 20 ms active low reset signal at RESET if<7> = 1 in SMI

Mask Register 2. This bit is cleared once the pulse has gone inactive.

5 NMI/IRQ

Read/Write A one selects NMI, and a zero selects IRQ.

6 Power Switch

Read/Write A one in this bit drives a zero on open drain Power Switch Bypass pin. 7 INITIALIZATION Read/Write A one restores power on default value to all registersexcept the Serial Bus Address register. This bit clears itself since the power on default is zero. LM79 www.national.com25

Functional Description(Continued)

13.4 Interrupt Status Register 1 — Address 41h

Power on default<7:0> = 00h Bit Name Read/Write Description 0 IN0 Read Only A one indicates a High or Low limit has been exceeded. 1 IN1 Read Only A one indicates a High or Low limit has been exceeded. 2 IN2 Read Only A one indicates a High or Low limit has been exceeded. 3 IN3 Read Only A one indicates a High or Low limit has been exceeded. 4 Temperature Read Only A one indicates a High or Low limit has been exceeded.

5 BTI

Read Only A one indicates an interrupt has occurred from the Board Temperature Interrupt (BTI) input (O.S. output of multiple LM75 chips). 6 FAN1 Read Only A one indicates the fan count limit has been exceeded. 7 FAN2 Read Only A one indicates the fan count limit has been exceeded.

13.5 Interrupt Status Register 2 — Address 42h

<7:0> = 00h Bit Name Read/Write Description 0 IN4 Read Only A one indicates a High or Low limit has been exceeded. 1 -IN5 Read Only A one indicates a High or Low limit has been exceeded. 2 -IN6 Read Only A one indicates a High or Low limit has been exceeded. 3 FAN3 Read Only A one indicates the fan count limit has been exceeded. 4 Chassis Intrusion Read Only A one indicates Chassis Intrusion has gone high. 5 FIFO Overflow Read Only A one indicates an overflow in FIFO (POST RAM) i.e. 32nd location in FIFO has been written via Port x0h or x4h.

6 SMI__IN

Read Only A one indicates SMI__IN has gone low.

7 Reserved Read Only

13.6 SMI Mask Register 1 — Address 43h

Power on default<7:0> = 00h Bit Name Read/ Write 0 IN0 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 1 IN1 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 2 IN2 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 3 IN3 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 4 Temperature Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 5 BTI Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 6 FAN1 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 7 FAN2 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. LM79 www.national.com 26

Functional Description(Continued)

13.7 SMI Mask Register 2 — Address 44h

Power on default<7:0> = 00h Bit Name Read/ Write 0 IN4 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 1 -IN5 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 2 -IN6 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 3 FAN3 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 4 Chassis Intrusion Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 5 FIFO Overflow Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 6 SMI__IN Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 7 RESET Enable Read/Write <7> = 1 in SM Mask Register 2 enables the RESET in the Configuration Register.

13.8 NMI Mask Register 1 — Address 45h

Power on default<7:0> = 00h Bit Name Read/ Write 0 IN0 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 1 IN1 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 2 IN2 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 3 IN3 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 4 Temperature Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 5 BTI Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 6 FAN1 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 7 FAN2 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.

13.9 NMI Mask Register 2 — Address 46h

Power on <7:0> = 01000000 binary Bit Name Read/ Write 0 IN4 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 1 -IN5 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 2 -IN6 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 3 FAN3 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 4 Chassis Intrusion Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 5 FIFO Overflow Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 6 SMI__IN Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. Note:The Power on default is1 for this bit. 7 Chassis Clear Read/Write A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The register bit self clears after the pulse has been output. LM79 www.national.com27

Functional Description(Continued)

13.10 VID/Fan Divisor Register — Address 47h

Power on –<7:4> is 0101, and<3:0>is mapped to VID<3:0> Bit Name Read/Write Description 3-0 VID <3:0> Read Only The VID <3:0> inputs 5-4 FAN1 RPM Control Read/Write FAN1 Speed Control. <5:4> = 00 - divide by 1; <5:4> = 01 - divide by 2; <5:4> = 10 - divide by 4; <5:4> = 11 - divide by 8. 7-6 FAN2 RPM Control Read/Write FAN2 Speed Control. <7:6> = 00 - divide by 1; <7:6> = 01 - divide by 2; <7:6> = 10 - divide by 4; <7:6> = 11 - divide by 8.

13.11 Serial Bus Address Register — Address 48h

Power on default Serial Bus address<6:0> = 0101101 and<7> = 0 binary Bit Name Read/Write Description 6-0 Serial Bus Address Read/Write Serial Bus address <6:0>

13.12 Chip Reset/VID4/Device ID Register Address 49h

Power on default for the latest version of LM79<7:0> = 1100 000X. Bit Name Read/Write Description

0 VID4 Read Only VID4 input

5 Chip Reset Read/Write A one will reset all the registers of the LM79 to the power on default state.

6 Reserved Read Only

7 Device ID Read Only LM79 device identification. The LM78 has <7> =0 .

13.13 POST RAM — Address 00h–1Fh

The address pointer for the POST RAM auto-increments when written to at Port x0h or x4h. Once the address pointer reaches 1Fh, a FIFO overflow interrupt will be generated and the FIFO will stop incrementing. Normal reads via Port x5h and x6h auto-increment a separate pointer, and will not cause a FIFO overflow interrupt.

13.14 Value RAM — Address 20h–3Fh or 60h–7Fh (auto-increment)

Address A6–A0 Address A6–A0 with Auto-Increment Description 20h 60h IN0 reading 21h 61h IN1 reading 22h 62h IN2 reading 23h 63h IN3 reading 24h 64h IN4 reading 25h 65h -IN5 reading 26h 66h -IN6 reading 27h 67h Temperature reading 28h 68h FAN1 reading LM79 www.national.com 28

Functional Description(Continued) Address A6–A0 Address A6–A0 with Auto-Increment Description Note:This location stores the number of counts of the internal clock per revolution. 29h 69h FAN2 reading Note:This location stores the number of counts of the internal clock per revolution. 2Ah 6Ah FAN3 reading Note:This location stores the number of counts of the internal clock per revolution. 2Bh 6Bh IN0 High Limit 2Ch 6Ch IN0 Low Limit 2Dh 6Dh IN1 High Limit 2Eh 6Eh IN1 Low Limit 2Fh 6Fh IN2 High Limit 30h 70h IN2 Low Limit 31h 71h IN3 High Limit 32h 72h IN3 Low Limit 33h 73h IN4 High Limit 34h 74h IN4 Low Limit 35h 75h -IN5 High Limit 36h 76h -IN5 Low Limit 37h 77h -IN6 High Limit 38h 78h -IN6 Low Limit 39h 79h Over Temperature Limit (High) 3Ah 7Ah Temperature Hysteresis Limit (Low) 3Bh 7Bh FAN1 Fan Count Limit Note:It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Ch 7Ch FAN2 Fan Count Limit Note:It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Dh 7Dh FAN3 Fan Count Limit Note:It is the number of counts of the internal clock for the Low Limit of the fan speed. 3E–3Fh 7E–7Fh Reserved Note:Setting all ones to the high limits for voltages and fans (01111111binary for temperature) means interrupts willnever be generated except the case when voltages go below the low limits. For voltage input high limits, the device is doing a greater than comparison. For low limits, however, it is doing a less than or equal to comparison. LM79 www.national.com29

FIGURE 13. In this PC application the LM79 monitors temperature, fan speed for 3 fans, and 7 power as an optical chassis intrusion detector.

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com 44-Lead (10 mm x 10 mm) Molded Plastic Quad Flatpak Order Number LM79CCVF LM79 Microprocessor System Hardware Monitor National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.