LM6511 TI | Alldatasheet
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www.ti.com SNOS695C –JUNE 1999–REVISED MARCH 2013 LM6511180ns3VComparator Check forSamples: LM6511 1FEATURES DESCRIPTION The LM6511 voltagecomparatorisidealforanalog- 2• (TypicalUnless OtherwiseNoted) digitalinterfacecircuitrywhen onlya +3V or +3.3V• Operates at+2.7V,+3V, +3.3V,+5V supplyisavailable.The open-collectoroutputpermits
- Low Power Consumption <9.45mW @ V+ = signalcompatibilitywith a wide varietyof digital 2.7V(max) families:+5V CMOS, +3V CMOS, TTL and so on. Supplyvoltagemay rangefrom2.7V to36V between• FastResponse Time of180 ns supplyvoltageleads.The LM6511 operateswithlittle power consumption(Pdiss < 9.45 mW at V+ = +2.7VAPPLICATIONS and V− = 0V).
- PortableEquipment Thisvoltagecomparatoroffersmany featuresthatare• CellularPhones availableintraditionalsub-microsecondcomparators:
- DigitalLevelShifting outputsync strobe,inputsand outputmay be isolated from system ground, and wire-ORing.Also, the LM6511 uses the industry-standard,single comparatorpinoutconfiguration. Connection Diagram Figure1. 8-PinSOIC See Package Number D These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNOS695C –JUNE 1999–REVISED MARCH 2013 www.ti.com AbsoluteMaximum Ratings(1)(2) SupplyVoltage −0.3to+36V OutputtoNegativeSupplyVoltage 50V Ground toNegativeSupplyVoltage 30V DifferentialInputVoltage ±30V InputVoltage See (1) StorageTemperatureRange −65°C to+150°C SolderingInformation: SOIC Package (VaporPhase in60 sec) 215°C Power Dissipation 500 mW OutputShortCircuitDuration 10s JunctionTemperature 150°C ESD Rating(C = +100 pF,R = 1.5kΩ) 300V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Operatingratingsindicateconditionsthe deviceisintendedtobe functional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand testconditions, see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. OperatingRatings(1) SupplyVoltage 2.5Vto30V TemperatureRange −40°C ≤ TJ ≤ +85°C ThermalResistance(θJA) SOIC Package 170°C/W (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Operatingratingsindicateconditionsthe deviceisintendedtobe functional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand testconditions, see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted. DC ElectricalCharacteristics Unlessotherwisespecified,alllimitsguaranteedforTJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 2.7V, V− = 0V,50Ω ≤ R L ≤ 50kΩ,and IL = 1.0mA unlessotherwisespecified Symbol Parameter Conditions Typical LM6511I Units (Limits)Limit VOS OffsetVoltage R S ≤ 50 kΩ(1) 1.5 5 mV 8 max IB InputBiasCurrent 38 130 nA max200 IOS InputOffsetCurrent R S ≤ 50 kΩ(1) 1.5 20 nA max50 IS PositiveSupplyCurrent 2.7 3.5 5 mA maxNegativeSupplyCurrent 1.5 2.0 2.5 VSAT SaturationVoltage VIN ≤ 10 mV 0.23 0.4 V ISINK = 8 mA 0.4 max AV LargeSignalVoltageGain ΔVOUT = 2V 40 V/mV CMRR Common Mode RejectionRatio 72 dB ISTROBE StrobeON Current See (2) 2.0 5.0 mA max (1) The offsetvoltageand offsetcurrentlimitsarethemaximum valuesrequiredtodrivetheoutputwithina voltofeithersupplywitha 1 mA load.Therefore,theseparametersdefinean errorband and takeintoaccounttheworst-caseeffectsofvoltagegainand input impedance. (2) Thisspecificationgivestherangeofcurrentwhichmust be drawn fromthestrobepintoensuretheoutputisproperlydisabled.Do not shortthestrobepintoground;itshouldbe currentdrivenat3 mA to5 mA.
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www.ti.com SNOS695C –JUNE 1999–REVISED MARCH 2013 DC ElectricalCharacteristics(continued) Unlessotherwisespecified,alllimitsguaranteedforTJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 2.7V, V− = 0V,50Ω ≤ R L ≤ 50kΩ,and IL = 1.0mA unlessotherwisespecified Symbol Parameter Conditions Typical LM6511I Units (Limits)Limit VIN InputVoltageRange 0.50 V min V+ − 1.25 V max OutputLeakage Current VIN ≥ 10 mV, VOUT = 35V, nA0.2ISTROBE = 3 mA max AC ElectricalCharacteristics Unlessotherwisespecified,alllimitsguaranteedforTJ = 25°C. Boldfacelimitsapplyatthetemperatureextremes.V+ = 2.7V, V− = 0V,50Ω ≤ R L ≤ 50kΩ,and IL = 1.0mA unlessotherwisespecified Symbol Parameter Conditions Typical LM6511I Units (Limits)Limit TR Response Time See (1) 180 ns (1) Thisspecificationisfora 100 mV inputstepwitha 25 mV overdrive. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM6511
SNOS695C –JUNE 1999–REVISED MARCH 2013 www.ti.com LM6511 TypicalPerformance Characteristics VS = 3V unlessotherwisenoted InputBias Current InputOffsetCurrent Figure2. Figure3. InputCurrent vs.InputVoltage Common Mode Limits Figure4. Figure5. TransferFunction Output SaturationVoltage Figure6. Figure7.
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www.ti.com SNOS695C –JUNE 1999–REVISED MARCH 2013 LM6511 TypicalPerformance Characteristics(continued) VS = 3V unlessotherwisenoted Supply Current Output CurrentLimiting vs.Temperature Figure8. Figure9. PropagationDelay Output Leakage Current vs.Overdrive Figure10. Figure11. TypicalApplication Notes:Because oftheverywideoperatingand outputvoltagerange,theLM6511 may be used toshiftlogiclevels from3V toTTL orCMOS totheotherway around.By biasingtheinputto½ oftheinputlogicsupply(VA),this assuresthatthisinputremainswithintheinputvoltagerange.The pull-upresistorshouldgo totheoutputlogicsupply (VB). Figure12. UniversalLogic LevelShifter Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM6511
SNOS695C –JUNE 1999–REVISED MARCH 2013 www.ti.com Schematic Diagram
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www.ti.com SNOS695C –JUNE 1999–REVISED MARCH 2013
REVISION HISTORY
Changes from RevisionB (March 2013)toRevisionC Page Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM6511
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM6511IM Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 LM65 11IM LM6511IM/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LM65 11IM LM6511IM/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LM65 11IM LM6511IMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM65 11IM LM6511IMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM65 11IM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM6511IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM6511IM/NOPB D SOIC 8 95 495 8 4064 3.05 LM6511IM/NOPB.B D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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