LMC6482 NSC | Alldatasheet
Document overview
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Technical content
Features
(Typical unless otherwise noted) n Rail-to-Rail Input Common-Mode Voltage Range (Guaranteed Over Temperature) n Rail-to-Rail Output Swing (within 20 mV of supply rail, 100 kΩ load) n Guaranteed 3V, 5V and 15V Performance n Excellent CMRR and PSRR: 82 dB n Ultra Low Input Current: 20 fA n High Voltage Gain (RL = 500 kΩ ): 130 dB n Specified for 2 kΩ and 600Ω loads n Available in MSOP Package
Applications
n Data Acquisition Systems n Transducer Amplifiers n Hand-held Analytic Instruments n Medical Instrumentation n Active Filter, Peak Detector, Sample and Hold, pH Meter, Current Source n Improved Replacement for TLC272, TLC277 3V Single Supply Buffer Circuit Connection Diagram Rail-To-Rail Input DS011713-1 DS011713-2 Rail-To-Rail Output DS011713-3 DS011713-4 November 1997 LMC6482 CMOS Dual Rail-To-Rail Input and Output Operational Amplifier © 1999 National Semiconductor Corporation DS011713 www.national.com
Ordering Information
Package Temperature Range NSC Drawing Transport Media Package Marking Military Industrial −55˚C to +125˚C −40˚C to +85˚C 8-Pin LMC6482MN LMC6482AIN, N08E Rail LMC6482MN, Molded DIP LMC6482IN LMC6482AIN, LMC6482IN 8-pin LMC6482AIM, M08A Rail LMC6482AIM, LMC6482IM Small Outline LMC6482IM Tape and Reel 8-pin LMC6482AMJ/883 J08A Rail LMC6482AMJ/883Q5962-9453401MPA Ceramic DIP 8-pin LMC6482IMM MUA08A Rail A10 Mini SO Tape and Reel www.national.com 2
Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) 1.5 kV Differential Input Voltage ±Supply Voltage Voltage at Input/Output Pin (V +) +0.3V, (V−) −0.3V Supply Voltage (V+ −V −) 16V Current at Input Pin (Note 12) ±5m A Current at Output Pin (Notes 3, 8) ±30 mA Current at Power Supply Pin 40 mA Lead Temperature (Soldering, 10 sec.) 260˚C Storage Temperature Range −65˚C to +150˚C Junction Temperature (Note 4) 150˚C Operating Ratings(Note 1) Supply Voltage 3.0V ≤ V+ ≤ 15.5V Junction Temperature Range LMC6482AM −55˚C ≤ TJ ≤ +125˚C LMC6482AI, LMC6482I −40˚C ≤ TJ ≤ +85˚C Thermal Resistance (θJA) N Package, 8-Pin Molded DIP 90˚C/W M Package, 8-Pin Surface Mount 155˚C/W MSOP package, 8-Pin Mini SO 194˚C/W Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (Note 5) LMC6482AI LMC6482I LMC6482M Units Limit Limit Limit (Note 6) (Note 6) (Note 6) VOS Input Offset Voltage 0.11 0.750 3.0 3.0 mV 1.35 3.7 3.8 max TCV OS Input Offset Voltage 1.0 µV/˚C Average Drift I B Input Current (Note 13) 0.02 4.0 4.0 10.0 pA max IOS Input Offset Current (Note 13) 0.01 2.0 2.0 5.0 pA max C IN Common-Mode 3 pF Input Capacitance R IN Input Resistance >10 Tera Ω CMRR Common Mode 0V ≤ VCM ≤ 15.0V 82 70 65 65 dB minRejection Ratio V + = 15V 67 62 60 0V ≤ VCM ≤ 5.0V 82 70 65 65 V+ = 5V 67 62 60 +PSRR Positive Power Supply 5V ≤ V+ ≤ 15V, V− = 0V 82 70 65 65 dB Rejection Ratio V O = 2.5V 67 62 60 min −PSRR Negative Power Supply −5V ≤ V− ≤ −15V, V+ = 0V 82 70 65 65 dB Rejection Ratio V O = −2.5V 67 62 60 min VCM Input Common-Mode V + = 5V and 15V V − − 0.3 − 0.25 − 0.25 − 0.25 V Voltage Range For CMRR ≥ 50 dB 000 max V+ V+ V+ min AV Large Signal R L = 2k Ω Sourcing 666 140 120 120 V/mV Voltage Gain (Notes 7, 13) 84 72 60 min Sinking 75 35 35 35 V/mV 20 20 18 min R L = 600Ω Sourcing 300 80 50 50 V/mV (Notes 7, 13) 48 30 25 min Sinking 35 20 15 15 V/mV 13 10 8 min www.national.com3
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (Note 5) LMC6482AI LMC6482I LMC6482M Units Limit Limit Limit (Note 6) (Note 6) (Note 6) VO Output Swing V + = 5V 4.9 4.8 4.8 4.8 V R L = 2k Ω to V+/2 4.7 4.7 4.7 min 0.1 0.18 0.18 0.18 V 0.24 0.24 0.24 max V+ = 5V 4.7 4.5 4.5 4.5 V R L = 600Ω to V+/2 4.24 4.24 4.24 min 0.3 0.5 0.5 0.5 V 0.65 0.65 0.65 max V+ = 15V 14.7 14.4 14.4 14.4 V R L = 2k Ω to V+/2 14.2 14.2 14.2 min 0.16 0.32 0.32 0.32 V 0.45 0.45 0.45 max V+ = 15V 14.1 13.4 13.4 13.4 V R L = 600Ω to V+/2 13.0 13.0 13.0 min 0.5 1.0 1.0 1.0 V 1.3 1.3 1.3 max ISC Output Short Circuit Sourcing, VO = 0V 20 16 16 16 mA Current 12 12 10 min V+ = 5V Sinking, V O = 5V 15 11 11 11 mA 9.5 9.5 8.0 min ISC Output Short Circuit Sourcing, VO = 0V 30 28 28 28 mA Current 22 22 20 min V+ = 15V Sinking, V O = 12V 30 30 30 30 mA (Note 8) 24 24 22 min IS Supply Current Both Amplifiers 1.0 1.4 1.4 1.4 mA Both Amplifiers 1.3 1.6 1.6 1.6 mA V + = 15V, VO = V+/2 1.9 1.9 2.0 max Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RL > 1M. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (Note 5) LMC6482AI LMC6482I LMC6482M Units Limit Limit Limit (Note 6) (Note 6) (Note 6) SR Slew Rate (Note 9) 1.3 1.0 0.9 0.9 V/µs 0.7 0.63 0.54 min GBW Gain-Bandwidth Product V + = 15V 1.5 MHz φm Phase Margin 50 Deg G m Gain Margin 15 dB Amp-to-Amp Isolation (Note 10) 150 dB e n Input-Referred F = 1 kHz 37 nV/ √Hz Voltage Noise V cm = 1V in Input-Referred F = 1 kHz 0.03 pA/ √Hz Current Noise www.national.com 4
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RL > 1M. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (Note 5) LMC6482AI LMC6482I LMC6482M Units Limit Limit Limit (Note 6) (Note 6) (Note 6) T.H.D. Total Harmonic Distortion F = 10 kHz, AV = −2 % R L = 10 kΩ ,V O = 4.1 VPP 0.01 F = 10 kHz, AV = −2 R L = 10 kΩ ,V O = 8.5 VPP 0.01 % V+ = 10V Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 3V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Symbol Parameter Conditions Typ (Note 5) LMC6482AI LMC6482I LMC6482M Units Limit Limit Limit (Note 6) (Note 6) (Note 6) VOS Input Offset Voltage 0.9 2.0 3.0 3.0 mV 2.7 3.7 3.8 max TCV OS Input Offset Voltage 2.0 µV/˚C Average Drift I B Input Bias Current 0.02 pA IOS Input Offset Current 0.01 pA CMRR Common Mode 0V ≤ VCM ≤ 3V 74 64 60 60 dB Rejection Ratio min PSRR Power Supply 3V ≤ V+ ≤ 15V, V− = 0V 80 68 60 60 dB Rejection Ratio min VCM Input Common-Mode For CMRR ≥ 50 dB V − −0.25 0 0 0 V Voltage Range max min VO Output Swing R L = 2k Ω to V+/2 2.8 V 0.2 V R L = 600Ω to V+/2 2.7 2.5 2.5 2.5 V min 0.37 0.6 0.6 0.6 V max IS Supply Current Both Amplifiers 0.825 1.2 1.2 1.2 mA 1.5 1.5 1.6 max Unless otherwise specified, V+ = 3V, V− = 0V, VCM = VO = V+/2, and RL > 1M. Symbol Parameter Conditions Typ (Note 5) LMC6482AI LMC6482I LMC6482M Units Limit Limit Limit (Note 6) (Note 6) (Note 6) SR Slew Rate (Note 11) 0.9 V/µs GBW Gain-Bandwidth Product 1.0 MHz T.H.D. Total Harmonic Distortion F = 10 kHz, A V = −2 0.01 % R L = 10 kΩ ,V O = 2V PP Note 1:Absolute Maximum Ratings indicate limts beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in- tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. www.national.com5
Note 3:Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of±30 mA over long term may adversely affect reliability. Note 4:The maximum power dissipation is a function of TJ(max),θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) −T A)/θJA. All numbers apply for packages soldered directly into a PC board. Note 5:Typical Values represent the most likely parametric norm. Note 6:All limits are guaranteed by testing or statistical analysis. Note 8:Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected. Note 9:V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of either the positive or negative slew rates. Note 10:Input referred, V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP . Note 11:Connected as voltage Follower with 2V step input. Number specified is the slower of either the positive or negative slew rates. Note 12:Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings. Note 13:Guaranteed limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value. Note 14:For guaranteed Military Temperature parameters see RETS6482X. Typical Performance CharacteristicsVS = +15V, Single Supply, TA = 25˚C unless otherwise specified Supply Current vs Supply Voltage DS011713-40 Input Current vs Temperature DS011713-41 Sourcing Current vs Output Voltage DS011713-42 Sourcing Current vs Output Voltage DS011713-43 Sourcing Current vs Output Voltage DS011713-44 Sinking Current vs Output Voltage DS011713-45 www.national.com 6
Typical Performance CharacteristicsVS = +15V, Single Supply, TA = 25˚C unless otherwise specified (Continued) Sinking Current vs Output Voltage DS011713-46 Sinking Current vs Output Voltage DS011713-47 Output Voltage Swing vs Supply Voltage DS011713-48 Input Voltage Noise vs Frequency DS011713-49 Input Voltage Noise vs Input Voltage DS011713-50 Input Voltage Noise vs Input Voltage DS011713-51 Input Voltage Noise vs Input Voltage DS011713-52 Crosstalk Rejection vs Frequency DS011713-53 www.national.com7
Typical Performance CharacteristicsVS = +15V, Single Supply, TA = 25˚C unless otherwise specified (Continued) Crosstalk Rejection vs Frequency DS011713-54 Positive PSRR vs Frequency DS011713-55 Negative PSRR vs Frequency DS011713-56 CMRR vs Frequency DS011713-57 CMRR vs Input Voltage DS011713-58 CMRR vs Input Voltage DS011713-59 CMRR vs Input Voltage DS011713-60 ΔVOS vs CMR DS011713-61 ΔVOS vs CMR DS011713-62 www.national.com 8
Typical Performance CharacteristicsVS = +15V, Single Supply, TA = 25˚C unless otherwise specified (Continued) Input Voltage vs Output Voltage DS011713-63 Input Voltage vs Output Voltage DS011713-64 Open Loop Frequency Response DS011713-65 Open Loop Frequency Responce DS011713-66 Open Loop Frequency Response vs Temperature DS011713-67 Maximum Output Swing vs Frequency DS011713-68 Gain and Phase vs Capacitive Load DS011713-69 Gain and Phase vs Capacitive Load DS011713-70 Open Loop Output Impedance vs Frequency DS011713-71 www.national.com9
Typical Performance CharacteristicsVS = +15V, Single Supply, TA = 25˚C unless otherwise specified (Continued) Open Loop Output Impedance vs Frequency DS011713-72 Slew Rate vs Supply Voltage DS011713-73 Non-Inverting Large Signal Pulse Response DS011713-74 Non-Inverting Large Signal Pulse Response DS011713-75 Non-Inverting Large Signal Pulse Response DS011713-76 Non-Inverting Small Signal Pulse Response DS011713-77 Non-Inverting Small Signal Pulse Response DS011713-78 Non-Inverting Small Signal Pulse Response DS011713-79 Inverting Large Signal Pulse Response DS011713-80 www.national.com 10
Typical Performance CharacteristicsVS = +15V, Single Supply, TA = 25˚C unless otherwise specified (Continued) Inverting Large Signal Pulse Response DS011713-81 Inverting Large Signal Pulse Response DS011713-82 Inverting Small Signal Pulse Response DS011713-83 Inverting Small Signal Pulse Response DS011713-84 Inverting Small Signal Pulse Response DS011713-85 Stability vs Capacitive Load DS011713-86 Stability vs Capacitive Load DS011713-87 Stability vs Capacitive Load DS011713-88 Stability vs Capacitive Load DS011713-89 www.national.com11
Typical Performance CharacteristicsVS = +15V, Single Supply, TA = 25˚C unless otherwise specified (Continued)
Application Information
1.0 Amplifier Topology
The LMC6482 incorporates specially designed wide-compliance range current mirrors and the body effect to extend input common mode range to each supply rail. Complementary paralleled differential input stages, like the type used in other CMOS and bipolar rail-to-rail input ampli- fiers, were not used because of their inherent accuracy prob- lems due to CMRR, cross-over distortion, and open-loop gain variation. The LMC6482’s input stage design is complemented by an output stage capable of rail-to-rail output swing even when driving a large load. Rail-to-rail output swing is obtained by taking the output directly from the internal integrator instead of an output buffer stage.
2.0 Input Common-Mode Voltage Range
Unlike Bi-FET amplifier designs, the LMC6482 does not ex- hibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 1shows an input voltage ex- ceeding both supplies with no resulting phase inversion on the output. The absolute maximum input voltage is 300 mV beyond ei- ther supply rail at room temperature. Voltages greatly ex- ceeding this absolute maximum rating, as in Figure 2, can cause excessive current to flow in or out of the input pins possibly affecting reliability. Applications that exceed this rating must externally limit the maximum input current to ±5 mA with an input resistor (RI) as shown inFigure 3.
3.0 Rail-To-Rail Output
The approximated output resistance of the LMC6482 is 180Ω sourcing and 130Ω sinking at Vs= 3V and 110Ω sourcing and 80Ω sinking at Vs= 5V. Using the calculated output resistance, maximum output voltage swing can be es- timated as a function of load.
4.0 Capacitive Load Tolerance
The LMC6482 can typically directly drive a 100 pF load with V S = 15V at unity gain without oscillating. The unity gain fol- lower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of op-amps. The combi- Stability vs Capacitive Load DS011713-90 Stability vs Capacitive Load DS011713-91 DS011713-10 FIGURE 1. An Input Voltage Signal Exceeds the FIGURE 2. A ±7.5V Input Signal Greatly FIGURE 3. RI Input Current Protection for
damped pulse response or oscillation. Figure 4. This simple tech-
5.0 Compensating for Input
which typically provides significant overcompensation. FIGURE 4. Resistive Isolation FIGURE 5. Pulse Response of FIGURE 6. LMC6482 Noninverting Amplifier, FIGURE 7. Pulse Response of FIGURE 8. Canceling the Effect of Input Capacitance
6.0 Printed-Circuit-Board Layout for High-Impedance
less than 20 fA, it is essential to have an excellent layout. effort of using point-to-point up-in-the-air wiring. FIGURE 9. Example of Guard Ring in P.C. Board FIGURE 10. Typical Connections of Guard Rings (Input pins are lifted out of PC board and soldered directly to components. FIGURE 11. Air Wiring
7.0 Offset Voltage Adjustment
Figure 13. Large value resistances and potentiometers are configurations with VS = ±5V.
8.0 Upgrading Applications
ter the input signal returns to the common mode range.
9.0 Data Acquisition Systems
FIGURE 12. Inverting Configuration FIGURE 13. Non-Inverting Configuration
10.0 Instrumentation Circuits
and silicon-based tranducers. Figure 15. This combination is used instead of one large val- Figure 16. Low sensitivity trimming is made FIGURE 14. Operating from the same FIGURE 15. Low Power 3 Op-Amp Instrumentation Amplifier
11.0 Spice Macromodel
- Input common-mode voltage range
- Frequency and transient response
- GBW dependence on loading conditions
- Quiescent and dynamic supply current
- Output swing dependence on loading conditions and many more characteristics as listed on the macromodel disk. Contact your local National Semiconductor sales office to obtain an operational amplifier spice model library disk. Typical Single-Supply Applications The circuit inFigure 17uses a single supply to half wave rec- tify a sinusoid centered about ground. RI limits current into the amplifier caused by the input voltage exceeding the sup- ply voltage. Full wave rectification is provided by the circuit in Figure 19. DS011713-30
FIGURE 16. Low-Power Two-Op-Amp Instrumentation Amplifier FIGURE 17. Half-Wave Rectifier FIGURE 18. Half-Wave Rectifier Waveform FIGURE 19. Full Wave Rectifier
Physical Dimensionsinches (millimeters) unless otherwise noted 8-Pin Ceramic Dual-In-Line Package Order Number LMC6482AMJ/883 8-Pin Small Outline Package Order Package Number LMC6482AIM or LMC6482IM www.national.com 20
Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) 8-Pin Molded Dual-In-Line Package Order Package Number LMC6482AIN, LMC6482IN or LMC6482MN www.national.com21
Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com 8-Lead Mini Small Outline Molded Package, JEDEC Order Number LMC6482IMM, or LMC6482IMMX LMC6482 CMOS Dual Rail-To-Rail Input and Output Operational Amplifier National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.