LM63610-Q1

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LM63610-Q1 3.5-V to 36-V, 1-A, Automotive Step-down Voltage Converter

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LM63610-Q1 3.5V to 36V, 1A, Automotive, Step-Down Voltage Converter datasheet (Rev. C)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SNVSBO7,C]
PDF pages: 52

Technical content

LM63610-Q1 3.5V to 36V, 1A, Automotive, Step-Down Voltage Converter

1 Features

AEC-Q100-qualified for automotive applications – Device temperature grade 1: –40°C to +125°C ambient operating temperature
Functional Safety-Capable – Documentation available to aid functional safety system design
Supports automotive system requirements – Input voltage range: 3.5V to 36V – Short minimum on-time of 50ns – Good performance Pseudo-random spread spectrum Compatible with CISPR 25 – Low operating quiescent current of 23µA – Junction temperature range –40°C to +150°C
High design flexibility – Pin selectable VOUT: 3.3V, 5V, adjustable 1V to 20V – Pin compatible with LM63615, LM63625, LM63635 (1.5A, 2.5A, and 3.25A) – Pin selectable frequency: 400kHz, 2.1MHz, adjustable 250kHz to 2200kHz – Pin selectable FPWM, AUTO, sync modes – TSSOP: thermally-enhanced package – WSON: for space-constrained applications
Small design size – Highly integrated design – Low component count

2 Applications

Automotive infotainment and cluster
Automotive body electronics and lighting
Automotive advance driver assistance systems (ADAS)

3 Description

The LM63610-Q1 regulators are a family of easy- to-use, synchronous, step-down DC/DC converters designed for rugged automotive applications. The LM63610-Q1 can drive up to 1A of load current from an input of up to 36V. The converter has high light load efficiency and output accuracy in a small design size. Features such as a RESET flag and precision enable provide both flexible and easy- to-use designs for a wide range of applications. Automatic frequency foldback at light load improves efficiency while maintaining tight load regulation. Integration eliminates many external components and provides a pinout designed for simple PCB layout. Protection features include thermal shutdown, input undervoltage lockout, cycle-by-cycle current limit, and hiccup short-circuit protection. The LM63610-Q1 is available in both the HTSSOP 16-pin power package, with PowerPAD™ integrated circuit package, and the WSON 12-pin power package. Please contact Texas Instruments for availability of the WSON package.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LM63610-Q1 PWP (HTSSOP, 16) 5.00mm × 6.4mm DRR (WSON, 12) 3.00mm × 3.00mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. VIN VIN EN CBOOT SW FB AGND VOUT CBOOT L1CIN COUT VCC RESET PGND CVCCRT VSEL SYNC/ MODE Simplified Schematic Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 eff_ 13.5V 18V 24V Typical Efficiency At 5V Vout, 2.1MHz LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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4 Device Comparison Table

OPTION SAMPLE ORDER NUMBER PACKAGE RATED CURRENT BODY SIZE (NOM) LM63610DQ See the orderable addendum at the end of the data sheet. PWP0016D (HTSSOP) 5.00mm × 4.00mm LM63610DQ DRR0012 (WSON) 3.00mm × 3.00mm www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LM63610-Q1

5 Pin Configuration and Functions

(17) Figure 5-1. PWP Package 16-Pin HTSSOP With PowerPAD™ Integrated Circuit Package (Top View) 3 10 PGND/DAP EN BOOT AGND VCC FB RT 12SW VIN 6 7

11 N/C

Figure 5-2. WSON Package 12-Pin DRR0012 With PowerPAD™ Integrated Circuit Package (Top View) LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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Table 5-1. Pin Functions PIN

DESCRIPTION

1, 2 1 SW P Regulator switch node. Connect to power inductor. 3 2 CBOOT P Boot-strap supply voltage for internal high-side driver. Connect a high-quality, 220nF capacitor from this pin to the SW pin. 4 3 VCC A Internal 5V LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for regulator functions. Connect a high- quality, 1µF capacitor from this pin to PGND. 5 4 RT A Frequency programming input. Tie to VCC for 400kHz; or to AGND for 2.1MHz or connect to an RT timing resistor. See the Switching Frequency Selection section for details. Do not float. 6 5 VSEL A Output voltage select input. Tie to VCC for 5V output or to AGND for 3.3V output; connect to a 10kΩ for an adjustable output. See the Output Voltage Selection section for details. Do not float. 7 6 SYNC/MODE A Mode selection and synchronization input. Tie to VCC for FPWM mode; or to AGND for AUTO mode; or supply an external synchronizing clock to this input. 8 7 RESET A Open drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be open when not used. 9 8 FB A Feedback input to regulator. Connect to output capacitor for 5V or 3.3V fixed option; or tap point of feedback voltage divider for ADJ option. Do not float; do not ground. 10 9 AGND G Analog ground for regulator and system. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB. 11 10 EN A Enable input to regulator. High = ON, Low = OFF. Can be connected directly to VIN. Do not float. 12, 13 12 VIN(1) P Input supply to regulator. Connect high-quality bypass capacitors directly to this pin and PGND. Make sure that a high-quality 220nF bypass capacitor is placed within 1mm of the VIN pin and within 1mm of the PGND pin. 14 11 NC — No internal connection to device 15, 16 13 PGND G Power ground terminal. Connect to system ground and AGND. Connect to bypass capacitor with short wide traces. A = Analog, P = Power, G = Ground (1) Input capacitor placement outside the recommended range can result in device performance degradation including, but not limited to, increased input voltage and switch-node ringing outside the absolute maximum rating, and instability. See Section 8.5.2 for a recommended layout example. www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM63610-Q1

6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended junction temperature range(1) PARAMETER MIN MAX UNIT VIN to PGND (HTSSOP package) –0.3 40 V VIN to PGND (WSON package) –0.3 42 V EN to AGND (HTSSOP package) –0.3 40 V EN to AGND (WSON package) –0.3 42 V SYNC/MODE to AGND –0.3 6 V VSEL and RT to AGND –0.3 5.5 V RESET to AGND –0.3 16 V FB to AGND (fixed VOUT mode) –0.3 16 V FB to AGND (adjustable VOUT mode) –0.3 5.5 V AGND to PGND –0.3 0.3 V SW to PGND for transients of less than 10ns (HTSSOP package) -6 40 V SW to PGND for transients of less than 10ns (WSON package) -6 42 V BOOT to SW –0.3 5.5 V VCC to AGND –0.3 5.5 V Temperature Junction temperature, TJ –40 150 °C Temperature Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±750 V (1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over the recommended junction temperature range of –40°C to 150°C (unless otherwise noted)(1) MIN MAX UNIT SYNC/MODE, VSEL, and RT to AGND 0 5 V RESET 0 5 V VOUT (2) 1 20 V VCC 2.7 5.25 V IOUT, LM63610 0 1 A (1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For specified specifications, see the Electrical Characteristics table. (2) Under no conditions can the output voltage be allowed to fall below zero volts. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) LM63610-Q1 LM63610-Q1 UNITDRR0012 (WSON) HTSSOP (PWP)

12 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance(2) 47.4 43.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 44.6 35.4 °C/W RθJB Junction-to-board thermal resistance 20.7 18.5 °C/W ΨJT Junction-to-top characterization parameter 0.7 0.9 °C/W ΨJB Junction-to-board characterization parameter 20.7 18.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.3 4.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. (2) The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. These values do not represent the performance obtained in an actual application. For design information please see the Maximum Ambient Temperature section. www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LM63610-Q1

6.5 Electrical Characteristics

Limits apply over the junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) VIN Minimum operating input voltage 3.5 V IQ Non-switching input current; measured at VIN pin(2) VEN = 3.3V, VFB = 1.2× regulation point 23 40 µA ISD Shutdown quiescent current; measured at VIN pin VEN = 0V 5.3 10 µA VUVLO_R Minimum operating voltage threshold Rising VIN, IVCC = 0A 3.5 V VUVLO_F Minimum operating voltage threshold Falling VIN, IVCC = 0A 2.6 3 V IPOR Pulldown current on SW when OVP is triggered VEN = 0V, VSW = 5V 0.5 1.5 2.5 mA ENABLE (EN PIN) VEN-VCC VCC enable voltage VEN rising 0.85 V VEN-H Precision enable high level for VOUT VEN rising 1.425 1.5 1.575 V VEN-L Precision enable low level for VOUT VEN falling 0.9 0.94 V ILKG-EN Enable input leakage current VEN = 13.5V –100 0.2 300 nA OUTPUT VOLTAGE SELECTION (VSEL PIN) RSEL-ADJ Resistor range for valid adjustable output voltage selection at start-up 8 50 kΩ INTERNAL LDO VCC Internal VCC voltage 6V ≤ VIN ≤ maximum operating VIN 4.75 5 5.25 V VCCM VCC clamp voltage 1mA sourced into VCC 5.25 5.55 5.8 V VOLTAGE REFERENCE (FB PIN) VFB_ADJ Feedback voltage VIN = 3.5 - maximum operating VIN 0.985 1 1.015 V VFB_5V Feedback voltage VIN = 5.5 - maximum operating VIN 4.925 5 5.075 V VFB_3p3V Feedback voltage VIN = 3.8 - maximum operating VIN 3.25 3.3 3.35 V IFB_ADJ Input leakage current at FB pin FB = 1V 0.2 100 nA IFB_5V Input leakage current at FB pin FB = 5V 2.89 3.4 µA IFB_3p3V Input leakage current at FB pin FB = 3.3V 1.67 2 µA CURRENT LIMITS ISC Short-circuit high side current Limit 1A Version 1.9 2.25 2.7 A ILS-LIMIT Low side current limit 1.5 1.8 2.12 A IPEAK-MIN Minimum Peak Inductor Current 0.375 0.7 A IL-NEG Negative current limit –1.49 –1.2 –0.75 A VHICCUP Hiccup threshold on FB pin 37% 42% 47% POWER GOOD ( RESET PIN) V RESET- HIGH RESET upper threshold - Rising % of FB voltage 110% 112% 115% V RESET- LOW RESET lower threshold - Falling % of FB voltage 91% 93% 95% V RESET- HYS RESET hysteresis % of FB voltage, 1.1% 1.8% 2.5% V RESET_VA LID Minimum input voltage for proper PG function Measured when V RESET < 0.4V with 10kΩ pullup to external 5V 0.7 1.04 1.25 V LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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6.5 Electrical Characteristics (continued)

6.6 Timing Requirements

128 Cycles

tOC Overcurrent hiccup retry delay time 70 104 140 ms tOC_active Time after soft start done timer before hiccup current protection is enabled 11 16 22 ms SOFT START tSS Internal soft-start time 1 1.6 2.2 ms tSS_DONE Soft-start done timer 5 8 11 ms POWER GOOD (RESET PIN) and OVERVOLTAGE PROTECTION tdg RESET edge deglitch delay 10 17 30 µs tRISE- DELAY RESET active time Time FB must be valid before RESET is released 2 3 5 ms OSCILLATOR (SYNC/MODE PIN) tON_OFF- SYNC Sync input ON and OFF-time 100 ns (1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation usingStatistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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6.7 Switching Characteristics

6.8 System Characteristics

The following specifications apply only to the typical applications circuit with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by production testing. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) ISUPPLY Input supply current when in regulation VIN = 12V, VOUT = 3.3V, IOUT = 0A, RFBT = 1MΩ 23 µA VDROP Dropout voltage; (VIN – VOUT) VOUT = 5V, IOUT = 1A, fSW = 1850kHz 0.95 V VDROP Dropout voltage; (VIN – VOUT) VOUT = 5V, IOUT = 1A, VOUT – 1% of regulation, fSW = 140kHz 150 mV DMAX Maximum switch duty cycle(2) VIN = VOUT = 12VOUT = 1A 98% VOLTAGE REFERENCE (FB PIN) VOUT (1) VOUT = 5V VIN = 7V to 30V , IOUT = 1A to full load, CCM –1.5% 1.5% VOUT = 5V VIN = 7V to 30V, IOUT = 0A to full load, AUTO mode –1.5% 2.5% VOUT (1) VOUT = 3.3V VIN = 3.8V to 30V , IOUT = 1A to full load, CCM –1.5% 1.5% VOUT = 3.3V VIN = 3.8V to 30V , IOUT = 0A to full load, AUTO mode –1.5% 2.5% tSYNC-L Delay from sync clock staying low to PFM entry 100 ns tSYNC-H Delay from sync clock staying high to default frequency 100 ns THERMAL SHUTDOWN TSD Thermal shutdown temperature Shutdown temperature 155 163 175 °C TSDR Thermal shutdown temperature Recovery temperature 150 °C (1) Deviation is with respect to VIN =13.5V, IOUT = 1A. (2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: fMIN = 1 / (tON-MAX + TOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN). LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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6.9 Typical Characteristics

Unless otherwise specified the following conditions apply: TA = 25°C, VIN = 13.5V Input Voltage (V) Input Current (PA) 5 10 15 20 25 30 35 40 OFF_ -40C 25C 125C EN = 0V Figure 6-1. Input Supply Current in Shutdown Mode INPUT VOLTAGE (1V/DIV) OUTPUT VOLTAGE (0.9V/DIV) UPDN IOUT = 1mA See Figure 8-23 Figure 6-2. UVLO Thresholds Input Voltage (V) Peak Inductor Current (mA) 5 10 15 20 25 30 35 40 400 425 450 475 500 525 550 575 600 Ipea -40C 25C 125C IOUT = 0A VOUT = 5V See Figure 8-23 fSW = 2100kHz Figure 6-3. IPEAK-MIN for LM63610 www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM63610-Q1

7 Detailed Description

7.1 Overview

The LM63610-Q1 devices are synchronous peak-current-mode buck regulators designed for a wide variety of automotive applications. The regulators automatically switch modes between PFM and PWM, depending on load. At heavy loads, the devices operate in PWM at a constant switching frequency. At light loads, the mode changes to PFM with diode emulation, allowing DCM. This reduces the input supply current and keeps efficiency high. The device features the following:

Adjustable switching frequency
Forced PWM mode (FPWM)
Frequency synchronization
Selectable output voltage The RESET output allows easy system sequencing. In addition, internal compensation reduces design time and requires fewer external components than externally compensated regulators.

7.2 Functional Block Diagram

OSCILLATOR INT. REG. BIAS 1.0 V Reference PFM MODE CONTROL CONTROL LOGIC HS CURRENT SENSE DRIVER LS CURRENT SENSE PWM COMP. SYNC/MODE RT VCC VIN CBOOT SW PGNDAGND FB VSEL EN RESET

7.3 Feature Description

7.3.1 SYNC/MODE Selection

The device features selectable operating modes through the SYNC/MODE input. Table 7-1 shows the selection programming. Mode changes can be made on the fly anytime after the device is powered up. It is not recommended that this input be allowed to float, however, an internal 100k Ω pulls the input to ground if left floating. The value of this internal resistor and the logic thresholds for this input can be found in the Table 7-1. See Device Functional Modes for details of the operating modes. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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Table 7-1. Mode Selection Settings SYNC/MODE INPUT MODE VCC FPWM AGND AUTO Synchronizing clock FPWM; synchronized to external clock Float (not recommended) AUTO

7.3.2 Output Voltage Selection

The output voltage of the device is set by the condition of the VSEL input. The condition of this input is tested when the device is first enabled. After the converter is running, the voltage selection is fixed and cannot be changed until the next power-on cycle. Table 7-2 shows the selection programming. The device contains an integrated voltage divider connected to the FB input. The converter regulates the voltage on the FB input to 5V, 3.3V, or 1V, as selected. In the ADJ mode, the voltage on the FB input is regulated to 1V and the internal divider is disabled. In this case, an external voltage divider is used to set the desired output voltage anywhere within the recommended operating range. The ADJ mode is programmed by connecting a 10kΩ from the VSEL input to ground. Although not recommenced, if this input is left floating, the device enters the ADJ mode. See Setting the Output Voltage for details of selecting the FB divider resistors. See the Specifications for specified specifications regarding the accuracy of the FB voltage and input current to the FB pin. Providing internal voltage dividers for the 5V and 3.3V modes saves external components, reducing both board space and component cost. The relatively large values of the internal dividers reduce the load on the output, helping to improve the light load efficiency of the converter. In addition, because the divider is inside the device, the divider is less likely to pick up externally generated noise. Table 7-2. Output Voltage Settings VSEL INPUT OUTPUT VOLTAGE VCC 5V AGND 3.3V 10kΩ to AGND ADJ Float (not recommended) ADJ

7.3.3 Switching Frequency Selection

The switching frequency is set by the condition of the RT input. The condition of this input is tested when the device is first enabled. After the converter is running, the switching frequency selection is fixed and cannot be changed until the next power-on cycle. Table 7-3 shows the selection programming. In the adjustable frequency mode, the switching frequency can be set between 250kHz and 2200kHz by proper selection of the value of R T. The curve in Figure 7-1 indicates the required resistor value for R T to set a desired switching frequency. TI does not recommend that this input be allowed to float; the switching action ceases with no generated output voltage under this condition. R T = 15770 f SW (1) where

RT = value of RT timing resistor in kΩ
fSW = switching frequency in kHz Table 7-3. Switching Frequency Settings RT INPUT SWITCHING FREQUENCY VCC 400kHz AGND 2100kHz www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LM63610-Q1

Table 7-3. Switching Frequency Settings (continued) RT INPUT SWITCHING FREQUENCY RT to AGND Adjustable according to RT value Float (not recommended) No switching 200 600 1000 1400 1800 2200 RT (k) Switching Frequency (kHz) C002 Figure 7-1. Switching Frequency versus RT

7.3.3.1 Spread Spectrum Option

The LM63610-Q1 is available with a spread spectrum clock dithering feature. This feature uses a pseudo- random pattern to dither the internal clock frequency. The pattern repeats at a 0.98Hz rate while the depth of modulation is ±5%. The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading emissions across a wider range of frequencies than a part with fixed frequency operation. In most systems containing the LM63610-Q1 devices, low frequency conducted emissions from the first few harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of emissions at higher harmonics which fall in the FM band. These harmonics often couple to the environment through electric fields around the switch node. The LM63610-Q1 devices use a ±5% spread of frequencies which spreads energy smoothly across the FM band but is small enough to limit subharmonic emissions below its switching frequency.

7.3.4 Enable and Start-up

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use of an external voltage divider to provide an adjustable input UVLO (see External UVLO ). Applying a voltage greater than VEN-VCC causes the device to enter standby mode, powering the internal VCC, but not producing an output voltage. Increasing the EN voltage to VEN-H fully enables the device, allowing it to enter start-up mode and begin the soft-start period. When the EN input is brought below V EN-L, the regulator stops running and enters standby mode. Further decrease in the EN voltage to below V EN-VCC completely shuts down the device. Figure 7-2 shows this behavior. The EN input can be connected directly to VIN if this feature is not needed. This input must not be allowed to float. The values for the various EN thresholds can be found in Specifications . The LM63610-Q1 uses a reference-based soft start that prevents output voltage overshoots and large inrush currents as the regulator is starting up. After EN goes high, there is a delay of about 1 ms before the soft-start period begins. The output voltage begins to rise and reaches the final value in about 1.5ms (t ss). After a delay of about 3ms (trise-delay), the RESET flag goes high. During start-up, the device is not allowed to enter FPWM mode until the tss-done time has elapsed. This time is measured from the rising edge of EN. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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Figure 7-2. Precision Enable Behavior

7.3.5 RESET Flag Output

The RESET flag function ( RESET output pin) of the LM63610-Q1 devices can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions lasting less than t dg do not trip the RESET flag. After the FB voltage has returned to the regulation value and after a delay of t rise-delay, the RESET flag goes high. RESET operation can best be understood by reference to Figure 7-3 and Figure 7-4. The RESET output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic supply. It can also be pulled up to either VCC or V OUT through an appropriate resistor, as desired. Values of pullup resistor in the range of 10k Ω to 100kΩ are reasonable. If this function is not needed, the RESET pin can be left floating. When EN is pulled low, the flag output is also forced low. With EN low, RESET remains valid as long as the input voltage is ≥ 1.2V (typical). Limit the current into the RESET flag pin to about 5mA D.C. The maximum current is internally limited to about 50mA when the device is enabled and about 65mA when the device is disabled. The internal current limit protects the device from any transient currents that can occur when discharging a filter capacitor connected to this output. www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LM63610-Q1

Low = Fault VRESET-HIGH High = Power Good VRESET-LOW VRESET-HYS VRESET-HYS Figure 7-3. Static RESET Operation VOUT Glitches do not cause false operation nor reset timer < tdg Trise-delay tdg VRESET-LOW RESET t t Trise-delay Figure 7-4. RESET Timing Behavior

7.3.6 Undervoltage Lockout and Thermal Shutdown and Output Discharge

The LM63610-Q1 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC pin). When VIN reaches about (VPOR-R), the device is ready to receive an EN signal and start-up. When V IN falls below (VPOR-F), the device shuts down, regardless of EN status. Because the LDO is in dropout during these transitions, the above values roughly represent the VCC voltage levels during the transitions. Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction temperature reaches about 163°C, the device shuts down; re-start occurs when the temperature falls to about 150°C. An extended input voltage UVLO can also be accomplished as shown in External UVLO. The LM63610-Q1 features an output voltage discharge FET connected from the SW pin to ground. This FET is activated when the EN input is below V EN-L, or when the output voltage exceeds V RESET-HIGH. This way, the LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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output capacitors are discharged through the power inductor. At output voltages above about 5V, the discharge current is approximately constant at I POR or about 1.4mA. Below this voltage, the FET characteristic looks approximately resistive at a value of 2.5kΩ.

7.4 Device Functional Modes

7.4.1 Overview

In typical usage, the device is put in AUTO mode (SYNC/MODE pin = ground). In AUTO mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator operates in PFM where the switching frequency is varied to regulate the output voltage. At higher loads, the mode changes to PWM with the switching frequency set by the condition of the RT pin (see Switching Frequency Selection). In PWM mode, the regulator operates as a current mode, the constant frequency converter using PWM to regulate the output voltage. While operating in this mode, the output voltage is regulated by switching at a constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and low output voltage ripple. In PFM mode, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The duration of the burst depends on how long it takes the inductor current to reach I PEAK-MIN. The periodicity of these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current required to regulate the output voltage at small loads. This trades off very good light-load efficiency for larger output voltage ripple and variable switching frequency. Also, a small increase in output voltage occurs at light loads. See Application Curves for output voltage variation with load in PFM mode. Figure 7-5 and Figure 7-6 show the typical switching waveforms in PFM and PWM. There are four cases where the switching frequency does not conform to the condition set by the RT pin:

Light load operation (AUTO mode)
Dropout
Minimum on-time operation
Current limit Under all of these cases, the switching frequency folds back, meaning it is less than that programmed by the RT control pin. During these conditions, by definition, the output voltage remains in regulation, except for current limit operation. When the device is placed in the forced PWM mode (FPWM), the switching frequency remains constant as programmed by the RT pin for all load conditions. This mode essentially turns off the light-load PFM frequency foldback mode detailed in Light Load Operation . See Sync/Mode Selection and Sync/FPWM Operation for details. www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LM63610-Q1

5 V/DIV

5 µs/DIV Figure 7-5. Typical PFM Switching Waveforms VIN = 12V, VOUT = 5V, IOUT = 10mA Switch Voltage Figure 7-6. Typical PWM Switching Waveforms FPWM VIN = 12V, VOUT = 5V, IOUT = 0A, fSW = 2100 kHz

7.4.2 Light Load Operation

During light load operation, the device is in PFM mode with DEM. This provides high efficiency at the lower load currents. The actual switching frequency and output voltage ripple depend on the input voltage, output voltage, and load. The output current at which the device moves in and out of PFM can be found in Application Curves. The output current for mode change depends on the input voltage, inductor value, and the programmed switching frequency. The curves apply for the BOM shown in Table 8-3 . At higher programmed switching frequencies, the load at which the mode change occurs is greater. For applications where the switching frequency must be known for a given condition, the transition between PFM and PWM must be carefully tested before the design is finalized. Alternatively, the mode can be set to FPWM.

7.4.2.1 Sync/FPWM Operation

The forced PWM mode (FPWM) can be used to turn off AUTO mode and force the device to switch at the frequency programmed by the RT pin, even for small loads. This has the disadvantage of lower efficiency at light loads. When a valid clock signal is present on the SYNC/MODE input, the switching frequency is locked to the external clock. The device mode is also FPWM. The mode can be changed dynamically by the system. See Figure 7-7 and Figure 7-8 for typical examples of SYNC/MODE function changes. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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Figure 7-7. Typical Transition from FPWM to AUTO Mode VIN = 12V, VOUT = 5V, IOUT = 1mA Inductor Current 500 mA/DIV Output Voltage 50 mV/DIV Sync Burst 5 V 200 µs/DIV Figure 7-8. Typical Transition from Sync Mode to FPWM Mode VIN = 12V, VOUT = 5V, IOUT = 1mA

7.4.3 Dropout Operation

The dropout performance of any buck regulator is affected by the R DSON of the power MOSFETs, the DC resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage level approaches the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value (see Specifications). Beyond this point, the switching can become erratic and the output voltage can fall out of regulation. To avoid this problem, the LM63610-Q1 automatically reduces the switching frequency to increase the effective duty cycle and maintain regulation. There are two definitions of dropout voltage used in this data sheet. For both definitions, the dropout voltage is the difference between the input and output voltage under a specific condition. For the first definition, the difference is taken when the switching frequency has dropped to 1850kHz (obviously this applies to cases where the nominal switching frequency is >1850kHz). For this condition, the output voltage is within regulation. For the second definition, the difference is taken when the output voltage has fallen by 1% of the nominal regulation value. In this condition, the switching frequency has reached the lower limit of about 130kHz. See Application Curves for details on these characteristics. Typical overall dropout characteristics can be found in Figure 7-9. Input Voltage (V) Output Voltage (V) 3.4 3.6 3.8 4.2 4.4 4.6 4.8 drop 1.5 A 2.5 A Figure 7-9. Overall Dropout Characteristic VOUT = 5V, Refer to LM63615/25 Data Sheet

7.4.4 Minimum On-time Operation

Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend the minimum controllable duty cycle, the LM63610-Q1 automatically reduces the switching frequency when the minimum on-time limit is reached. This way, the converter can regulate the lowest programmable output voltage www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LM63610-Q1

at the maximum input voltage. Use Equation 2 to find an estimate for the approximate input voltage for a given output voltage before frequency foldback occurs. The values of t ON and f SW can be found in Specifications. As the input voltage is increased, the switch on-time (duty-cycle) reduces to regulate the output voltage. When the on-time reaches the limit, the switching frequency drops while the on-time remains fixed. This relationship is highlighted in fSW vs VIN curves in Application Curves. V IN ≤ V O UT t ON × f S W (2)

7.4.5 Current Limit and Short-Circuit Operation

The LM63610-Q1 incorporates both peak and valley inductor current limits to provide protection to the device from overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current run-away during short circuits on the output, while both peak and valley limits work together to limit the maximum output current of the converter. A "hiccup" type mode is also incorporated for sustained short circuits. Finally, a zero current detector is used on the low-side power MOSFET to implement DEM at light loads (see the Glossary). The nominal value of this limit is about 0A. As the device is overloaded, a point is reached where the valley of the inductor current cannot reach below ILS-LIMIT before the next clock cycle. When this occurs, the valley current limit control skips that cycle, causing the switching frequency to drop. Further overload causes the switching frequency to continue to drop, but the output voltage remains in regulation. As the overload is increased, both the inductor current ripple and peak current increases until the high-side current limit, I SC, is reached. When this limit is activated, the switch duty cycle is reduced and the output voltage falls out of regulation. This represents the maximum output current from the converter and is given approximately by Equation 3. The output voltage and switching frequency continue to drop as the device moves deeper into overload while the output current remains at approximately IOMAX. I O MAX ≈ I SC + I LS − LIM IT 2 (3) If a severe overload or short circuit causes the FB voltage to fall below V HICCUP, the convert enters "hiccup" mode. VHICCUP represents about 40% of the nominal programmed output voltage. In this mode, the device stops switching for t OC, or about 100ms and then goes through a normal restart with soft start. If the short-circuit condition remains, the device runs in current limit for a little longer than t OC_active, or about 23ms, and then shuts down again. This cycle repeats, as shown in Figure 7-10 as long as the short-circuit condition persists. This mode of operation reduces the temperature rise of the device during a sustained short on the output. The output current in this mode is approximately 20% of I OMAX. After the output short is removed and the t OC delay is passed, the output voltage recovers normally as shown in Figure 7-11. See Figure 7-12 for the overall output voltage versus output current characteristic. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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Figure 7-10. Inductor Current Burst in Short-Circuit Mode; Refer to LM63615/25 Data Sheet Inductor Current

2 A/DIV

2 V/DIV

Short Applied Short Removed 50 ms/DIV Figure 7-11. Short-Circuit Transient and Recovery; Refer to LM63615/25 Data Sheet Output Voltage Output Current IOMAX0.2 × IOMAX 0.4 × VOUT VOUT Figure 7-12. Output Voltage versus Output Current in Current Limit www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LM63610-Q1

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The LM63610-Q1 step-down DC-to-DC converters are typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 1iA. The following design procedure can be used to select components for the device. Note In this data sheet, the effective value of capacitance is defined as the actual capacitance under D.C. bias and temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with an X5R or better dielectric throughout. All high value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and temperature effects. Under D.C. bias, the capacitance drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective capacitance up to the required value. This action can also ease the RMS current requirements on a single capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to make sure that the minimum value of effective capacitance is provided.

8.2 Typical Application

Figure 8-1 shows a typical application circuit for the device. This device is designed to function over a wide range of external components and system parameters. However, the internal compensation is optimized for a certain range of external inductance and output capacitance. As a quick start guide, see for typical component values. U1VIN EN SYNC/ MODE VSEL RT SW BOOT FB VCC PGND AGND 0.22μF CBOOT COUT L VOUT = 5V CIN CIN-HF VIN = 6V to 36V CVCC 100k 1 F 220nF4.7 F RESET RESET IOUT = 1A4.7 H 1 × 10 F Figure 8-1. Example Application Circuit VIN = 12V, VOUT = 5V, IOUT = 1A, fSW = 2.1MHz LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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Table 8-1. Typical External Component Values for 1A Output Current fSW (kHz) VOUT L (µH)(1) TYPICAL(2) COUT MINIMUM(2) COUT VSEL RT CIN CBOOT CVCC 400 3.3 10 4 × 10µF 2 × 10µF AGND VCC 4.7µF + 220nF 220nF 1µF 2100 3.3 4.7 2 × 10µF 1 × 10µF AGND AGND 4.7µF + 220nF 220nF 1µF 400 5 10 4 × 10µF 2 × 10µF VCC VCC 4.7µF + 220nF 220nF 1µF 2100 5 4.7 2 × 10µF 1 × 10µF VCC AGND 4.7µF + 220nF 220nF 1µF (1) See the Inductor Selection section. (2) See the Output Capacitor Selection section.

8.2.1 Design Requirements

Table 8-2 provides the parameters for the detailed design procedure: Table 8-2. Detailed Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 12V (6V to 36V) Output voltage 5V Maximum output current 0A to 1A Switching frequency 2.1MHz

8.2.2 Detailed Design Procedure

The following design procedure applies to Figure 8-1 and Table 8-2.

8.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size. Lower switching frequency implies reduced switching losses and usually results in higher system efficiency. However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence, a more compact design. 2100kHz was chosen for this example.

8.2.2.2 Setting the Output Voltage

The output voltage of the LM63610-Q1 is set by the condition of the VSEL input. This example requires a 5V output, so the VSEL input is connected to VCC and the FB input is connected directly to the output capacitor. For cases where the desired output voltage is other than 5V or 3.3V, an external feedback divider is required. As shown in Figure 8-2, the divider network is comprised of R FBT and R FBB, and closes the loop between the output voltage and the converter. In this case, a 10k Ω resistor is connected from the VSEL input go ground. The converter regulates the output voltage by holding the voltage on the FB pin equal to the internal reference voltage, 1V. The resistance of the divider is a compromise between excessive noise pickup and excessive loading of the output. Smaller values of resistance reduce noise sensitivity, but also reduce the light-load efficiency. The recommended value for R FBT is 100k Ω with a maximum value of 1M Ω. If 1M Ω is selected for RFBT, then a feedforward capacitor must be used across this resistor to provide adequate loop phase margin (see CFF Selection). After RFBT is selected, Equation 4 is used to select RFBB. VREF is nominally 1V. R FBB = R F B T V OUT V RE F − 1 (4) www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LM63610-Q1

10 k Figure 8-2. Feedback Divider for Adjustable Output Voltage Setting

8.2.2.2.1 CFF Selection

In some cases, a feedforward capacitor can be used across R FBT to improve the load transient response or improve the loop-phase margin. This is especially true when values of R FBT > 100kΩ are used. Large values of RFBT in combination with the parasitic capacitance at the FB pin can create a small signal pole that interferes with the loop stability. A CFF helps mitigate this effect. Equation 5 can be used to estimate the value of C FF. The value found with Equation 5 is a starting point; use lower values to determine if any advantage is gained by the use of a C FF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with Feedforward Capacitor Application Report is helpful when experimenting with a feedforward capacitor. C FF < V O UT × C OUT 120 × R FBT × V R EF V OUT (5)

8.2.2.3 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load current. Use the maximum device current when you select the ripple current for applications with much smaller maximum load than the maximum available from the device. Equation 6 can be used to determine the value of inductance. The constant K is the percentage of inductor current ripple. K = 0.3 was chosen for this example and L = 4.7µH inductance was found. L = V IN − V O U T f SW × K × I OUTmax × V OUT V IN (6) Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, ISC (see Specifications). This makes sure that the inductor does not saturate even during a short circuit on the output. When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly. Although the valley current limit, I LIMIT, is designed to reduce the risk of current run-away, a saturated inductor can cause the current to rise to high values very rapidly. This can lead to component damage. Do not allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some relaxation in the current rating of the inductor. However, they have more core losses at frequencies above about 1MHz. In any case, the inductor saturation current must not be less than the maximum peak inductor current at full load. To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 7 . The maximum inductance is limited by the minimum current ripple required for the current mode control to perform correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device maximum rated current under nominal conditions. L MIN ≥ M × V OUT f SW (7) LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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M = 0.69 for 1A device

8.2.2.4 Output Capacitor Selection

The value of the output capacitor and its ESR determine the output voltage ripple and load transient performance. The output capacitor bank is usually limited by the load transient requirements rather than the output voltage ripple. Use Equation 8 to estimate a lower bound on the total output capacitance, and an upper bound on the ESR, which are required to meet a specified load transient. C O UT ≥ ∆ I OUT f SW × ∆ V O UT × K × 1 − D × 1 + K + K 2 12 × 2 − D ESR ≤ 2 + K × ∆ V O UT 2 × ∆ I O UT × 1 + K + K 2 12 × 1 + 1 1 − D D = V OUT V IN (8) where

ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = ripple factor from Inductor Selection After the output capacitor and ESR have been calculated, use Equation 9 to check the peak-to-peak output voltage ripple, Vr. V r ≅ ∆ I L × ESR 2 + 1 8 × f SW × C O UT 2 (9) The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple requirements. This example requires a ΔVOUT of ≤ 150mV for an output current step of ΔIOUT = 1A. Equation 8 gives a minimum value of 8.1µF and a maximum ESR of 0.13 Ω. Assuming a 20% tolerance and a 10% bias de-rating, the user arrives at a minimum capacitance of 10µF. This can be achieved with a 10µF, 16V, ceramic capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response. Ceramic capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic capacitor can be placed in parallel with the ceramics to build up the required value of capacitance. When using a mixture of aluminum and ceramic capacitors, use the minimum recommended value of ceramics and add aluminum electrolytic capacitors as needed. In general, use a capacitor rating of at least 10V for output voltages of 3.3V or less, and use a capacitor of 16V or more for output voltages of 5V and above. The recommendations given in Table 8-1 provide typical and minimum values of output capacitance for the given conditions. These values are the rated or nameplate figures. If the minimum values are to be used, the design must be tested over all of the expected application conditions, including input voltage, output current, and ambient temperature. This testing must include both bode plot and load transient assessments. The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed. In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LM63610-Q1

placed on the output can reduce high frequency noise. Small case size ceramic capacitors in the range of 1nF to 100nF can help reduce spikes on the output caused by inductor and board parasitics.

8.2.2.5 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum of 4.7µF of ceramic capacitance is required on the input of the LM63610-Q1, connected directly between VIN and PGND. This must be rated for at least the maximum input voltage that the application requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. More input capacitance is required for larger output currents. In addition, a small case size 220nF ceramic capacitor must be used at the input as close a possible to the regulator, typically within 1mm of the VIN and PGND pins. This provides a high frequency bypass for the control circuits internal to the device. For this example, a 4.7µF, 50V, X7R (or better) ceramic capacitor is chosen. The 220nF must also be rated at 50V with an X7R dielectric and preferably a small case size, such as an 0603. Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance. Most of the input switching current passes through the ceramic input capacitor or capacitors. Use Equation 10 to calculate the approximate RMS current. This value must be checked against the manufacturers' maximum ratings. I RM S ≅ I O UT 2 (10) The input capacitor is part of the buck converter high di/dt current loop. The high di/dt current, together with excessive parasitic inductance between the IC and the input capacitor, can result in excessive voltage ringing on the SW node of the IC. The placement of the input capacitor on the board is critical for minimizing the parasitic inductance in the high di/dt loop and accordingly minimizing the SW node ringing at each switching. For designs targeting the maximum operating voltage of the regulator, make sure that the ringing on the SW node must not exceed the absolute maximum rating of the device. The SW node ringing is a function of how well the input capacitor is positioned with respect to the IC. Refer to the PCB layout example in Layout Example for proper placement of the input capacitors.

8.2.2.6 CBOOT

The LM63610-Q1 requires a bootstrap capacitor to be connected between the BOOT pin and the SW pin. This capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of 220nF and at least 16V is required.

8.2.2.7 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output requires a 1µF, 16V ceramic capacitor connected from VCC to PGND for proper operation. In general, this output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the RESET function and as a logic supply for the various control inputs of the device. A value of 100kΩ is a good choice for the RESET flag pullup resistor. The nominal output voltage on VCC is 5V.

8.2.2.8 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This can be accomplished by using the circuit shown in Figure 8-3 . The input voltage at which the device turns on is designated as V ON while the turnoff voltage is V OFF. First, a value for R ENB is chosen in the range of 10k Ω to 100kΩ. Then, Equation 11 is used to calculate RENT and VOFF. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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Figure 8-3. Setup for External UVLO Application R ENT = R EN B × V ON V EN − H − 1 V OFF = V EN − L × V ON V EN − H (11) where

VON = VIN turn-on voltage
VOFF = VIN turn-off voltage

8.2.2.9 Maximum Ambient Temperature

As with any power conversion device, the LM63610-Q1 dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance, RθJA of the device, and PCB combination. The maximum internal die temperature for the LM63610-Q1 must be limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load current. Equation 12 shows the relationships between the important parameters. It is easy to see that larger ambient temperatures (T A) and larger values of R θJA reduce the maximum available output current. The converter efficiency can be estimated by using the curves provided in this data sheet. Note that these curves include the power loss in the inductor. If the desired operating conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly. The correct value of R θJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal Metrics Application Report , the value of R θJA given in the Thermal Information table is not valid for design purposes and must not be used to estimate the thermal performance of the application. The values reported in that table were measured under a specific set of conditions that are rarely obtained in an actual application. The data given for R θJC(bott) and ΨJT can be useful when determining thermal performance. See Semiconductor and IC Package Thermal Metrics Application Report for more information and the resources given at the end of this section. I O UT ma x = T J − T A R θJ A × η 1 − η × 1 V OUT (12) where

η = efficiency The effective RθJA is a critical parameter and depends on many factors such as the following:
Power dissipation
Air temperature/flow
PCB area
Copper heat-sink area
Number of thermal vias under the package
Adjacent component placement The HTSSOP uses a die attach paddle, or "thermal pad" (DAP) to provide a place to solder down to the PCB heat-sinking copper. This provides a good heat conduction path from the regulator junction to the heat sink and www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LM63610-Q1

must be properly soldered to the PCB heat sink copper. A typical example of R θJA versus copper board area can be found in Figure 8-4. The copper area given in the graph is for each layer. The top and bottom layers are 2oz. copper each, while the inner layers are 1oz. Figure 8-4 shows a typical curve of maximum output current versus ambient temperature. This data was taken with a device and PCB combination, giving an R θJA of about 30°C/W. Remember that the data given in these graphs are for illustration purposes only, and the actual performance in any given application depends on all of the previously mentioned factors. Copper Area (cm2) RTJA (qC/W) 0 20 40 60 80 100 120 140 160 180 17.5 22.5 27.5 32.5 37.5 thet 4L, 0.9W 4L, 2W 2L, 0.9W 2L, 2W Figure 8-4. Typical RθJA versus Copper Area for the HTSSOP Package The following resources can be used as a guide to optimal thermal PCB design and estimating R θJA for a given application environment:

AN-2020 Thermal Design By Insight, Not Hindsight Application Report
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
Semiconductor and IC Package Thermal Metrics Application Report
Thermal Design Made Simple with LM43603 and LM43602 Application Report
Using New Thermal Metrics Application Report LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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8.2.3 Application Curves

Unless otherwise specified, the following conditions apply: V IN = 13.5V, TA = 25°C. Figure 8-23 shows the circuit with the appropriate BOM from Table 8-3. Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 100 eff_ 13.5V 18V 24V LM63610 VOUT = 5V fSW = 400kHz (AUTO) Figure 8-5. Efficiency Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 eff_ 13.5V 18V 24V LM63610 VOUT = 5V fSW = 2100kHz (AUTO) Figure 8-6. Efficiency Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 eff_ 13.5V 18V 24V LM63610 VOUT = 3.3V fSW = 400kHz (AUTO) Figure 8-7. Efficiency Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 eff_ 13.5V 18V 24V LM63610 VOUT = 3.3V fSW = 2100kHz (AUTO) Figure 8-8. Efficiency Output Current (A) Output Voltage (V) 4.98 4.99 5.01 5.02 5.03 5.04 5.05 5.06 LL_5 13.5V 18V 24V LM63610 VOUT = 5V fSW = 2100kHz (AUTO) Figure 8-9. Line and Load Regulation Output Current (A) Output Voltage (V) 3.29 3.3 3.31 3.32 3.33 3.34 LL_3 13.5V 18V 24V A. LM63610 VOUT = 3.3V fSW = 2100kHz (AUTO) Figure 8-10. Line and Load Regulation www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LM63610-Q1

Output Current (A) Switching Frequency (kHz) 1E-6 1E-5 0.0001 0.001 0.01 0.1 1 0.01 0.1 100 1000 10000 Fsw_ 3.3V LM63610 VIN = 13.5V fSW = 2100kHz (AUTO) Figure 8-11. Switching Frequency versus Output Current Input Voltage (V) Switching Frequency (kHz) 0 4 8 12 16 20 24 28 32 36 40 250 500 750 1000 1250 1500 1750 2000 2250 Fsw_ 1.5A LM63610 VOUT = 3.3V fSW = 2100kHz (FPWM) Figure 8-12. Switching Frequency versus Input Voltage Input Voltage (V) Switching Frequency (kHz) 0 4 8 12 16 20 24 28 32 36 40 250 500 750 1000 1250 1500 1750 2000 2250 Fsw_ 1.5A LM63610 VOUT = 5V fSW = 2100kHz (FPWM) Figure 8-13. Switching Frequency versus Input Voltage 3.3V VOUT, 200mV/DIV Output Current, 1A/DIV 50µs/DIV LM63610 VOUT = 3.3V fSW = 2100kHz 0A to 1.5A, 2µs FPWM Figure 8-14. Load Transient Output Current, 1A/DIV VOUT, 200mV/DIV 50µs/DIV LM63610 VOUT = 5V fSW = 2100kHz 0A to 1.5A, 2µs FPWM Figure 8-15. Load Transient 3.3V Output Current, 1A/DIV VOUT, 100mV/DIV 50µs/DIV LM63610 VOUT = 3.3V fSW = 2100kHz 0.5A to 1.5A, 2µs AUTO Figure 8-16. Load Transient LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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0.22μF CBOOT COUT L VOUT CIN CIN-HF VIN CVCC 100k 1 F 220nF10 F RESET RESET Frequency VOUT Mode Figure 8-23. Circuit for Typical Application Curves Table 8-3. BOM for Typical Application Curves VOUT (1) FREQUENCY OUTPUT CURRENT COUT L 3.3V 400kHz 1A 2 × 22µF 10µH, 40mΩ 3.3V 2100kHz 1A 1 × 10µF 4.7µH, 30mΩ 5V 400kHz 1A 2 × 22µF 10µH, 40mΩ 5V 2100kHz 1A 1 × 10µF 4.7µH, 30mΩ (1) The values in this table were selected to enhance certain performance criteria and can not represent typical values. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

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8.2.4 EMI Performance Curves

EMI results critically depend on PCB layout and test setup. The results given here are typical and given for information purposes only. Figure 8-26 shows the used EMI filter. The limit lines shown refer to CISPR25 class 5. 1 MHz 10 MHz 30 MHz0.15 MHz dBµV AV PK LM63625DQ VOUT = 5V fSW = 2100kHz IOUT = 2.5A Dither Figure 8-24. Typical Conducted EMI With LM63625 150kHz to 30MHz

80 MHz30 MHz 100 MHz

dBµV AV PK LM63625DQ VOUT = 5V fSW = 2100kHz IOUT = 2.5A Dither Figure 8-25. Typical Conducted EMI With LM63625 30MHz to 108MHz F 4.7 F Input Supply 1.5 H 0.51 2 × 2.2 F 0.22 F Input to Regulator Ferrite Bead A. Input filter used only for EMI measurements shown in the EMI Performance Curves section. Figure 8-26. Typical Input EMI Filter With LM63625

8.3 Best Design Practices

Do not exceed the Absolute Maximum Ratings.
Do not exceed the Recommended Operating Conditions.
Do not exceed the ESD Ratings.
Do not allow the EN input to float.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
Do not use the value of RθJA given in the Thermal Information table to design your application. See the Maximum Ambient Temperature section.
Follow all the guidelines and suggestions found in this data sheet before committing the design to production. TI application engineers are ready to help critique your design and PCB layout to help make your project a success.
Use a 220nF capacitor connected directly to the VIN and PGND pins of the device. See the Section 8.2.2.5 section for details. www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LM63610-Q1

8.4 Power Supply Recommendations

The characteristics of the input supply must be compatible with the limits found in the Section 6 table of this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded regulator. The average input current can be estimated with Equation 13. I IN = V O UT × I OUT V I N × η (13) where

η is the efficiency If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input capacitors, can form an under damped resonant circuit, resulting in overvoltage transients at the input to the regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and reduce any overshoots. A value in the range of 20µF to 100µF is usually sufficient to provide input damping and help hold the input voltage steady during large load transients. TI recommends that the input supply must not be allowed to fall below the output voltage by more than 0.3V. Under such conditions, the output capacitors discharges through the body diode of the high-side power MOSFET. The resulting current can cause unpredictable behavior, and in extreme cases, possible device damage. If the application allows for this possibility, then use a Schottky diode from VIN to VOUT to provide a path around the regulator for this current. In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the output voltage of the regulator, the output capacitors discharges through the device, as mentioned above. Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to instability as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple Success with Conducted EMI from DCDC Converters User's Guide provides helpful suggestions when designing an input filter for any switching regulator.

8.5 Layout

8.5.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the regulator is dependent on the PCB layout to a great extent. In a buck converter, the most critical PCB feature is the loop formed by the input capacitors and power ground, as shown in Figure 8-27. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this disruption, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Figure 8-28 shows a recommended layout for the critical components of the . 1. Place the input capacitors as close as possible to the VIN and PGND terminals. VIN and PGND pins are adjacent, simplifying the input capacitor placement. Thermal reliefs in this area are not recommended. 2. Place a bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and routed with short, wide traces to the VCC and PGND pins. Thermal reliefs in this area are not recommended. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

Product Folder Links: LM63610-Q1

Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short and wide traces to the BOOT and SW pins. Thermal reliefs in this area are not recommended. 4. Place the feedback divider as close as possible to the FB pin of the device. If an external feedback divider is used with the ADJ option, place RFBB, RFBT, and CFF, close to the device. The connections to FB and AGND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator. 5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as a heat dissipation path. 6. Connect the thermal pad to the ground plane. The thermal pad (DAP) connection must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection and an electrical ground connection for the regulator. The integrity of this solder connection has a direct bearing on the total effective RθJA of the application. Thermal reliefs in this area are not recommended. 7. Provide wide paths for VIN, VOUT, SW, and PGND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. Thermal reliefs in this area are not recommended. 8. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature section, enough copper area must be used to make sure of a low RθJA, commensurate with the maximum load current and ambient temperature. The top and bottom PCB layers must be made with two ounce copper and no less than one ounce. Use an array of heat-sinking vias to connect the thermal pad (DAP) to the ground plane on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer heat-spreading ground planes. 9. Keep the switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI. See the following PCB layout resources for additional important guidelines:

Layout Guidelines for Switching Power Supplies application report
Simple Switcher PCB Layout Guidelines application report
Construction Your Power Supply- Layout Considerations seminar
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application report CIN VIN SW GND KEEP CURRENT LOOP SMALL Figure 8-27. Current Loops With Fast Edges

8.5.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces. A ground plane also provides a quiet reference potential for the control circuitry. Connect the AGND and PGND pins to the ground planes using vias next to the bypass www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LM63610-Q1

capacitors. PGND pins are connected directly to the source of the low-side MOSFET switch and also connected directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the ground plane contains much less noise and must be used for sensitive routes. TI recommends providing adequate device heat sinking by using the thermal pad (DAP) of the device as the primary thermal path. Use a minimum 4 × 3 array of 10 mil thermal vias to connect the DAP to the system ground plane heat sink. The vias must be evenly distributed under the DAP. Use as much copper as possible for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding, and lower thermal resistance. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

Product Folder Links: LM63610-Q1

8.5.2 Layout Example

Bottom Trace VIA to Ground Plane SYNC/MODE CVCC RT VCC CBOOT FB AGND Figure 8-28. Example Layout www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LM63610-Q1

9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation see the following:

Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application report
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 application report
Texas Instruments, Using New Thermal Metrics application report
Texas Instruments, Layout Guidelines for Switching Power Supplies application report
Texas Instruments, Simple Switcher PCB Layout Guidelines application report
Texas Instruments, Constructing Your Power Supply-layout Considerations seminar
Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application report

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 www.ti.com

Product Folder Links: LM63610-Q1

Changes from Revision B (May 2025) to Revision C (August 2026) Page

Added a statement and table note about input capacitor placement recommendation in the Pin Configurations Changes from Revision A (July 2021) to Revision B (May 2025) Page
Updated fSPREAD specification to combine HTSSOP and WSON packages in the Switching Characteristics Changes from Revision * (July 2020) to Revision A (July 2021) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LM63610-Q1 SNVSBO7C – JULY 2020 – REVISED AUGUST 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LM63610-Q1

www.ti.com 26-Aug-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM63610DQDRRRQ1 Active Production WSON (DRR) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 150 L63610 LM63610DQDRRRQ1.A Active Production WSON (DRR) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 150 L63610 LM63610DQPWPRQ1 Active Production HTSSOP (PWP) | 16 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 150 63610DQ LM63610DQPWPRQ1.A Active Production HTSSOP (PWP) | 16 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 150 63610DQ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM63610DQDRRRQ1 WSON DRR 12 3000 367.0 367.0 35.0 LM63610DQPWPRQ1 HTSSOP PWP 16 2000 353.0 353.0 32.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 6.6

6.2 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.2 MAX

2X 0.95 MAX NOTE 5 2X 0.23 MAX NOTE 5 2.30 1.54 2.46 1.86 B 4.5 4.3 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP 4X (0.3) PowerPAD TSSOP - 1.2 mm max heightPWP0016K SMALL OUTLINE PACKAGE 4224484/A 08/2018

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may differ or may not be present. TM PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 2.500 THERMAL PAD 8 9

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP (3.4) NOTE 9 (5) NOTE 9 (1.1) TYP (0.6) (1.2) TYP ( 0.2) TYP VIA (2.46) (2.3) PowerPAD TSSOP - 1.2 mm max heightPWP0016K SMALL OUTLINE PACKAGE 4224484/A 08/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP (2.3) BASED ON

0.125 THICK

(2.46) BASED ON PowerPAD TSSOP - 1.2 mm max heightPWP0016K SMALL OUTLINE PACKAGE 4224484/A 08/2018 2.08 X 1.940.175 2.25 X 2.100.15 2.46 X 2.30 (SHOWN)0.125 2.75 X 2.570.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9 METAL COVERED BY SOLDER MASK SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WSON - 0.8 mm max heightDRR 12 PLASTIC SMALL OUTLINE - NO LEAD3 x 3, 0.5 mm pitch 4223490/B

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4224874/C 11/2023 www.ti.com WSON - 0.8 mm max height PLASTIC QUAD FLAT PACK- NO LEAD DRR0012E A 0.08 C 0.05 C B SYMM SYMM

0.1 MIN

(0.13) SECTION A-A TYPICAL PIN 1 INDEX AREA 3.1 2.9 3.1 2.9 0.05 0.00 0.8 0.7 SEATING PLANE C 2.5 A A PIN 1 ID (45° X 0.3) 10X 0.5 12X 0.52 0.32 12X 0.3 0.2 (0.43) TYP 2.6 2.4 1.4 1.2 (0.2) TYP 6 7 (0.16) TYP

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4224874/C 11/2023 www.ti.com WSON - 0.8 mm max heightDRR0012E PLASTIC QUAD FLAT PACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X EXPOSED METAL METAL SOLDER MASK OPENING

0.07 MAX

(PREFERRED) SOLDER MASK DEFINED EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING

0.07 MIN

(1.3) (2.5) (1) (2.5) 10X (0.5) 12X (0.25) 12X (0.62) (Ø0.2) VIA TYP 2X (2.78) (R0.05) TYP 1 12

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224874/C 11/2023 www.ti.com WSON - 0.8 mm max heightDRR0012E PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 82% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM 2X (1.21) (1.1) (0.65) (2.5) 10X (0.5) 12X (0.25) 12X (0.62) 2X (2.78) (R0.05) TYP

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated Last updated 10/2025

Product Information

LM63610-Q1 specifications and overview.

Summary

LM63610-Q1 3.5-V to 36-V, 1-A, Automotive Step-down Voltage Converter

Description

LM63610-Q1 3.5-V to 36-V, 1-A, Automotive Step-down Voltage Converter

Source title LM63610-Q1 Datasheet(PDF) - Texas Instruments

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