Power Management

LM63440AASQRYFRQ1

Texas Instruments

LM634x0-Q1 3V to 36V, 4A and 6A, Automotive, Synchronous Buck DC/DC Converters With Adjustable Switching Frequency, Optimized for Reliability and Low EMI REVISED AUGUST 2024

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LM634x0-Q1 3V to 36V, 4A and 6A, Automotive, Synchronous Buck DC/DC Converters With Adjustable Switching Frequency, Optimized for Reliability and Low EMI

1 Features

AEC-Q100 qualified for automotive applications – Device temperature grade 1: –40°C to +125°C ambient operating temperature
Functional Safety-Capable – Documentation available to aid functional safety system design
Versatile synchronous buck DC/DC converter – Wide input voltage range of 3V to 36V with tolerance for load-dump transients up to 42V – 4A and 6A options available – 1% accurate adjustable output voltage from 1V to 95% VIN – 150°C maximum junction temperature – Frequency adjustable from 200kHz to 2.2MHz using the RT pin or a SYNC signal
Improved reliability with optimized pinout design and clearance for short-circuit-to-adjacent-pin test
Designed for low EMI requirements – Enhanced HotRod™ QFN package with dual input paths reduces switch-node ringing – Spread spectrum frequency modulation – Selectable FPWM or PFM mode at light loads
High efficiency across the full load range – 92.5% at 13.5VIN, 5VOUT, 6A, 2.1MHz – 7µA typical at 3.3VOUT no-load input current – 0.6µA typical shutdown quiescent current – 0.6V typical dropout at full load – External bias option for improved efficiency
Create a custom regulator design using the LM634x0-Q1 with WEBENCH® Power Designer

2 Applications

Automotive infotainment and cluster: head unit, media hub, USB charge, display
Automotive ADAS and body electronics

3 Description

The LM634x0-Q1 derives from a family of automotive, synchronous, buck, DC/DC converters with excellent efficiency and ultra-low I Q. With integrated high-side and low-side MOSFETs, up to 6A of output current is delivered over a wide input voltage range from 3V to 36V, with support for load-dump transients up to 42V. The converter implements soft recovery from dropout to eliminate overshoot on the output. The LM634x0-Q1 incorporates numerous features for excellent EMI performance, including spread- spectrum frequency modulation, a low-EMI Enhanced HotRod QFN package that mitigates switch-node ringing, and a symmetrical pinout for excellent input capacitor placement. The switching frequency can be set between 200kHz and 2.2MHz to avoid sensitive frequency bands, while optimizing efficiency or design size based on the application requirements. PFM mode enables frequency foldback during light-load operation, allowing an unloaded current consumption of only 7µA (typical) and high light-load efficiency. A seamless transition between PWM and PFM modes, along with low MOSFET on-resistances and an external bias input, provides exceptional efficiency and thermal performance across the entire load range. The package has several NC pins between critical power pins, which improve the Failure Modes and Effects Analysis (FMEA) result. Device Information PART NUMBER(1) CURRENT PACKAGE(2) LM63460-Q1 6A RYF (VQFN, 22) LM63440-Q1 4A (1) See the Device Comparison Table . (2) For more information, see Section 11. PGOOD EN/SYNC PGND1 CBOOT SW FB BIAS VIN1 PGND2 VIN2 CIN-HF1 CIN-HF2 CIN CBOOT COUT LOLM63460-Q1 VOUT = 5 V IOUT = 6 A VIN = 3 V...36 V * VOUT tracks VIN if VIN < 5.6 V 2 47 F 0.76 H 0.1 F F 10 F 10 nF 10 nF RFBT RT GND VCC CVCC RFBB RRT 6.04 k 24.9 k 100 k Typical Schematic O u t p u t C u r r e n t ( A ) Efficiency (%) 0 1 2 3 4 5 6 7 5 8 0 8 5 9 0 9 5 1 0 0 V I N = 8 V V I N = 1 2 V V I N = 1 8 V V I N = 2 4 V Efficiency, VOUT = 5V, fSW = 2.1MHz, LM63460-Q1 LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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4 Device Comparison Table

LM63460AASQRYFRQ1 Adjustable 6A On AUTO Adjustable Standard LM63460AFSQRYFRQ1 Adjustable 6A On FPWM Adjustable Standard LM64460-Q1 LM64460APPQRYFRQ1 Adjustable 6A Pin selectable Pin selectable 2.1MHz Standard LM64460APPSRYFRQ1 Adjustable 6A Pin selectable Pin selectable 2.1MHz Tri-temperature LM64460BPPQRYFRQ1 3.3V 6A Pin selectable Pin selectable 2.1MHz Standard LM64460CPPQRYFRQ1 5V 6A Pin selectable Pin selectable 2.1MHz Standard LM63440-Q1 LM63440AASQRYFRQ1 Adjustable 4A On AUTO Adjustable Standard LM63440AFSQRYFRQ1 Adjustable 4A On FPWM Adjustable Standard LM64440-Q1 LM64440APPQRYFRQ1 Adjustable 4A Pin selectable Pin selectable 2.1MHz Standard LM64440BPPQRYFRQ1 3.3V 4A Pin selectable Pin selectable 2.1MHz Standard LM64440CPPQRYFRQ1 5V 4A Pin selectable Pin selectable 2.1MHz Standard www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LM63440-Q1 LM63460-Q1

5 Pin Configuration and Functions

Figure 5-1. 22-Pin Enhanced HotRod ™ QFN RYF Package (Top View) Table 5-1. Pin Functions PIN TYPE (1)

DESCRIPTION

NAME NO. CBOOT 1 P High-side driver supply rail. Connect a 100nF capacitor between SW and CBOOT. An internal bootstrap diode connects to VCC and allows the bootstrap capacitor to charge when SW is low. NC 2 — No internal connection BIAS 3 P Input to the internal LDO. Connect to the output voltage point to improve efficiency. Connect an optional high-quality 0.1µF to 1µF capacitor from this pin to GND for improved noise immunity. If the output voltage is above 12V, connect BIAS to GND. VCC 4 O Internal LDO output. VCC supplies the internal control circuits. Do not connect to any external loads. Connect a high-quality 1µF capacitor from VCC to GND. FB 5 I Output voltage feedback input to the internal control loop. Connect to the output voltage sense point for fixed 3.3V or 5V output voltage settings. Connect to a feedback divider tap point to set an adjustable output voltage. Do not float or connect to GND. PGOOD 6 O Open-drain power-good status indicator output. Pull up PGOOD to a suitable voltage supply through a current-limiting resistor. High = power OK, low = fault. The PGOOD output goes low when EN = low, VIN > 1V. RT 7 I/O Connect a resistor from RT to GND with a value between 5.76kΩ and 66.5kΩ to set the switching frequency between 200kHz and 2.2MHz. Do not float or connect directly to GND. EN/SYNC 8 I Precision enable input. High = on, Low = off. EN/SYNC can be connected to VIN. Precision enable allows this pin to be used as an adjustable input voltage UVLO. See Precision Enable and Input Voltage UVLO (EN) . Do not float. EN/SYNC also functions as a synchronization input pin, triggering on the rising edge of the external clock signal. Use a capacitor to AC couple the clock signal to EN/SYNC. When synchronized to an external clock, the converter operates in FPWM mode and disables the PFM light-load mode. See Section 7.3.5. NC 9 — No internal connection VIN2 10 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. A low-impedance connection must be provided to VIN1. NC 11 — No internal connection PGND2 12 G Power-ground connection to the internal low-side MOSFET. Connect to system ground. A low- impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2. NC 13 — No internal connection LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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Table 5-1. Pin Functions (continued) PIN TYPE (1) NAME NO. SW1 14 P Switch node of the converter. Connect to the output inductor.SW2 15 SW3 16 NC 17 — No internal connection PGND1 18 G Power ground to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1. NC 19 — No internal connection VIN1 20 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. A low-impedance connection must be provided to VIN2. NC 21 — No internal connection SW4 22 P Switch node of the converter. Connect to the bootstrap capacitor. GND – G Exposed pad of the package internally connected to ground. The exposed pad must be connected to the PCB inner-layer system ground plane or planes using numerous thermal vias to reduce thermal impedance. See Layout Guidelines . (1) P = Power, G = Ground, I = Input, O = Output

5.1 Wettable Flanks

100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins and terminals that are easily viewed. Therefore, visually determining whether or not the package is successfully soldered onto the printed-circuit board (PCB) is difficult. The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LM634x0-Q1 is assembled using a 22-pin Enhanced HotRod QFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs.

5.2 Pinout Design for Clearance and FMEA

The LM634x0-Q1 has a carefully designed pinout arrangement that provides additional clearance spacing between high-voltage pins (VIN, SW, and CBOOT) and nearby low-voltage pins (such as PGND). Moreover, the LM634x0-Q1 pinout is designed for critical automotive applications requiring functional safety system design with stricter reliability and higher durability. In terms of pin FMEA (failure mode effects analysis), the typical failure scenarios considered include short circuit to ground, short circuit to input supply (VIN), short circuit to a neighboring pin, and if a pin is left open circuit. These faults are considered as applied externally to the IC and therefore are board-level failures rather than IC-level reliability failures. Example sources of such faults are stray conductive filaments causing pin-to-pin shorts or a board manufacturing defect causing an open-circuit track. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM63440-Q1 LM63460-Q1

6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)(1) MIN MAX UNIT Input Voltage VIN1, VIN2 to PGND1, PGND2 –0.3 42 V CBOOT to SW –0.3 5.5 V BIAS to PGND1, PGND2 –0.3 16 V EN/SYNC to PGND1, PGND2 –0.3 42 V RT to PGND1, PGND2 –0.3 5.5 V FB to PGND1, PGND2 –0.3 16 V PGOOD to PGND1, PGND2 0 20 V Output Voltage SW to PGND1, PGND2(2) –0.3 VIN + 0.3 V VCC to PGND1, PGND2 –0.3 5.5 V Current PGOOD sink current 10 mA TJ Junction temperature –40 150 °C Tstg Storage temperature –40 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) A voltage of 2V below PGND and 2V above VIN can appear on this pin for ≤ 200ns with a duty cycle of ≤ 0.01%.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) Device HBM Classification Level 2 ±2000 V Charged device model (CDM), per AEC Q100-011 Device CDM Classification Level C5 ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1) MIN NOM MAX UNIT Input voltage Input voltage range after start-up 3 36 V Input voltage BIAS pin operating voltage 12 V Output voltage Output voltage range for adjustable version(2) 1 0.95*VIN V Frequency Frequency adjustment range 200 2200 kHz Sync frequency Synchronization frequency range 200 2200 kHz Load current Output DC current range, LM63440-Q1(3) 0 4 A Load current Output DC current range, LM63460-Q1(3) 0 6 A Temperature Operating junction temperature TJ range –40 150 °C (1) Recommended operating conditions indicate conditions for which the device is intended to be functional. For detailed specifications and conditions, see Electrical Characteristics table. (2) Under no conditions should the output voltage be allowed to fall below zero volts. (3) Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See Application Information for details. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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6.4 Thermal Information

The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7 and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application. For example, the EVM for this device achieves an RθJA of 23.5℃/W. THERMAL METRIC(1) LM63460-Q1, LM63440-Q1 UNITRYF (VQFN)

22 PINS

RθJA Junction-to-ambient thermal resistance (LM63460-Q1 EVM)(3) 23.5 °C/W RθJA Junction-to-ambient thermal resistance (JESD 51-7)(2) 38.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 30.3 °C/W RθJB Junction-to-board thermal resistance 8.8 °C/W ΨJT Junction-to-top characterization parameter 1 °C/W ΨJB Junction-to-board characterization parameter 8.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7 and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application. (3) Refer to the LM63460-Q1 EVM User's Guide for board layout and additional information. For thermal design information please see the Application Information section.

6.5 Electrical Characteristics

6.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5V. VIN1 shorted to VIN2 = VIN. VOUT is the converter output voltage. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LDO AND VCC VCC Internal VCC voltage VBIAS > 3.4V, CCM operation(1) 3.3 V VBIAS = 3.1V, non-switching 3.1 VCC-UVLO Internal VCC undervoltage lockout VCC rising undervoltage threshold 3.6 V VCC-UVLO-HYST Internal VCC undervoltage lockout hysteresis Hysteresis below VCC-UVLO 1.1 V FEEDBACK VFB_acc Initial reference voltage accuracy VIN = 3.3V to 36V, TJ = 25°C, FPWM mode –1% 1% IFB Input current from FB to GND Adjustable versions only, VFB = 1V 1 50 nA OSCILLATOR fADJ Minimum adjustable frequency by RT pin RRT = 66.5kΩ 0.18 0.2 0.22 MHz Adjustable frequency by RT pin with 400kHz setting RRT = 33.2kΩ 0.36 0.4 0.44 MHz Maximum adjustable frequency by RT pin RRT = 5.76kΩ 1.98 2.2 2.42 MHz fS_SS Frequency span of spread spectrum operation – largest deviation from center frequency Spread spectrum active 2% fPSS Spread spectrum pattern frequency(1) Spread spectrum active, fSW = 2.1MHz 1.5 Hz MOSFETS RDS(on)HS Power switch on-resistance High-side MOSFET RDS(on) 41 82 mΩ RDS(on)LS Power switch on-resistance Low-side MOSFET RDS(on) 21 45 mΩ VBOOT-UVLO Voltage on CBOOT relative to SW that turns off the high-side switch 2.1 V CURRENT LIMITS IL-HS High-side switch current limit, LM63460-Q1(4) Duty cycle approaches 0% 8.9 10.3 11.5 A High-side switch current limit, LM63440-Q1(4) 6 7 8.1 IL-LS Low-side switch current limit, LM63460-Q1 6.1 7.1 8.1 A Low-side switch current limit, LM63440-Q1 4.0 4.8 5.4 IL-ZC Zero-cross current limit. Positive current direction is out of the SW pin AUTO mode, static measurement 0.25 A IL-NEG Negative current limit. Positive current direction is out of the SW pin, LM63460-Q1 FPWM operation ANegative current limit FPWM and SYNC Modes. Positive current direction is out of the SW pin, LM63440-Q1 IPK_MIN_0 Minimum peak command in AUTO mode / device current rating Pulse duration < 100ns 25% LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5V. VIN1 shorted to VIN2 = VIN. VOUT is the converter output voltage. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPK_MIN_100 Minimum peak command in AUTO mode / device current rating Pulse duration > 1µs 12.5% VHICCUP Ratio of FB voltage to in-regulation FB voltage Hiccup disabled during soft start 40% POWER GOOD PGDOV PGOOD upper threshold – rising % of VOUT setting 105% 107% 110% PGDUV PGOOD lower threshold – falling % of VOUT setting 92% 94% 96.5% PGDHYST PGOOD hysteresis % of VOUT setting 1.3% VIN(PGD-VALID) Input voltage for proper PGOOD function 1.0 V VPGD(LOW) Low-level PGOOD function output voltage 46µA pullup to PGOOD, VIN = 1V, VEN = 0V 0.4 V1mA pullup to PGOOD, VEN = 0V 0.4 2mA pullup to PGOOD, VEN = 3.3V 0.4 RPGD RDS(on) of PGOOD output 1mA pullup to PGOOD, VEN = 0V 17 40 Ω 1mA pullup to PGOOD, VEN = 3.3V 40 90 Ω IOV Pulldown current at the SW node in an overvoltage condition 0.5 mA THERMAL SHUTDOWN TSHD Thermal shutdown rising threshold(1) 158 168 180 ℃ TSHD-HYS Thermal shutdown hysteresis(1) 10 ℃ (1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested. (2) IQ_VIN = IQ + IBIAS × (VOUT / VIN) (3) This is the current used by the device while not switching, open loop, with FB pulled to +5% above nominal. It does not represent the total input current to the converter while regulating. (4) High-side current limit is a function of duty cycle. High-side current limit value is highest at small duty cycle and less at higher duty cycle. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LM63440-Q1 LM63460-Q1

6.6 Timing Characteristics

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6.7 Systems Characteristics

The following values are specified by design provided that the component values in the typical application circuit are used. Limits apply over the junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and Maximum limits are derived using test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EFFICIENCY ƞ5V_2p1MHz Typical 2.1MHz efficiency VOUT = 5V, IOUT = 6A, LM63460-Q1 92.5% VOUT = 5V, IOUT = 4A, LM63440-Q1 93% VOUT = 5V, IOUT = 100µA, RFBT = 1MΩ 73% ƞ3p3V_2p1MHz Typical 2.1MHz efficiency VOUT = 3.3V, IOUT = 6A, LM63460-Q1 90% VOUT = 3.3V, IOUT = 4A, LM63440-Q1 91% VOUT = 3.3V, IOUT = 100µA, RFBT = 1MΩ 71% ƞ5V_400kHz Typical 400kHz efficiency VOUT = 5V, IOUT = 6A, LM63460-Q1 93.6% VOUT = 5V, IOUT = 4A, LM63440-Q1 95% VOUT = 5V, IOUT = 100µA, RFBT = 1MΩ 76% RANGE OF OPERATION VVIN_MIN1 VIN for full functionality at reduced load, after start-up VOUT set to 3.3V 3.0 V VVIN_MIN2 VIN for full functionality at 100% of maximum rated load, after start-up VOUT set to 3.3V 3.95 V IQ-VIN Operating quiescent current(1) VOUT = 3.3V, IOUT = 0A, AUTO mode, RFBT = 1MΩ 7 µA VOUT = 5V, IOUT = 0A, AUTO mode, RFBT = 1MΩ 10 VDROP1 Input-to-output voltage differential to maintain regulation accuracy without inductor DCR drop VOUT = 3.3V, IOUT = 4A, –3% output accuracy at 25°C 0.4 V VOUT = 3.3V, IOUT = 4A, –3% output accuracy at 125°C 0.55 VDROP2 Input-to-output voltage differential to maintain fSW ≥ 1.85MHz, without inductor DCR drop VOUT = 3.3V, IOUT = 4A, –3% regulation accuracy at 25°C 0.8 V VOUT = 3.3V, IOUT = 4A, –3% regulation accuracy at 125°C 1.2 DMAX Maximum switch duty cycle fSW = 1.85MHz 87% While in frequency foldback 98% (1) See detailed Input Supply Current for the meaning of this specification and how it can be calculated. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LM63440-Q1 LM63460-Q1

6.8 Typical Characteristics

Unless otherwise specified, VIN = 13.5V and fSW = 2.1MHz. J u n c t i o n T e m p e r a t u r e (  C ) Nonswitching Quiescent Current (A) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 2 1 6 VBIAS = 5V Figure 6-1. Non-Switching Input Supply Current I n p u t V o l t a g e ( V ) Shutdown Current (A) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 T J = - 4 0  C T J = 2 5  C T J = 1 5 0  C VEN/SYNC = 0V Figure 6-2. Shutdown Supply Current J u n c t i o n T e m p e r a t u r e ( ° C ) FB Voltage (V) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 0 . 9 9 0 . 9 9 5 1 . 0 0 5 1 . 0 1 Figure 6-3. Feedback Voltage J u n c t i o n T e m p e r a t u r e (  C ) Current Limit (A) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 0 1 2 P e a k V a l l e y Figure 6-4. High-Side and Low-Side Current Limits J u n c t i o n T e m p e r a t u r e ( ° C ) Switching Frequency (kHz) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 4 0 0 8 0 0 1 2 0 0 1 6 0 0 2 0 0 0 2 4 0 0 f S W = 2 0 0 k H z f S W = 4 0 0 k H z f S W = 2 . 2 M H z Figure 6-5. Switching Frequency Set by RT Resistor J u n c t i o n T e m p e r a t u r e ( ° C ) MOSFET RDS(on)(m) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 H i g h - s i d e M O S F E T L o w - s i d e M O S F E T Figure 6-6. High-Side and Low-Side MOSFET RDS(on) LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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6.8 Typical Characteristics (continued)

Unless otherwise specified, VIN = 13.5V and fSW = 2.1MHz. J u n c t i o n T e m p e r a t u r e ( ° C ) Enable Threshold Voltage (V) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 0 . 2 5 0 . 5 0 . 7 5 1 . 2 5 1 . 5 V E N R i s i n g V E N F a l l i n g V E N _ W A K E R i s i n g V E N _ W A K E F a l l i n g Figure 6-7. Enable Thresholds J u n c t i o n T e m p e r a t u r e ( ° C ) PGOOD Thresholds (%) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 8 0 8 5 9 0 9 5 1 0 0 1 0 5 1 1 0 1 1 5 O V T r i p p i n g O V R e c o v e r y U V R e c o v e r y U V T r i p p i n g Figure 6-8. PGOOD Thresholds www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM63440-Q1 LM63460-Q1

7 Detailed Description

7.1 Overview

The LM634x0-Q1 is an easy-to-use, synchronous, buck DC/DC converter designed for a wide variety of automotive applications where strict reliability and low EMI are of paramount importance. The devices operates over an input voltage range of 3.95V to 36V, with operation down to 3V after start-up and transients as high as 42V. The LM63460-Q1 delivers up to 6A DC while the LM63440-Q1 delivers 4A DC load current with high conversion efficiency and ultra-low input quiescent current in a very small design size. The LM634x0-Q1 has a programmable switching frequency between 200kHz to 2.2MHz using the RT pin, including sub-AM band at 400kHz and above the AM band at 2.1MHz. The converter includes specific features for optimal EMI performance in noise-sensitive automotive applications, such as:

An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI.
Parallel input paths with a symmetrical capacitor layout minimize parasitic inductance, switch-voltage ringing, and radiated field coupling.
Pseudo-random spread spectrum (PRSS) modulation reduces peak emissions.
Frequency synchronization and optional FPWM mode enable constant switching frequency across the full load current range.
Integrated high-side and low-side power MOSFETs with enhanced gate-drive control enable low-noise PWM switching. Together, these features significantly reduce EMI filtering requirements, thus eliminating shielding and other expensive EMI mitigation measures, while helping to meet the CISPR 25 Class 5 automotive EMI standard for conducted and radiated emissions. The enhanced HotRod QFN package of the LM634x0-Q1 has a carefully designed wettable-flank pinout arrangement that provides additional clearance spacing between adjacent VIN, SW, or PGND power pins to improve reliability and pin FMEA . The converter also incorporates other features for comprehensive system requirements, including:
A precision enable input with hysteresis for programmable line undervoltage lockout (UVLO)
Cycle-by-cycle peak and valley current limits for excellent inductor sizing
An open-drain power-good monitor for power-rail sequencing and fault reporting
Internally fixed output voltage soft start
Monotonic start-up into prebiased loads
Thermal shutdown with automatic recovery The LM634x0-Q1 is qualified to AEC-Q100 grade 1 and has electrical characteristics specified up to a maximum junction temperature of 150°C. The following help provide an excellent point-of-load regulator design for automotive applications requiring enhanced reliability and durability:
Wide input voltage range
Low quiescent current consumption
Optimized thermal design and high-temperature operation
Improved pin FMEA
Small design size LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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7.2 Functional Block Diagram

LS current senseVout UV/OV LS current min FPWM / AUTO FPWM / AUTO www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LM63440-Q1 LM63460-Q1

7.3 Feature Description

7.3.1 Input Voltage Range (VIN1, VIN2)

With a steady-state input voltage range from 3V to 36V, the LM634x0-Q1 is intended for step-down conversions from typical 12V and 24V automotive supply rails. The schematic circuit in Figure 7-1 shows all the necessary components to implement an LM634x0-Q1 step-down regulator using a single input supply. PGOOD EN/SYNC RT PGND1 GND VCC CBOOT SW FB BIAS VIN1 PGND2 VIN2 CVCC CIN-HF1 CIN-HF2 CIN2 CBOOT COUT RFBB LOLM63460-Q1 RRT CIN1 IOUT(max) = 6 A VIN = 3 V to 36 V RFBT RFFCFF RENT RENB CSYNC SYNC optional Optional external bias Optional feedforward network Precision enable for VIN UVLO Synchronization (200 kHz to 2.2 MHz) RPG VCC PGOOD indicator VOUT = 1 V to 95% VIN Figure 7-1. LM63460-Q1 Schematic Diagram with Input Voltage Operating Range of 3V to 36V The minimum input voltage required for start-up is 3.95V. Take extra care to make sure that the voltage at the VIN pins of the converter (VIN1 and VIN2) does not exceed the absolute maximum voltage rating of 42V during line or load transient events. Voltage ringing at the VIN pins that exceeds the Absolute Maximum Ratings can damage the IC.

7.3.2 Output Voltage Setpoint (FB)

While dependent on switching frequency and load current levels, the LM634x0-Q1 is generally capable of providing an output voltage in the range of 1V to a maximum of slightly less than the input voltage. Define the output voltage setpoint with feedback resistors designated as RFBT and RFBB as shown in Figure 7-1. The LM634X0-Q1 uses a 1V reference voltage, and the internal error amplifier regulates the FB voltage to be equal to the reference voltage. Use Equation 1 to determine R FBB for a desired output voltage setpoint and a given value of RFBT. (1) While RFBT is generally in the range of 10kΩ to 1MΩ, use a value of 100kΩ for improved noise immunity (relative to higher resistances such as 1MΩ) and reduced current consumption (compared to lower resistance values).

7.3.3 Precision Enable and Input Voltage UVLO (EN/SYNC)

The EN/SYNC input supports adjustable input undervoltage lockout (UVLO) programmed by resistor values for application-specific power-up and power-down requirements. Also, an external logic signal can be used to drive the EN/SYNC input to toggle the output ON or OFF and for system sequencing or protection. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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The LM634x0-Q1 enters a low-I Q shutdown mode when EN/SYNC is pulled below 0.4V. The internal LDO regulator powers off, shutting down the bias currents of the LM634x0-Q1. When the EN/SYNC voltage is between the hard shutdown and the precision enable thresholds, the LM634x0-Q1 operates in standby mode with the VCC voltage in regulation. After the voltage at EN/SYNC is above VEN-TH, the converter begins to switch normally, provided the input voltage drives the internal VCC above the rising UVLO threshold of 3.6V (typical). The EN/SYNC pin cannot be left floating. The simplest way to enable operation is to connect the EN/SYNC pin to VIN, allowing self-start-up of the LM634x0-Q1. However, many applications benefit from the use of a divider network from VIN to EN/SYNC as shown in Figure 7-1 , which establishes a precision input voltage UVLO. This can be used for sequencing, to prevent re-triggering of the device when used with long input cables, or to reduce the occurrence of deep discharge of a battery power source. Note that the precision enable threshold, V EN-TH, has a 28% hysteresis to prevent ON/OFF re-triggering. An external logic output of another IC can also be used to drive EN/SYNC, allowing system power sequencing. Calculate the resistor divider values using Equation 2. See Input Voltage UVLO for additional information. (2) where

VIN(on) is the required input voltage turn-on threshold. Note that EN/SYNC can also be used as an external synchronization clock input. A blanking time, t B, is applied to the enable logic after a clock edge is detected. Any logic change within the blanking time is ignored. The blanking time is not applied when the converter is in shutdown mode. The blanking time ranges from 4µs to 28µs. To effectively disable the output, the EN/SYNC input must stay low for longer than 28µs.

7.3.4 Frequency Synchronization (EN/SYNC)

Use the EN/SYNC pin of the LM634X0-Q1 to synchronize the internal oscillator to an external clock signal ranging from 200kHz to 2.2MHz. The internal oscillator can be synchronized by AC coupling a positive clock edge to EN/SYNC, as shown in Figure 7-1. TI recommends to keep the parallel combination value of R ENT and R ENB in the 100k Ω range. R ENT is required for synchronization, but R ENB can be left unmounted. The external clock must be off before start-up to allow proper start-up sequencing. Referring to Figure 7-2, the AC-coupled voltage edge at EN/SYNC must exceed the SYNC amplitude threshold, VEN_SYNC, to trip the internal synchronization pulse detector. In addition, the minimum EN/SYNC rising pulse and falling pulse durations must be longer than t SYNC_EDGE and shorter than the blanking time, t B. A 3.3V or higher amplitude pulse signal coupled through a 1nF capacitor, CSYNC, is suggested. VEN/SYNC EN/SYNC Voltage tSYNC_EDGE tSYNC_EDGE VEN_SYNC Figure 7-2. Typical Synchronization Waveform Applied to EN/SYNC www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LM63440-Q1 LM63460-Q1

After a valid synchronization signal is applied for 2048 cycles, the clock frequency quickly changes to that of the applied signal. Synchronization overrides spread spectrum, turning it off.

7.3.5 Clock Locking

A clock locking procedure initiates after a valid synchronization signal is detected. The LM634x0-Q1 receives this signal at the EN/SYNC pin. After approximately 2048 pulses, the clock frequency completes a smooth transition to the frequency of the synchronization signal without output voltage variation. Note that when the frequency is adjusted suddenly, the phase is maintained so the clock cycle that lies between operation at the default frequency and at the synchronization frequency is of intermediate length. This action eliminates very long or very short pulses. After the frequency is adjusted, the phase is adjusted over a few tens of cycles so that rising synchronization edges correspond to rising switch (SW) node pulses. See Figure 7-3. VSYNCDH VSYNCDL Pulse 1 Pulse 2 Pulse 3 Pulse 4 Phase lock achieved, Rising edges align to within approximately 45 ns, no spread spectrum VIN GND Pulse ~2048 Pulse ~2049 Pulse ~2050 Pulse ~2051 SW Node Synchronization signal Spread Spectrum is on between pulse 1 and approximately pulse 2048, there is no change to operating frequency On approximately pulse 2048, spread spectrum turns off Also clock frequency matches the synchronization signal and phase locking begins The synchronization signal is detected after four pulses. The converter is ready to synchronize after approximately 2048 pulses, and the frequency is adjusted using a glitch-free technique. Phase locking is subsequently achieved. Figure 7-3. Synchronization Process Note also that the LM634x0-Q1 turns on spread spectrum after the first edge in the synchronization pulse. See the EN/SYNC pin description in Pin Configuration and Functions . Upon adjustment of the frequency at the approximate 2048 th pulse, spread spectrum is turned off. Finally, if the converter runs at reduced switching frequency due to low or high input voltage or during current limit, frequency lock does not occur until the condition causing low-frequency operation has been removed.

7.3.6 Adjustable Switching Frequency (RT)

Connect a resistor from RT to GND to set the switching frequency. Use Equation 3 or refer to Figure 7-4 for resistor values. Note that a resistor value outside of the recommended range can cause the device to shut down. This prevents unintended operation if RT is shorted to ground or left open. Do not apply a pulsed signal to this pin to force synchronization. If synchronization to an external clock is required, refer to Section 7.3.4. (3) F r e q u e n c y ( k H z ) RT Resistance (k) 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0 1 8 0 0 2 0 0 0 2 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 Figure 7-4. Setting the Switching Frequency LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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7.3.7 Power-Good Monitor (PGOOD)

The PGOOD function is implemented to replace a discrete reset device, reducing BOM count and cost. The PGOOD voltage goes low when the feedback (FB) voltage is outside of the specified PGOOD thresholds (see Figure 6-8 ). This can occur during current limit and thermal shutdown, as well as when disabled and during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions that are shorter than t PGDFLT(fall) do not trip the PGOOD flag. Refer to Figure 7-5 to best understand PGOOD operation. The PGOOD output consists of an open-drain N-channel transistor, requiring an external pullup resistor to a suitable logic supply or V OUT. When EN is pulled low, the flag output is also forced low. With EN low, PGOOD remains valid as long as the input voltage is above 1V (typical). Input Voltage Input Voltage Output Voltage VPGD_UV (falling) VPGD_HYST VIN_OPERATE (rising) VIN(PGD_VALID) GND < 18 V VIN_OPERATE (falling) PGOOD PGOOD may not be valid if input is below VIN(PGD_VALID) Startup delay PGOOD may not be valid if input is below VIN(PGD_VALID) Small glitches do not reset tPGDFLT(rise) timer Small glitches do not cause PGOOD to signal a fault tPGDFLT(rise) tPGDFLT(fall) tPGDFLT(fall) tPGDFLT(rise) tPGDFLT(fall) tPGDFLT(fall) Figure 7-5. PGOOD Timing Diagram (Excludes OV Events) Table 7-1. Conditions That Cause PGOOD to Signal a Fault (Pull Low) FAULT CONDITION INITIATED FAULT CONDITION ENDS (AFTER WHICH tPGDFLT(rise) MUST PASS BEFORE PGOOD OUTPUT IS RELEASED)(1) VOUT < VOUT-target × PGDUV AND t > tPGDFLT(fall) Output voltage in regulation: VOUT-target × (PGDUV + PGDHYST) < VOUT < VOUT-target × (PGDOV – PGDHYST) (see Figure 6-8) VOUT > VOUT-target × PGDOV AND t > tPGDFLT(fall) Output voltage in regulation TJ > TSHD TJ < TSHD-F AND output voltage in regulation VEN < VEN-TH falling VEN > VEN-TH rising AND output voltage in regulation VCC < VCC-UVLO - VCC-UVLO-HYST VCC > VCC-UVLO AND output voltage in regulation (1) As an additional operational check, PGOOD remains low during the soft-start time, which is defined as the time for the output voltage to reach the setpoint or tSS2 has passed since initiation (whichever is lower).

7.3.8 Bias Supply Regulator (VCC, BIAS)

VCC is the output of the internal LDO subregulator used to supply the control circuits of the LM634x0-Q1. The nominal VCC voltage is 3.3V. The BIAS pin is the input to the internal LDO. This input can be connected to V OUT to provide the lowest possible input supply current. If the BIAS voltage is less than 3.1V, VIN1 and VIN2 directly power the internal LDO. To prevent unsafe operation, VCC has UVLO protection that prevents switching if the internal voltage is too low. See VCC-UVLO and VCC-UVLO-HYST in the Electrical Characteristics . Note that these UVLO levels and the dropout voltage of the LDO are used to derive the minimum VIN_OPERATE and VIN_OPERATE_H values. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LM63440-Q1 LM63460-Q1

7.3.9 Bootstrap Voltage and UVLO (CBOOT)

The gate driver of the high-side (HS) switch requires a bias voltage higher than V IN. The bootstrap capacitor, CBOOT, connected between CBOOT and SW, works as a charge pump to boost the voltage on CBOOT to a level of VCC above the SW voltage. The LM634x0-Q1 has an integrated bootstrap diode to minimize external component count. Use a 100nF bootstrap capacitor rated for 10V or higher. The V BOOT-UVLO threshold (2.1V typical) is designed to maintain proper HS switch operation. If the bootstrap capacitor voltage drops below VBOOT-UVLO, then the converter initiates a charging sequence, turning on the low-side switch before attempting to turn on the HS switch.

7.3.10 Spread Spectrum

The purpose of spread spectrum is to eliminate peak emissions at specific frequencies by spreading these emissions across a wider range of frequencies. In most systems containing the LM634x0-Q1, low-frequency conducted emissions from the first few harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of the emissions at higher harmonics that fall in the FM frequency band. These harmonics often couple to the environment through electric fields around the switch node and inductor. The LM634x0-Q1 uses a ±2% spread of frequencies, which can spread energy smoothly across the FM and TV bands but is small enough to limit subharmonic emissions below the converter switching frequency. Peak emissions at the switching frequency of the converter are only reduced slightly, by less than 1dB, while peaks in the FM band are typically reduced by more than 6dB. The LM634x0-Q1 uses a cycle-to-cycle frequency hopping method based on a linear feedback shift register (LFSR). This intelligent pseudo-random generator limits cycle-to-cycle frequency changes to limit output ripple. The pseudo-random pattern repeats at less than 1.5Hz, which is below the audio band. Spread spectrum is only available while the clock of the LM634x0-Q1 is free running at the natural frequency. Any of the following conditions overrides spread spectrum, turning it off:

The clock is slowed when operating in dropout.
The clock is slowed at light load in AUTO mode. In FPWM mode, spread spectrum is active even if there is no load.
At a high-input-voltage to low-output-voltage conversion ratio when the device operates at the minimum on time, the internal clock is slowed, disabling spread spectrum. Refer to the Timing Characteristics for more detail.
The clock is synchronized to an external clock signal.

7.3.11 Soft Start and Recovery From Dropout

The converter uses a reference-based soft start that prevents output voltage overshoot and large inrush current during start-up. Soft start is triggered by any of the following conditions:

Power is applied to the VIN pins of the IC, releasing UVLO.
EN/SYNC goes high to turn on the device.
Recovery from a hiccup-waiting period
Recovery from thermal shutdown protection After soft start is triggered, the IC takes the following actions:
The reference used by the IC to regulate the output voltage is slowly ramped. The net result is that the output voltage takes tSS to reach 90% of the desired value.
The operating mode is set to AUTO, activating diode emulation. This action allows a pre-biased start-up without pulling the output voltage low if there is a voltage already present on the output. Together, these actions provide start-up with limited inrush currents and also facilitate the use of high output capacitance and higher loading conditions that cause the peak inductor current to border on current limit during start-up without triggering hiccup. See Figure 7-6. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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V 90% of VOUT setpoint

0 V tSS2

Triggering event If selected, FPWM is enabled after regulation but no later than tSS2 tEN VEN VOUT setpoint EN and VOUT voltages t VOUT V 90% of VOUT setpoint Triggering event If selected, FPWM is enabled after regulation but no later than tSS2 tEN (a) (b) Soft start functions with the output voltage starting from 0V in (a), or if there is already a prebiased output as shown in (b). In either case, the output voltage must reach within 10% of the setpoint within tSS after soft start initiates. FPWM and hiccup are disabled during soft start, with both FPWM and hiccup enabled after the output voltage reaches regulation or after the tSS2 time interval expires, whichever happens first. Figure 7-6. Soft-Start Operation Any time the output voltage falls more than a few percent, the output voltage ramps up slowly. This condition is called recovery from dropout and differs from soft start in three important ways:

The reference voltage is set to approximately 1% above what is needed to achieve the preset output voltage setpoint.
Hiccup is allowed if the output voltage is less than 40% of the nominal setpoint. Note that during dropout regulation, hiccup is inhibited.
FPWM mode is allowed during recovery from dropout. If the output voltage were to suddenly be pulled up by an external supply, the converter can pull down on the output. Despite being called recovery from dropout, this feature is active whenever the output voltage drops to a few percent lower than the setpoint. This action primarily occurs under the following conditions:
Dropout: When there is insufficient input voltage to maintain the desired output voltage
Overcurrent: When there is an overcurrent event that is not severe enough to trigger hiccup VIN VOUT Set Point Input and Output Voltage Slope the same as during soft start Time t VOUT V Whether the output voltage falls due to high load current or low input voltage, after the condition that causes the output to fall below the setpoint is removed, the output recovers at the same rate as during start-up. Even though hiccup does not trigger due to dropout, it can, in principle, be triggered during recovery if output voltage is below 40% of the output voltage setpoint for more than 128 clock cycles. Figure 7-7. Recovery From Dropout

7.3.12 Overcurrent and Short-Circuit Protection

The converter protects from overcurrent conditions with cycle-by-cycle current limiting on both the high-side and the low-side MOSFETs. High-side MOSFET overcurrent protection is implemented by nature of peak-current mode control. The HS switch current is sensed when the HS switch is turned on after a short blanking time. Every switching cycle, this switch current is compared to the minimum of a fixed current setpoint or the output of the voltage regulation loop minus slope compensation. Because the voltage loop output has a maximum value www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LM63440-Q1 LM63460-Q1

and slope compensation increases with duty cycle, the HS current limit decreases with increased duty cycle when the duty cycle is above 35%. See Figure 7-8. D u t y C y c l e Command Current (A) 0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 0 1 2 H S S w i t c h M a x C u r r e n t R a t e d O u t p u t C u r r e n t Figure 7-8. HS Switch Maximum Current as a Function of Duty Cycle for the LM63460-Q1 When the LS switch is turned on, the switch current is also sensed and monitored. Like the HS device, the LS switch turns off as commanded by the voltage control loop and low-side current limit. If the LS switch current is higher than I L-LS at the end of a switching cycle, the switching cycle is extended until the LS current reduces below the limit. The LS switch is turned off after the LS current falls below the limit, and the HS switch is turned on again as long as at least one clock period has passed since the last time the HS device has turned on. iL VSW IL-LS Inductor current t t SW voltage VIN Typically, tSW > clock setting tON < tON(max) IL-HS IOUT Figure 7-9. Current Limit Waveforms Because the current waveform assumes values between I L-HS and I L-LS, the maximum output current is very close to the average of these two values. Hysteretic control is used and current does not increase as output voltage approaches zero. The converter employs hiccup overcurrent protection if there is an extreme overload, and the following conditions are met for 128 consecutive switching cycles:

The output voltage is below approximately 0.4 times the output voltage setpoint.
Greater than tSS2 has passed since soft start has started; see Soft Start and Recovery from Dropout .
The converter is not operating in dropout, which is defined as having minimum off time controlled duty cycle. In hiccup mode, the device shuts down and attempts to soft start after t W. Hiccup mode helps reduce the device power dissipation under severe overcurrent conditions and short circuits. See Figure 7-10. After the overload is removed, the device recovers as though in soft start; see Figure 7-11. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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Figure 7-10. Inductor Current Bursts During Hiccup VOUT 2 V/DIV 20 ms/DIV IL 5 A/DIV Figure 7-11. Short-Circuit Recovery

7.3.13 Thermal Shutdown

Thermal shutdown prevents the device from extreme junction temperatures by turning off the internal switches when the IC junction temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C. After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 158°C. When the junction temperature falls below 158°C (typical), the converter attempts to soft start. While the converter is shut down due to high junction temperature, power continues to be provided to VCC. To prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced current limit while the converter is disabled due to high junction temperature. The VCC current limit is reduced to a few milliamperes during thermal shutdown.

7.3.14 Input Supply Current

The converter is designed to have very low input supply current when regulating at light loads. This is achieved by powering much of the internal circuits from the output. The BIAS pin is the input to the LDO that powers the majority of the control circuits. By connecting BIAS to the regulator output, a small amount of current is drawn from the output. This current is reduced at the input by the ratio of V OUT / V IN. Equation 4 defines the current consumed by the operating (switching) buck converter at no load: (4) where

IQ_VIN is the current into the VIN pins – see the Electrical Characteristics .
IEN is current into the EN/SYNC pin – see the Electrical Characteristics . Include this current if EN/SYNC is connected to VIN. Note that this current drops to a very low value if EN/SYNC connects to a voltage less than 5V.
IDIV is the current consumption of the feedback divider used to set output voltage.
ηeff is the light-load efficiency when IQ_VIN is removed from the input current of the buck converter. ηeff = 0.8 is a conservative value that can be used under normal operating conditions. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LM63440-Q1 LM63460-Q1

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN/SYNC pin provides electrical ON and OFF control of the device. When the EN/SYNC voltage is less than 0.4V, both the regulator and the internal LDO have no output voltage. The converter is in shutdown mode, and the quiescent current drops to 0.6µA typical.

7.4.2 Standby Mode

The internal LDO has a lower enable threshold than the output of the converter. When the EN/SYNC pin voltage is above 1.1V (maximum) and below the precision enable threshold, the internal LDO regulates the VCC voltage at 3.3V typical. The precision enable circuitry is ON after VCC is above the UVLO. The internal power MOSFETs remain off unless the voltage on EN/SYNC goes above the precision enable threshold. The converter also employs UVLO protection. If the VCC voltage is below the UVLO level, the output of the converter is turned off.

7.4.3 Active Mode

The converter is in active mode whenever the EN/SYNC voltage is above the threshold voltage, V IN, is high enough to satisfy V IN_OPERATE, and no other fault conditions are present. The simplest way to enable operation is to connect EN/SYNC to VIN, which allows self start-up when the applied input voltage exceeds the minimum VIN_OPERATE. In active mode, depending on the load current, input voltage, and output voltage, the converter is in one of five modes:

Continuous conduction mode (CCM) with fixed switching frequency when the load current is above half of the inductor current ripple.
AUTO mode – Light-load operation with PFM where the switching frequency decreases at very light load.
FPWM mode – Light-load operation that maintains constant switching frequency across the full load range.
Minimum on time: The switching frequency reduces to maintain regulation with high step-down conversion ratios, that is, high input voltage to low output voltage.
Dropout mode: The switching frequency reduces to minimize the dropout voltage.

7.4.3.1 CCM Mode

The following operating description of the converter refers to the Functional Block Diagram and to the waveforms in Figure 7-12. In CCM, the converter supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on time, the SW voltage, VSW, swings up to approximately V IN, and the inductor current, i L, increases with a linear slope. The HS switch is turned off by the control logic. During the HS switch off time, t OFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces V SW to swing below ground by the voltage drop across the LS switch. The control loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on time of the HS switch over the switching period: D = tON / tSW (5) In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN (6) LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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–IOUT RDS(on)LS D = tON tSW VOUT VIN iL VSW ILPK IOUT ILripple Inductor current t t SW voltage VIN tSW tON tOFF Figure 7-12. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

7.4.3.2 AUTO Mode – Light-Load Operation

The converter can have two behaviors while lightly loaded. AUTO mode operation allows for a seamless transition between normal current-mode operation while heavily loaded and in highly efficient light-load operation. The other behavior, called FPWM mode, maintains full frequency even when unloaded. Which mode the converter operates in depends on which factory option is employed. See Section 4 . Note that the converter operates in FPWM mode when synchronizing frequency to an external clock signal. In AUTO mode, the converter employs two techniques to improve efficiency during light-load operation:

Diode emulation, which allows DCM operation
Switching frequency reduction Note that while these two features operate together to create excellent light-load behavior, the features operate independently of each other.

7.4.3.2.1 Diode Emulation

Diode emulation prevents reverse current through the inductor, which requires a lower frequency to regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced. With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to maintain regulation. D = tON tSW VOUT VIN iL VSW ILPK IOUT Inductor current t t SW voltage VIN tSW tON tOFF tHIGHZ In AUTO mode, the low-side MOSFET is turned off after the inductor current is near zero. As a result, after the output current is less than half of what the inductor ripple is in CCM, the converter operates in DCM and diode emulation is active. Figure 7-13. PFM Mode Operation at Light Loads www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LM63440-Q1 LM63460-Q1

The converter has a minimum peak inductor current setting while operating in AUTO mode. After current is reduced to a low value with fixed input voltage, the on time remains constant. Regulation is then achieved by adjusting the switching frequency. This mode of operation is called PFM mode regulation.

7.4.3.2.2 Frequency Foldback

The converter reduces the switching frequency whenever the output voltage is higher than the setpoint. This function is enabled whenever COMP, an internal signal, is low and there is an offset between the FB regulation setpoint and the voltage applied at FB. The net effect is that there is a larger output impedance while lightly loaded in AUTO mode than in normal operation. The output voltage is approximately 1% high when the converter is completely unloaded. 1% Above Set point VOUT Set Point Output Voltage Current Limit VOUT Output Current IOUT0 In AUTO mode, after the output current drops below approximately 1/10th the rated current of the converter, the output resistance increases so that output voltage is 1% high while the converter is completely unloaded. Figure 7-14. Steady-State Output Voltage Versus Output Current in AUTO Mode In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed on V OUT. If the DC offset on V OUT is not acceptable, use a dummy load at the output or select FPWM mode to reduce or eliminate this offset.

7.4.3.3 FPWM Mode – Light-Load Operation

Like AUTO mode operation, FPWM mode is selected as a factory option. FPWM applies by default during synchronization. In FPWM mode, the switching frequency is maintained constant while lightly loaded by allowing negative current to flow in the inductor. Negative current is limited to –3A for LM63460-Q1 and –2A for LM63440- Q1 devices by a reverse current limit circuit. D = tON tSW VOUT VIN iL VSW ILPK IOUT ILripple Inductor current t t SW voltage VIN tSW tON tOFF In FPWM mode, continuous conduction (CCM) is possible even if IOUT is less than half of Iripple. Figure 7-15. FPWM Mode Operation Frequency reduction is still available in FPWM mode if the output voltage is high enough to command minimum on time even while lightly loaded, allowing good behavior during faults that involve the output being pulled up. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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7.4.3.4 Minimum On-Time (High Input Voltage) Operation

The converter continues to regulate the output voltage even if the input-to-output voltage ratio requires an on time less than the minimum on time of the converter with a given clock setting. This is accomplished using valley current control as shown in Figure 7-16. –IOUT RDS(on)LS D = tON tSW VOUT VIN iL VSW ILVLY IOUT ILripple Inductor current t t SW voltage VIN tSW > clock setting tON = tON(min) tOFF In valley control mode, the inductor valley current is regulated, not inductor peak current. Figure 7-16. Valley Current Operation At all times, the compensation circuit dictates maximum peak and valley inductor currents. If for any reason, the valley current setpoint is exceeded, the clock cycle is extended until the valley current falls below that determined by the compensation circuit. If the converter is not operating in current limit, the maximum valley current is set above the peak inductor current, preventing valley control from being used unless there is a failure to regulate solely using peak current. If the input-to-output voltage ratio is too high, even though current exceeds the peak value dictated by compensation, the high-side switch cannot be turned off quickly enough to regulate the output voltage. As a result, the compensation circuit reduces both peak and valley currents. After a low enough current is established, the valley inductor current matches that being commanded by the compensation circuit. Under these conditions, the low-side switch is kept on and the next clock cycle is delayed until the inductor current drops below the desired valley current threshold. Because the on time is fixed at the minimum value, this type of operation resembles that of a device using a constant on-time (COT) control scheme.

7.4.3.5 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires the switching frequency to decrease to achieve the required duty cycle. At a given clock frequency, the duty cycle is limited by the converter minimum off time. After this limit is reached, if the clock frequency were maintained, the output voltage falls. Instead of allowing the output voltage to drop, the converter extends on time past the end of the clock cycle until the required peak inductor current is achieved. The clock is allowed to start a new cycle after the required peak inductor current is reached or after a pre-determined maximum on time, t ON(max), of approximately 9 µs passes. As a result, after the required duty cycle cannot be achieved at the selected clock frequency due to the minimum off-time requirement, the switching frequency decreases to maintain regulation. If the input voltage is low enough such that output voltage cannot be regulated even with an on time of t ON(max), the output voltage drops to slightly below the input voltage, VDROP1. See the Systems Characteristics . Refer to Figure 7-7 for additional information on recovery from dropout. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LM63440-Q1 LM63460-Q1

~100kHz VDROP1 Output Voltage VDROP2 if frequency =

1.85 MHz

Output voltage and switching frequency vs. input voltage: if there is little difference between the input voltage and output voltage setpoint, the converter reduces switching frequency to maintain regulation. If the input voltage is too low to provide the desired output voltage at approximately 110kHz, the output voltage tracks the input voltage. Figure 7-17. Switching Frequency and Output Voltage in Dropout iL VSW IOUT ILripple Inductor current –IOUT RDS(on)LS D = t t SW voltage tON tSW VIN tSW > clock setting tOFF = tOFF(min) tON < tON(max) VOUT VIN ILPK The inductor current takes longer than a normal clock period to reach the desired peak value, and consequently the switching frequency decreases to maintain regulation. This frequency reduction is limited by tON(max). Figure 7-18. Dropout Waveforms LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The LM63440-Q1 and LM63460-Q1 are synchronous buck converters that requires only a few external components to convert from a wide range of supply voltages to a fixed output voltage at an output current up to 6A. A comprehensive LM63440-Q1 or LM63460-Q1 quickstart calculator is available by download to expedite and streamline the process of designing of a LM63440-Q1 or LM63460-Q1 -based regulator circuit.

8.2 Typical Applications

For the circuit schematics, bill of materials, PCB layout files, and test results of an LM634x0-Q1 implementation, see the LM63460-Q1 EVM. 8.2.1 Design 1 – Automotive Synchronous 6A Buck Regulator at 2.1MHz Figure 8-1 shows the schematic diagram of a synchronous buck regulator with an output voltage set at 5V and a rated load current of 6A. In this example, the target half-load and full-load efficiencies are 94.5% and 92.5%, respectively, based on a nominal input voltage of 13.5V that ranges from 5V to 36V. The switching frequency is set at 2.1MHz with resistor R RT of 6.04kΩ. The BIAS input is connected to the 5V output, thus reducing IC bias power dissipation and improving efficiency performance. RT PGND1 GND VCC CBOOT SW FB BIAS VIN1 PGND2 VIN2 CVCC CIN-HF1 CIN-HF2 CIN2 CBOOT COUT RFBB LO LM63460-Q1 RRT CIN1 2 47 F 0.76 H 0.1 F 6.04 k 25.5 k 1 F 102 k 10 pF 1 k

10 F10 F

VOUT = 5 V IOUT = 6 A VIN = 5 V...36 V 10 nF10 nF RFBT RFFCFF Feedforward network PGOOD EN/SYNC RENT RENB CSYNC SYNC optional Precision enable for VIN UVLO Synchronization (200 kHz to 2.2 MHz) RPG VCC PGOOD indicator Optional external bias 100 k 365 k 100 k 1 nF Figure 8-1. Application Circuit 1 – 5V, 6A at 2.1MHz Note This application example is provided herein to showcase the LM63460-Q1 buck converter in several different implementation scenarios. Depending on the source impedance of the input supply bus, an electrolytic capacitor can be required at the input for stability, particularly at low input voltage and high output current operating conditions. See the Power Supply Recommendations for more detail. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LM63440-Q1 LM63460-Q1

8.2.1.1 Design Requirements

Table 8-1 shows the intended input, output, and performance parameters for this application example. The converter operates in dropout during cold crank when the input voltage decreases to 5V, with the output voltage slightly below the 5V setpoint. Table 8-1. Design Parameters DESIGN PARAMETER VALUE Input voltage range (for constant fSW) 6V to 18V Minimum transient input voltage, cold crank 5V Maximum transient input voltage, load dump 36V Output voltage and full-load current 5V, 6A Switching frequency 2.1MHz Output voltage regulation ±1% IC input current, no-load < 10µA IC shutdown current < 1µA Table 8-2 gives the selected buck converter power-stage components with availability from multiple vendors. This design uses a low-DCR inductor and all-ceramic output capacitor implementation. Table 8-2. List of Materials for Application Circuit 1 REF DES QTY SPECIFICATION VENDOR (1) PART NUMBER CIN 2 10µF, 50V, X7R, 1206, ceramic, AEC-Q200 Samsung CL31Y106KBKVPNE TDK CGA5L1X7R1H106K 10µF, 50V, X7S, 1210, ceramic, AEC-Q200 Murata GCM32EC71H106KA03 TDK CGA6P3X7S1H106M COUT 47µF, 6.3V, X7R, 1210, ceramic, AEC-Q200 Murata GCM32ER70J476KE19L 47µF, 10V, X7S, 1210, ceramic, AEC-Q200 TDK CGA6P1X7S1A476M Murata GCM32EC71A476KE02 3 22µF, 16V, X7R, 1210, ceramic, AEC-Q200 TDK CGA6P1X7R1C226M LO 1 1µH, 12mΩ, 11.6A, 4.1mm × 4.1mm × 3.1mm, AEC-Q200 Würth Electronik 74438357010 U1 1 LM63460-Q1 synchronous buck converter, AEC-Q100 Texas Instruments LM63460AASQRYFRQ1 (1) See the Third-Party Products Disclaimer. More generally, the LM63460-Q1 converter is designed to operate with a wide range of external components and system parameters. However, the integrated loop compensation is optimized for a certain range of buck inductance and output capacitance. As a starting point, Table 8-3 provides typical component values for several common application configurations. Table 8-3. Typical External Component Values fSW (kHz) VOUT (V) LO (µH) COUT-EFF(min) (µF) Typical COUT Components (1210, X7R) RFBT (kΩ) RFBB (kΩ) CFF (pF) RFF (kΩ) 2100 3.3 0.68 50 3 × 47µF, 6.3V or 4 × 22µF, 16V 100 43.2 10 1 2100 5 0.76 30 2 × 47µF, 10V or 3 × 22µF, 16V 100 24.9 10 1 400 1.8 2.2 120 3 × 100µF, 4V 80.6 100 22 1 400 3.3 3.3 70 3 × 47µF, 6.3V or 5 × 22µF, 16V 100 43.2 15 1 400 5 4.7 50 3 × 47µF, 10V or 4 × 22µF, 16V 100 24.9 15 1 400 12 6.8 20 3 × 22µF, 25V 100 9.09 4.7 1 LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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Note that the minimum output capacitances listed in Table 8-3 represents effective values for ceramic capacitors derated for DC bias voltage and temperature. 8.2.2 Design 2 – Automotive Synchronous 4A Buck Regulator at 2.1MHz Figure 8-2 shows the schematic diagram of a synchronous buck regulator with an output voltage set at 5V and a rated load current of 4A. In this example, the target half-load and full-load efficiencies are 94.25% and 94%, respectively, based on a nominal input voltage of 13.5V that ranges from 5V to 36V. The switching frequency is set at 2.1MHz with resistor R RT of 6.04kΩ. The BIAS input is connected to the 5V output, thus reducing IC bias power dissipation and improving efficiency performance. RT PGND1 GND VCC CBOOT SW FB BIAS VIN1 PGND2 VIN2 CVCC CIN-HF1 CIN-HF2 CIN2 CBOOT COUT RFBB LO LM63440-Q1 RRT CIN1 2 22 F 1.2 H 0.1 F 6.04k 25.5k 1 F 102k 10pF 1k VOUT = 5V IOUT = 4A VIN = 5V...36V 10nF10nF RFBT RFFCFF Feedforward network PGOOD EN/SYNC RENT RENB CSYNC SYNC optional Precision enable for VIN UVLO Synchronization (200kHz to 2.2MHz) RPG VCC PGOOD indicator Optional external bias 100k 365k 100k 1nF Figure 8-2. Application Circuit 2 – 5V, 4A at 2.1MHz Note This application example is provided herein to showcase the LM63440-Q1 buck converter in several different implementation scenarios. Depending on the source impedance of the input supply bus, an electrolytic capacitor can be required at the input for stability, particularly at low input voltage and high output current operating conditions. See the Power Supply Recommendations for more detail.

8.2.2.1 Design Requirements

The following table shows the intended input, output, and performance parameters for this application example. The converter operates in dropout during cold crank when the input voltage decreases to 5V, with the output voltage slightly below the 5V setpoint. Table 8-4. Design Parameters DESIGN PARAMETER VALUE Input voltage range (for constant fSW) 6V to 18V Minimum transient input voltage, cold crank 5V Maximum transient input voltage, load dump 36V Output voltage and full-load current 5V, 4A Switching frequency 2.1MHz Output voltage regulation ±1% IC input current, no-load < 10µA IC shutdown current < 1µA www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LM63440-Q1 LM63460-Q1

The following table gives the selected buck converter power-stage components with availability from multiple vendors. This design uses a low-DCR inductor and all-ceramic output capacitor implementation. Table 8-5. List of Materials for Application Circuit 2 REF DES QTY SPECIFICATION VENDOR (1) PART NUMBER CIN 2 10µF, 50V, X7R, 1206, ceramic, AEC-Q200 Samsung CL31Y106KBKVPNE TDK CGA5L1X7R1H106K 10µF, 50V, X7S, 1210, ceramic, AEC-Q200 Murata GCM32EC71H106KA03 TDK CGA6P3X7S1H106M COUT 1 47µF, 10V, X7S, 1210, ceramic, AEC-Q200 Murata GCM32EC71A476KE02 TDK CGA6P1X7S1A476M 2 22µF, 16V, X7S, 1206, ceramic, AEC-Q200 Murata GCM31CC71C226ME36 LO 1 U1 1 LM63440-Q1 synchronous buck converter, AEC-Q100 Texas Instruments LM63440AASQRYFRQ1 (1) See the Third-Party Products Disclaimer. More generally, the LM63440-Q1 converter is designed to operate with a wide range of external components and system parameters. However, the integrated loop compensation is optimized for a certain range of buck inductance and output capacitance. As a starting point, the following table provides typical component values for several common application configurations. Table 8-6. Typical External Component Values fSW (kHz) VOUT (V) LO (µH) COUT-EFF(min) (µF) TYPICAL COUT COMPONENTS (1210) RFBT (kΩ) RFBB (kΩ) CFF (pF) RFF (kΩ) 2100 3.3 0.68 30 2 × 22µF, 10V (X7R) or 1 × 47µF, 10V (X7S) 100 43.2 10 1 2100 5 0.82 20 1 × 47µF, 10V (X7S) 100 24.9 10 1 400 1.8 3.3 150 4 × 100µF, 4V (X7R) 80.6 100 47 1 400 3.3 4.7 75 2 × 47µF, 10V (X7S) or 4 × 22µF, 10V (X7R) 100 43.2 33 1 400 5 6.8 40 2 × 47µF, 10V (X7S) or 3 × 22µF, 16V (X7S) 100 24.9 22 1 400 12 8.2 20 2 × 22µF, 25V (X7S) 100 9.09 15 1 Note that the minimum output capacitances listed in Table 8-6 represents effective values for ceramic capacitors derated for DC bias voltage and temperature.

8.2.2.2 Detailed Design Procedure

The following design procedure applies to either schematic of Figure 8-1 or Figure 8-2.

8.2.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM63440-Q1 or LM63460-Q1 converter with WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2.2 Setting the Output Voltage

The LM63440-Q1 or LM63460-Q1 uses a feedback divider network to set the output voltage. The divider network comprises top and bottom feedback resistors designated as R FBT and R FBB, respectively. The resistances of the feedback divider are a compromise between excessive noise pickup and quiescent current consumption. Lower resistance values reduce noise sensitivity but also impact light-load efficiency. The recommended value for R FBT is 100k Ω with a maximum value of 1M Ω. If 1M Ω is selected for R FBT, then use a feedforward capacitor in parallel to provide adequate loop phase margin. Use Equation 1 to find RFBB for a given value of R FBT. Choosing R FBT and R FBB values of 102k Ω and 25.5k Ω, respectively, sets the output voltage at exactly 5V.

8.2.2.2.3 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall design size. Lower switching frequency implies reduced switching losses, resulting in higher system efficiency and less power dissipated in the converter. However, higher switching frequency enables the use of smaller inductors and capacitors, enabling a more compact design. Many automotive applications require that the AM radio band be strictly avoided. Such applications tend to operate at either 2.1MHz or 400kHz, above and below the AM band, respectively. To achieve small design size set the LM63440-Q1 or LM63460-Q1 switching frequency at 2.1MHz for this application example by installing a 6.04kΩ resistor from RT to GND.

8.2.2.2.4 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on the desired peak-to-peak ripple current, which is normally chosen to be in the range of 20% to 40% of the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load current for systems with a fixed input voltage. For systems with a variable input voltage such as the 12V automotive battery, 25% is commonly used. When selecting the ripple current for applications with lower maximum load than the maximum available from the device, the maximum device current must still be used. For the 4A device, use Equation 7 to determine the value of inductance. The constant K is the percentage of peak-to-peak inductor current ripple to rated output current. Choose K = 0.3 for this 5V, 4A, 2.1MHz example, resulting in an inductance of approximately 1.2µH. (7) For the 6A device, use Equation 8 to determine the value of inductance. The constant K is the percentage of peak-to-peak inductor current ripple to rated output current. Choose K = 0.3 for this 5V, 6A, 2.1MHz example, resulting in an inductance of approximately 0.8µH. (8) The saturation current rating of the inductor must be higher than the high-side switch current limit, I L-HS (see the Electrical Characteristics ). These requirements prevent inductor saturation during an overload condition on the www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LM63440-Q1 LM63460-Q1

output. While an output short-circuit condition causes the LM63440-Q1 or LM63460-Q1 to enter hiccup mode, an overload condition can hold the output current at current limit without triggering hiccup. When the inductor core material saturates, the inductance can fall to a low value, causing the inductor current to rise rapidly. Although the valley current limit, I L-LS, reduces the risk of current runaway, a saturated inductor causes the instantaneous current to increase to a high value. This can lead to component damage, avoiding inductor saturation is crucial. Inductors with a ferrite core material have hard saturation characteristics but usually have lower core losses than powdered iron cores. Powdered iron cores exhibit a soft saturation, allowing some relaxation in the current rating of the inductor. However, powdered iron cores typically have higher core losses at frequencies above 1MHz. To avoid subharmonic oscillation, the inductance value must not be less than that given by Equation 9 . The maximum inductance is limited by the minimum current ripple required for current-mode control to perform correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the converter maximum rated current under nominal conditions. (9) Equation 9 assumes that this design must operate with the input voltage near or in dropout. Use Equation 10 instead if the minimum input voltage for a given design is high enough to limit the duty cycle to less than 40%. (10)

8.2.2.2.5 Output Capacitor Selection

The value of the output capacitor and the ESR determine the output voltage ripple and load transient performance. The output capacitor is usually determined by load transient and stability requirements rather than the output voltage ripple. For LM63440-Q1, use Table 8-7 and for LM63460-Q1, use Table 8-8 to select the output capacitance and C FF feedforward capacitance values for a few common applications. Use a 1k Ω RFF in series with CFF to further improve noise performance. Table 8-7. Recommended Output Capacitors and CFF Values for LM63440-Q1 CONFIGURATION 3.3V OUTPUT 5V OUTPUT COUT CFF COUT CFF 2.1MHz – Ceramic 3 × 22µF, 16V ceramic 10pF 2 × 47µF, 10V ceramic 10pF 2.1MHz – Alternative 2 × 22µF, 16V ceramic + 47µF, 10mΩ electrolytic – 2 × 47µF, 10V ceramic + 47µF, 10mΩ electrolytic – 400kHz – Ceramic 4 × 22µF, 16V ceramic 33pF 2 × 47µF, 10V ceramic 22pF 400kHz – Alternative 1 × 22µF, 16V ceramic + 100µF, 10mΩ electrolytic 15pF 1 × 47µF, 10V ceramic + 47µF, 10mΩ electrolytic 10pF Table 8-8. Recommended Output Capacitors and CFF Values for LM63460-Q1 CONFIGURATION 3.3V OUTPUT 5V OUTPUT COUT CFF COUT CFF 2.1MHz – Ceramic 4 × 22µF, 16V ceramic 10pF 2 × 47µF, 10V ceramic 10pF 2.1MHz – Alternative 2 × 22µF, 16V ceramic + 100µF, 10mΩ electrolytic – 2 × 47µF, 10V ceramic + 100µF, 10mΩ electrolytic – 400kHz – Ceramic 5 × 22µF, 16V ceramic 15pF 3 × 47µF, 10V ceramic 15pF 400kHz – Alternative 2 × 22µF, 16V ceramic + 100µF, 10mΩ electrolytic – 1 × 47µF, 10V ceramic + 100µF, 10mΩ electrolytic – LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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Most ceramic capacitors deliver less capacitance than the rating of the capacitor indicates. Be sure to check selected capacitors for initial accuracy, temperature derating, and particularly voltage derating. Table 8-7 and Table 8-8 assumes typical derating for X7R-dielectric capacitors. If lower voltage or lower temperature-rated capacitors are used, more capacitance than listed can be required. More conveniently, Equation 11 calculates the required effective ceramic capacitance for a given application: (11) where FC is the target loop crossover frequency in units of kHz, which can be set at 10% to 15% of switching frequency and up to a maximum of 100kHz. This example requires improved transient performance, resulting in two 47µF, 10V, X7R ceramics as the output capacitance and 10pF for C FF. An alternative configuration is to use a low-ESR electrolytic capacitor in parallel with a reduced ceramic capacitance.

8.2.2.2.6 Input Capacitor Selection

Input capacitors are necessary to limit the input ripple voltage of the converter due to switching-frequency AC currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. Equation 12 gives the input capacitor RMS current, where D = V OUT/VIN is the converter duty cycle. The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the capacitors must be greater than half the output current. 2 L CIN,rms OUT II D I 1 D 12 © ¹ (12) Ideally, the DC and AC components of input current to the buck stage are provided by the input voltage source and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of amplitude (I OUT – I IN) during the D interval and sink I IN during the 1 – D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, Equation 13 gives the peak-to-peak ripple voltage amplitude: OUT IN OUT ESR SW IN I D 1 DV I R F C ' (13) Equation 14 gives the input capacitance required for a particular load current: OUT IN SW IN ESR OUT D 1 D IC F V R I t ' (14) where

ΔVIN is the input voltage ripple specification. The Enhanced HotRod QFN package of the LM63440-Q1 and LM63460-Q1 provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the input capacitors to be split and placed optimally with respect to the internal power MOSFETs, thus improving the effectiveness of the input bypassing. The converter requires a minimum of two 4.7µF ceramic input capacitors, preferably with X7R or X7S dielectric and in 1206 or 1210 footprint. In this example, place two 10 μF, 50V ceramic capacitors in a www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LM63440-Q1 LM63460-Q1

symmetrical layout immediately adjacent to the converter – one at each input-to-ground pin pair: [VIN1, PGND1] and [VIN2, PGND2]. Install additional capacitance for automotive applications to meet conducted EMI specifications, such as CISPR 25 Class 5 (that limits EMI over a frequency range from 150kHz to 108MHz). For example, place a 10nF, 0402 ceramic capacitor at each input-to-ground pin pair immediately adjacent to the converter. These capacitors minimize the parasitic inductance in the switching loops and can suppress switch-node voltage overshoot and ringing, which reduces high-frequency EMI. The two 10nF capacitors, designated as C IN-HF1 and C IN-HF2 in Figure 8-1 or Figure 8-2, must be rated at 50V with an X7R or better dielectric. As discussed in Section 8.3, a moderate-ESR electrolytic bulk capacitance (68µF to 100µF) at the input in parallel with the ceramics provides low-frequency filtering and parallel damping to mitigate the effects of input parasitic inductance resonating with the low-ESR, high-Q ceramic input capacitors. This is especially true if long leads or traces are used to connect the input supply to the converter.

8.2.2.2.7 Bootstrap Capacitor

The LM63440-Q1 and LM63460-Q1 requires a bootstrap capacitor connected between the CBOOT and SW pins. This capacitor stores energy that is used to supply the gate driver for the integrated high-side power MOSFET. Use a 100nF, X7R-dielectric, ceramic capacitor rated for at least 10V.

8.2.2.2.8 VCC Capacitor

The VCC pin is the output of the internal LDO subregulator used to supply the control circuits of the converter. Connect a 1μF, 16V ceramic capacitor from VCC to AGND for proper operation. In general, avoid loading VCC with any external circuitry. However, VCC can be used as the pullup supply for the PGOOD indicator – a 100k Ω pullup resistor is a good choice in this case. Note that VCC remains high when V EN-WAKE < V EN < V EN-TH. The nominal VCC voltage is 3.3V. Do not short VCC to ground or connect to an external voltage.

8.2.2.2.9 BIAS Power Connection

Because the output voltage is 5V in this design, connect the BIAS pin to V OUT to reduce the VCC LDO power loss. The output voltage is supplying the LDO current instead of the input voltage. The power saving is I VCC × (VIN – V OUT). The power saving is more significant when V IN is much higher than V OUT and at high switching frequencies. To prevent output voltage noise and transients from coupling to BIAS, add a series resistor between 1Ω and 10Ω between VOUT and BIAS. In addition, add a bypass capacitor with a value of 1 μF or higher close to the BIAS pin to filter noise. Note the maximum allowed voltage on BIAS is 16V.

8.2.2.2.10 Feedforward Network

Use a feedforward capacitor, CFF, to improve the phase margin and transient response of converter circuits that have low-ESR output capacitors. Because this capacitor can conduct noise from the output of the circuit directly to the FB node of the IC, connect a 1k Ω resistor, designated as R FF in Figure 8-1 or Figure 8-2, in series with CFF. If the ESR zero of the output capacitor is below 200kHz, feedforward network components are not required. Capacitor CFF has little effect if the output voltage is less than 2.5V, so C FF can be omitted. If the output voltage setpoint is greater than 14V, do not use C FF because it introduces too much gain at higher frequencies. Use the LM63440-Q1 or LM63460-Q1 Quickstart Calculator to review bode plot performance for a given combination of output capacitance and feedforward capacitance.

8.2.2.2.11 Input Voltage UVLO

In some cases, an input UVLO level different than that provided internal to the device is required. Based on the circuit shown in Figure 8-1 or Figure 8-2, VIN(on) and VIN(off) designate the input voltages thresholds at which the converter turns on and off, respectively. First, choose a value for the lower resistance R ENB in the range of 10kΩ to 100kΩ. Then use Equation 15 to calculate the upper resistance R ENT based on a target input voltage turn-on threshold of 5.9V. (15) LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

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Selecting upper and lower resistances of 365kΩ and 100kΩ gives input voltage turn-on and turn-off thresholds of 5.87V and 4.23V, respectively. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LM63440-Q1 LM63460-Q1

8.2.2.3 Application Curves

Unless otherwise indicated, V IN = 13.5V, V OUT = 5V, I OUT = 6A, f SW = 2.1MHz, AUTO mode, and T A = 25°C. Figure 8-1 shows the circuit schematic with relevant BOM components specified in Table 8-2. O u t p u t C u r r e n t ( A ) Efficiency (%) 0 1 2 3 4 5 6 7 5 8 0 8 5 9 0 9 5 1 0 0 V I N = 8 V V I N = 1 2 V V I N = 1 8 V V I N = 2 4 V Figure 8-3. LM634x0-Q1 Efficiency O u t p u t C u r r e n t ( A ) Output Voltage (V) 0 1 2 3 4 5 6 4 . 9 4 . 9 5 5 . 0 5 5 . 1 V I N = 8 V V I N = 1 2 V V I N = 1 8 V V I N = 2 4 V Figure 8-4. LM634x0-Q1 Load and Line Regulation VOUT 1 V/DIV 2 ms/DIV IOUT 2 A/DIV VIN 2 V/DIV Figure 8-5. LM634x0-Q1 Start-Up, 6A Resistive Load VOUT 1 V/DIV 2 ms/DIV IOUT 2 A/DIV EN 2 V/DIV Figure 8-6. LM634x0-Q1 Enable On and Off, 6A Resistive Load VOUT 200 mV/DIV 100 s/DIV IOUT 2 A/DIV Figure 8-7. LM634x0-Q1 Load Transient, IOUT = 3A to 6A VOUT 200 mV/DIV 100 s/DIV IOUT 2 A/DIV Figure 8-8. LM634x0-Q1 Load Transient, IOUT = 0A to 6A LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

38 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: LM63440-Q1 LM63460-Q1

Average detector Peak detector S t a r t 150 k H z S t o p 3 0M H z Figure 8-15. CISPR 25 Class 5 Conducted EMI, 150kHz to 30MHz Average detector Peak detector S t a r t 3 0 M H z S t o p 1 0 8 M H z Figure 8-16. CISPR 25 Class 5 Conducted EMI, 30MHz to 108MHz AVG detector PK detector QPK detector Figure 8-17. CISPR 25 Class 5 Radiated EMI, Bicon Antenna, Horizontal Polarization, 30MHz to 200MHz AVG detector PK detector QPK detector Figure 8-18. CISPR 25 Class 5 Radiated EMI, Bicon Antenna, Vertical Polarization, 30MHz to 200MHz AVG detector PK detector QPK detector Figure 8-19. CISPR 25 Class 5 Radiated EMI, Log Antenna, Horizontal Polarization, 200MHz to 1GHz AVG detector PK detector QPK detector Figure 8-20. CISPR 25 Class 5 Radiated EMI, Log Antenna, Vertical Polarization, 200MHz to 1GHz LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: LM63440-Q1 LM63460-Q1

8.2.3 Design 3 – Automotive Synchronous 6A Buck Regulator at 400kHz

Figure 8-21 shows the schematic diagram of a synchronous buck regulator with an output voltage set at 3.3V and a rated load current of 6A. The RT resistor of 33.2kΩ sets the switching frequency at 400kHz. In this example, the target half-load and full-load efficiencies are 94.5% and 91.5%, respectively, based on a nominal input voltage of 12V that ranges from 4V to 36V. The switching frequency is set at 400kHz. The BIAS input is connected to the 3.3V output, thus reducing IC bias power dissipation and improving efficiency performance. RT PGND1 GND VCC CBOOT SW FB BIAS VIN1 PGND2 VIN2 CVCC CIN-HF1 CIN-HF2 CIN2 CBOOT COUT RFBB LO LM63460-Q1 RRT CIN1 2 100 F 3.3 H 0.1 F 33.2 k 43.2 k 1 F 100 k 15 pF 1 k VOUT = 3.3 V IOUT = 6 A VIN = 4 V...36 V 10 nF10 nF RFBT RFFCFF Feedforward network PGOOD EN/SYNC RENT RENB CSYNC SYNC optional Precision enable for VIN UVLO Synchronization (200 kHz to 2.2 MHz) RPG VOUT PGOOD indicator Optional external bias 100 k 175 k 100 k 1 nF 2 10 F2 10 F Figure 8-21. Application Circuit 3 – 3.3V, 6A at 400kHz Note Depending on the source impedance of the input supply bus, an electrolytic capacitor can be required at the input for stability, particularly at low input voltage and high output current operating conditions. See the Power Supply Recommendations for more detail.

8.2.3.1 Design Requirements

Table 8-9 shows the intended input, output, and performance parameters for this application example. Note that during cold-crank operation when the input voltage decreases to 4V, the converter operates close to dropout but the output voltage remains at 3.3V setpoint. Table 8-9. Design Parameters DESIGN PARAMETER VALUE Input voltage range, steady state 4V to 36V Maximum transient input voltage, load dump 42V Output voltage and full-load current 3.3V, 6A Switching frequency 400kHz Output voltage regulation ±1% IC input current, no-load < 10µA IC shutdown current < 1µA www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LM63440-Q1 LM63460-Q1

Table 8-10 gives the selected buck converter power-stage components with availability from multiple vendors. This design uses a low-DCR inductor and all-ceramic output capacitor implementation. Table 8-10. List of Materials for Application Circuit 3 REF DES QTY SPECIFICATION VENDOR (1) PART NUMBER CIN 4 10µF, 50V, X7R, 1210, ceramic, AEC-Q200 AVX 12105C106K4T2A TDK CNA6P1X7R1H106K 10µF, 50V, X7S, 1210, ceramic, AEC-Q200 Murata GCM32EC71H106KA03 TDK CGA6P3X7S1H106M COUT 2 100µF, 6.3V, X7S, 1210, ceramic, AEC-Q200 Murata GRT32EC70J107ME13 3 47µF, 6.3V, X7R, 1210, ceramic, AEC-Q200 Murata GCM32ER70J476KE19L Taiyo Yuden JMK325B7476KMHTR LO 1 U1 1 LM63460-Q1 synchronous buck converter, AEC-Q100 AUTO Texas Instruments LM63460AASQRYFRQ1 FPWM LM63460AFSQRYFRQ1 (1) See the Section 9.1.1 .

8.2.3.2 Detailed Design Procedure

Refer to Section 8.2.2.2 for detail related to component selection for this 400kHz design. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: LM63440-Q1 LM63460-Q1

8.2.3.3 Application Curves

Unless otherwise indicated, V IN = 12V, V OUT = 3.3V, I OUT = 6A, f SW = 400kHz, AUTO mode, and T A = 25°C. Figure 8-21 shows the circuit schematic with relevant BOM components specified in Table 8-10. O u t p u t C u r r e n t ( A ) Efficiency (%) 0 1 2 3 4 5 6 7 5 8 0 8 5 9 0 9 5 1 0 0 V I N = 5 V V I N = 1 2 V V I N = 2 4 V V I N = 3 6 V Figure 8-22. LM634x0-Q1 Efficiency O u t p u t C u r r e n t ( A ) Output Voltage (V) 0 1 2 3 4 5 6 3 . 2 6 3 . 2 8 3 . 3 3 . 3 2 3 . 3 4 3 . 3 6 V I N = 5 V V I N = 1 2 V V I N = 2 4 V V I N = 3 6 V Figure 8-23. LM634x0-Q1 Load and Line Regulation VOUT 1 V/DIV 1 ms/DIV IOUT 2 A/DIV VIN 2 V/DIV Figure 8-24. LM634x0-Q1 Start-Up, 6A Resistive Load VOUT 1 V/DIV 1 ms/DIV IOUT 2 A/DIV EN/SYNC 2 V/DIV Figure 8-25. LM634x0-Q1 Enable On, Off, 6A Resistive Load VOUT 200 mV/DIV 100 s/DIV IOUT 2 A/DIV Figure 8-26. LM634x0-Q1 Load Transient, IOUT = 3A to 6A VOUT 200 mV/DIV 100 s/DIV IOUT 2 A/DIV Figure 8-27. LM634x0-Q1 Load Transient, IOUT = 0A to 6A www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LM63440-Q1 LM63460-Q1

Figure 8-28. LM634x0-Q1 Short-Circuit Hiccup VOUT 2 V/DIV 20 ms/DIV IL 5 A/DIV Figure 8-29. LM634x0-Q1 Short-Circuit Recovery to No Load LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: LM63440-Q1 LM63460-Q1

8.3 Power Supply Recommendations

The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded converter. Estimate the average input current with Equation 16. K IN OUTOUT IN V IVI (16) where

η is the efficiency. If the converter is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability and voltage transients each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the converter is operating close to the minimum input voltage, this dip can cause false UVLO triggering and a system reset. The best way to solve such issues is to reduce the distance from the input supply to the converter and use an electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady during large load transients. An ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit configurations. The input voltage must not be allowed to suddenly fall below the output voltage. In this scenario, such as a shorted input test, the output capacitors discharge through the body diode of the internal high-side power MOSFET. The current is effectively uncontrolled during this condition, possibly causing damage to the device. If this scenario is considered likely, then connect a Schottky bypass diode between the output and the input supply.

8.4 Layout

8.4.1 Layout Guidelines

Proper PCB design and layout is important in high-current, fast-switching converter circuits (with high current and voltage slew rates) to achieve reliable device operation and design robustness. Furthermore, the EMI performance of the converter depends to a large extent on PCB layout. Figure 8-30 denotes the high-frequency switching power loops of the LM63440-Q1 or LM63460-Q1 power stage. The topological architecture of a buck converter means that particularly high di/dt current flows in the power MOSFETs and input capacitors, and reducing the parasitic inductance by minimizing the effective power loop areas becomes mandatory. For both LM63440-Q1 and LM63460-Q1, note the dual and symmetrical arrangement of the input capacitors based on the VIN and PGND pins located on each side of the IC package. The high-frequency currents are split in two and effectively flow in opposing directions such that the related magnetic fields contributions cancel each other, leading to improved EMI performance. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: LM63440-Q1 LM63460-Q1

Figure 8-30. Input Current Loops The following list summarizes the essential guidelines for PCB layout and component placement to optimize DC/DC converter performance, including thermals and EMI signature. Figure 8-31 shows a recommended layout of either the LM63440-Q1 or LM63460-Q1 with optimized placement and routing of the power-stage and small-signal components.

Place the input capacitors as close as possible to the input pin pairs [VIN1, PGND1] and [VIN2, PGND2]: The respective VIN and PGND pins pairs are close together (with an NC pin in between to increase clearance), thus simplifying input capacitor placement. The Enhanced HotRod QFN package provides VIN and PGND pins on either side of the package to enable a symmetrical layout that helps to minimize switching noise and EMI. – Use low-ESR ceramic capacitors with X7R or X7S dielectric from VIN1 to PGND1 and VIN2 to PGND2. Place an 0402 capacitor close to each pin pair for high-frequency bypass as shown in Figure 8-31. Use an adjacent 1206 or 1210 capacitor on each side for bulk capacitance. – Ground return paths for both the input and output capacitors must consist of localized top-side planes that connect to the PGND1 and PGND2 pins. – Use a wide polygon plane on a lower PCB layer to connect VIN1 and VIN2 together and to the input supply.
Use a solid ground plane on the PCB layer beneath the top layer with the IC: This plane acts as a noise shield and a heat dissipation path. Using the PCB layer directly below the IC minimizes the magnetic field associated with the currents in the switching loops, thus reducing parasitic inductance and switch voltage overshoot and ringing. Use numerous thermal vias near PGND1 and PGND2 for heatsinking to the inner ground planes.
Make the VIN, VOUT, and GND bus connections as wide as possible: These paths must be wide and direct as possible to reduce any voltage drops on the input or output paths of the converter, thus maximizing efficiency.
Locate the buck inductor close to the SW1, SW2, and SW3 pins: Use a short, wide connection trace from the converter SW pins to the inductor. At the same time, minimize the length (and area) of this high-dv/dt surface to help reduce capacitive coupling and radiated EMI. Connect the dotted terminal of the inductor to the SW pins.
Place the VCC and BOOT capacitors close to the respective pins: The VCC and BOOT capacitors represent the supplies for the internal low-side and high-side MOSFET gate drivers, respectively, and thus carry high-frequency currents. Locate CVCC close to the VCC pin and place a GND via at the return terminal to connect to the GND plane and thus back to IC GND at the exposed pad. Connect CBOOT close to the CBOOT and SW4 pins.
Place the feedback divider as close as possible to the FB pin: Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load. This placement reduces the FB trace length and related noise coupling. The FB pin is the input to the voltage-loop error amplifier and represents a high-impedance node sensitive to noise. The connection to VOUT can be LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: LM63440-Q1 LM63460-Q1

somewhat longer. However, this latter trace must not be routed near any noise source (such as the switch node) that can capacitively couple into the feedback path of the converter.

Provide enough PCB area for proper heatsinking: Use sufficient copper area to achieve a low thermal impedance commensurate with the maximum load current and ambient temperature conditions. Provide adequate heatsinking for the LM63440-Q1 or LM63460-Q1 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pad (GND) of the package to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers preferably with two-ounce copper thickness (and no less than one ounce).

8.4.1.1 Thermal Design and Layout

For a DC/DC converter to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM63440-Q1 and LM63460-Q1 converter are available in a small 3.5mm × 4mm 22-pin Enhanced HotRod QFN (RYF) package to cover a range of application requirements. The Thermal Information table summarizes the thermal metrics of this package, with related detail provided by the Semiconductor and IC Package Thermal Metrics Application Report . The 22-pin Enhanced HotRod QFN package offers a means of removing heat from the semiconductor die through the exposed thermal pad at the base of the package. The exposed pad of the package is thermally connected to the substrate of the LM63440-Q1 or LM63460-Q1 device (ground). This allows a significant improvement in heatsinking, and it becomes imperative that the PCB is designed with thermal lands, thermal vias, and one or more ground planes to complete the heat removal subsystem. The exposed pad of the LM63440-Q1 or LM63460-Q1 is soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the IC thermal resistance to a very low value. Preferably, use a four-layer board with 2oz copper thickness for all layers to provide low impedance, proper shielding and lower thermal resistance. Numerous vias with a 0.3mm diameter connected from the thermal land (and from the area around the PGND1 and PGND2 pins) to the internal and solder-side ground planes are vital to promote heat transfer. In a multi-layer PCB design, a solid ground plane is typically placed on the PCB layer below the power-stage components. Not only does this provide a plane for the power-stage currents to flow, but it also represents a thermally conductive path away from the heat-generating devices.

8.4.2 Layout Example

capacitors adjacent to the inductor to provide shielding Place the boot capacitor close to the CBOOT and SW pins Figure 8-31. PCB Layout Example www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LM63440-Q1 LM63460-Q1

9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.1.2 Development Support

With an input operating voltage as low as 3V and up to 36V as specified in Table 9-1, the LM6k-Q1 family of automotive synchronous buck converters from TI provides flexibility, scalability and optimized design size for a range of applications. These converters enable DC/DC designs with high density, low EMI and increased flexibility. Available EMI mitigation features include pseudo-random spread spectrum (PRSS), integrated input bypass capacitors, RBOOT-configured switch-node slew rate control, and optimized package design with symmetrical VIN and PGND pins that shield a small switch-node copper area. All converters are rated for a maximum operating junction temperature of 150°C, have AEC-Q100 grade 1 qualification, and are functional safety capable. Table 9-1. Automotive Synchronous Buck DC/DC Converter Family DC/DC CONVERTER RATED IOUT PACKAGE FEATURES EMI MITIGATION LM60430-Q1, LM60440-Q1 3A, 4A WQFN (13) 400kHz fixed fSW, 3mm × 2mm package Shielded switch node LM63610-Q1, LM63615-Q1, LM63625-Q1, LM63635-Q1 1A, 1.5A, 2.5A, 3.25A WSON (12), HTSSOP (16) RT adjustable fSW, MODE/SYNC PRSS LM61430-Q1, LM61435-Q1, LM61440-Q1, LM61460-Q1 3A, 3.5A, 4A, VQFN-HR (14) RT adjustable fSW, EN/SYNC PRSS, RBOOT LM62435-Q1, LM62440-Q1 3.5A, 4A 2.1MHz default fSW, MODE/SYNC LMQ61460-Q1 6A RT adjustable fSW, EN/SYNC PRSS, RBOOT, integrated capacitorsLMQ62440-Q1 4A 2.1MHz default fSW, MODE/SYNC LM62460-Q1, LM61480-Q1, LM61495-Q1 6A, 8A, 10A VQFN-HR (16) RT adjustable fSW, MODE/SYNC DRSS, RBOOT LM63440-Q1, LM63460-Q1 4A, 6A VQFN-FCRLF (22) RT adjustable fSW, EN/SYNC, pin FMEA PRSS LM64440-Q1, LM64460-Q1 2.1MHz default fSW, MODE/SYNC, pin FMEA For development support see the following:

LM634x0-Q1 EVM User's Guide
LM634x0-Q1 Quickstart Calculator
LM63460-Q1 Simulation Models
LM634x0-Q1 EVM Altium Layout Files
For TI's reference design library, visit TI Designs.
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
To design a low-EMI power supply, review TI's comprehensive EMI Training Series.
TI reference designs: – 30-W Power For Automotive Dual USB Type-C™ Charge Port Reference Design – High Efficiency, Low Noise, 5-V/3.3-V/1.8-V/1.1-V Automotive Display Reference Design
Technical articles: – How Device-level Features And Package Options Can Help Minimize EMI In Automotive Designs – Optimizing Flip-chip IC Thermal Performance In Automotive Designs – Powering Levels Of Autonomy: A Quick Guide To DC/DC Solutions For SAE Autonomy Levels – Powering Infotainment Systems Of The Future
To view related devices of this product, see the LM64460-Q1 6-A converter and the TPSM63606 6-A power module. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: LM63440-Q1 LM63460-Q1

9.1.2.1 Custom Design With WEBENCH® Tools

Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
Texas Instruments, Enhanced HotRod™ QFN Package: Achieving Low EMI Performance in Industry’s Smallest 4-A Converter application report
Texas Instruments, Designing High Performance, Low-EMI, Automotive Power Supplies application report
Texas Instruments, EMI Filter Components And Their Nonidealities For Automotive DC/DC Regulators technical brief
Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
Texas Instruments, AN-2162 Simple Success With Conducted EMI From DC/DC Converters Application Report application report
Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

HotRod™ and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: LM63440-Q1 LM63460-Q1

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (October 2023) to Revision C (August 2024) Page

Added recommended operating current for the LM63440-Q1 and added GPN to the description of operating
Added high side, low side, and negative current limits for the LM63440-Q1 and added GPN to current limit
Added efficiency specifications for the LM63440-Q1 and added GPN to the test conditions for efficiency Changes from Revision A (October 2022) to Revision B (October 2023) Page Changes from Revision * (December 2021) to Revision A (October 2022) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: LM63440-Q1 LM63460-Q1

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LM63460AASQRYFRQ1 VQFN- LM63460AFSQRYFRQ1 VQFN- FCRLF LM63440AASQRYFRQ1 VQFN- FCRLF LM63440AFSQRYFRQ1 VQFN- FCRLF www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: LM63440-Q1 LM63460-Q1

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM63460AASQRYFRQ1 VQFN-FCRLF RYF 22 3000 367.0 367.0 35.0 LM63460AFSQRYFRQ1 VQFN-FCRLF RYF 22 3000 367.0 367.0 35.0 LM63440AASQRYFRQ1 VQFN-FCRLF RYF 22 3000 367.0 367.0 35.0 LM63440AFSQRYFRQ1 VQFN-FCRLF RYF 22 3000 367.0 367.0 35.0 LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: LM63440-Q1 LM63460-Q1

www.ti.com VQFN-FCRLF - 1.05 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RYF0022A A 0.08 C 4.1 3.9 1.05 0.95 SEATING PLANE PIN 1 INDEX AREA C (0.20) TYP 0.01 0.00 PIN 1 ID B 3.6 3.4 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. 2X 2.5 2X 3 18X 0.3 0.2

0.1 C A B

0.05 C 8X 0.3 0.2 18X 0.6 0.5 22X (0.18) 1.7±0.1 0.05 C 2.2±0.1 7 12 22 18 SYMM /UNI2104 SYMM /UNI2104 22X (0.5) AA

0.1 MIN

(0.1) (0.2) www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: LM63440-Q1 LM63460-Q1

www.ti.com VQFN-FCRLF - 1.05 mm max heightRYF0022A PLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK DETAILS

0.05 MAX

(PREFERRED) SOLDER MASK DEFINED NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be ﬁlled, plugged or tented. 2X (3) 22X (0.25) (3.65) 22X (0.5) 2X (2.5) 18X (0.75) (Ø0.2) TYP (2.2) (1.7) (3.15) SYMM /UNI2104 SYMM /UNI2104 (R0.05) TYP 8 12 22 19 (0.6) (0.85) LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 www.ti.com

Product Folder Links: LM63440-Q1 LM63460-Q1

www.ti.com VQFN-FCRLF - 1.05 mm max heightRYF0022A PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD: 81% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. 2X (3) 22X (0.25) (3.65) 22X (0.5) 2X (2.5) 18X (0.75) 2X (1.55) (3.15) SYMM /UNI2104 SYMM /UNI2104 (R0.05) TYP 8 12 22 19 (0.59) 2X (0.98) www.ti.com LM63440-Q1, LM63460-Q1 SNVSBW1C – DECEMBER 2021 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: LM63440-Q1 LM63460-Q1

www.ti.com 28-Aug-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM63440AASQRYFRQ1 ACTIVE VQFN-FCRLF RYF 22 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 6344AAS Samples LM63440AFSQRYFRQ1 ACTIVE VQFN-FCRLF RYF 22 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 6344AFS Samples LM63460AASQRYFRQ1 ACTIVE VQFN-FCRLF RYF 22 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 6346AAS Samples LM63460AFSQRYFRQ1 ACTIVE VQFN-FCRLF RYF 22 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 6346AFS Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

www.ti.com 28-Aug-2024 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LM63460AASQRYFRQ1 VQFN- FCRLF LM63460AFSQRYFRQ1 VQFN- FCRLF Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM63460AASQRYFRQ1 VQFN-FCRLF RYF 22 3000 367.0 367.0 35.0 LM63460AFSQRYFRQ1 VQFN-FCRLF RYF 22 3000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com VQFN-FCRLF - 1.05 mm max heightRYF0022A PLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK DETAILS (PREFERRED) SOLDER MASK DEFINED NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 2X (3) 22X (0.25) (3.65) 22X (0.5) 2X (2.5) 18X (0.75) (Ø0.2) TYP (2.2) (1.7) (3.15) SYMM SYMM (R0.05) TYP 8 12 22 19 (0.6) (0.85)

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated

Product Information

LM63440AASQRYFRQ1 specifications and overview.

Summary

LM634x0-Q1 3V to 36V, 4A and 6A, Automotive, Synchronous Buck DC/DC Converters With Adjustable Switching Frequency, Optimized for Reliability and Low EMI REVISED AUGUST 2024

Description

LM634x0-Q1 3V to 36V, 4A and 6A, Automotive, Synchronous Buck DC/DC Converters With Adjustable Switching Frequency, Optimized for Reliability and Low EMI REVISED AUGUST 2024

Source title LM63440AASQRYFRQ1 Datasheet(PDF) - Texas Instruments

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