LM61435AANQRJRRQ1

Texas Instruments

LM61435-Q1 Automotive 3-V to 36-V, 3.5-A, Low EMI Synchronous Step-Down Converter

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Load Current (A) Efficiency (%) 100 SNVS VIN = 8 V VIN = 13.5 V VIN = 24 V YELLOW: PEAK BLUE: AVERAGE Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM61435-Q1 SNVSBM0 –MARCH 2020 LM61435-Q1Automotive3-Vto36-V,3.5-A,LowEMISynchronousStep-DownConverter

1 Features

1• AEC-Q100 qualified for automotive applications – Temperature grade 1: –40°C to +150°C, TJ

Functional safety capable – Documentation available to aid functional safety system design
Optimized for ultra low EMI requirements – Hotrod™ package minimizes switch node ringing – Parallel input path minimizes parasitic inductance – Spread spectrum reduces peak emissions – Adjustable SW node rise time
Designed for automotive applications – Supports 42 V automotive load dump – ±1% total output regulation accuracy – VOUT adjustable from 1 V to 95% of VIN – 0.3-V dropout with 3-A load (typical)
High efficiency power conversion at all loads – 7-µA no load current at 13.5 VIN, 3.3 VOUT – 91% PFM efficiency at 1-mA, 13.5 VIN, 5 VOUT – External bias option for improved efficiency
Suitable for scalable power supplies – Pin compatible with: – LM61440-Q1 (36 V, 4 A, adjustable fSW) – LM61460-Q1 (36 V, 6 A, adjustable fSW)

2 Applications

Automotive infotainment and cluster: head unit, media hub, USB charge, display
Automotive ADAS and body electronics

3 Description

The LM61435-Q1 is an automotive-focused, high- performance, DC-DC synchronous step-down converter. With integrated high-side and low-side MOSFETs, up to 3.5 A of output current is delivered over a wide input range of 3.0 V to 36 V; tolerant of 42 V, easing input surge protection design. The LM61435-Q1 implements soft recovery from dropout eliminating overshoot on the output. The LM61435-Q1 is specifically designed for minimal EMI. The device incorporates pseudo-random spread spectrum, adjustable SW node rise time, low-EMI VQFN-HR package featuring low switch node ringing, and optimized pinout for ease of use. The switching frequency can be set or synchronized between 200 kHz and 2.2 MHz to avoid noise sensitive frequency bands. In addition the frequency can be selected for improved efficiency at low operating frequency or smaller solution size at high operating frequency. Auto-mode enables frequency foldback when operating at light loads, allowing an unloaded current consumption of only 7 µA (typical) and high light load efficiency. Seamless transition between PWM and PFM modes, along with very low MOSFET ON resistances and an external bias input, ensures exceptional efficiency across the entire load range. Electrical characteristics are specified over a junction temperature range of –40°C to +150°C. Find additional resources in the Related Documentation. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM61435-Q1 VQFN-HR (14) 4.00 mm × 3.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Conducted EMI: VOUT = 5 V, fSW = 2100 kHz Efficiency VOUT = 5 V, FSW = 2200 kHz

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES March 2020 * Initial release

5 Device Comparison Table

LM61435AANQRJRRQ1 LM61435AAN-Q1 Auto Mode No Adjustable Adjustable LM61435AASQRJRRQ1 LM61435AAS-Q1 Auto Mode Yes Adjustable Adjustable LM61435AFSQRJRRQ1 LM61435AFS-Q1 FPWM Yes Adjustable Adjustable

6 Pin Configuration and Functions

NAME NO. BIAS 1 P Input to internal LDO. Connect to output voltage point to improve efficiency. Connect an optional high quality 0.1-µF to 1-µF capacitor from this pin to ground for improved noise immunity. If output voltage is above 12 V, connect this pin to ground. VCC 2 O Internal LDO output. Used as supply to internal control circuits. Do not connect to any external loads. Connect a high-quality 1-µF capacitor from this pin to AGND. AGND 3 G Analog ground for internal circuitry. Feedback and VCC are measured with respect to this pin. Must connect AGND to both PGND1 and PGND2 on PCB. FB 4 I Output voltage feedback input to the internal control loop. Connect to feedback divider tap point for adjustable output voltage. Do not float or connect to ground. PGOOD 5 O Open-drain power-good status output. Pull this pin up to a suitable voltage supply through a current limiting resistor. High = power OK, low = fault. PGOOD output goes low when EN = low, VIN > 1-V. RT 6 I/O Connect this pin to ground through a resistor with value between 5.76kΩ and 66.5kΩ to set switching frequency between 200 kHz and 2200 kHz. Do not float or connect to ground. EN/SYNC 7 I Precision enable input. High = on, Low = off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. See the Application and Implementation section. Do not float. EN/SYNC also functions as a synchronization input pin. Used to synchronize the device switching frequency to a system clock. Triggers on rising edge of external clock. A capacitor can be used to AC couple the synchronization signal to this pin. When synchronized to external clock, the device functions in forced PWM and disables the PFM light load efficiency mode. See the Detailed Description. VIN1 8 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. Low impedance connection must be provided to VIN2. PGND1 9 G Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection should be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1. SW 10 O Switch node of the converter. Connect to output inductor. PGND2 11 G Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2. VIN2 12 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. Low impedance connection must be provided to VIN1. RBOOT 13 I/O Connect to CBOOT through a resistor. This resistance must be between 0 Ω and open and determines SW node rise time. CBOOT 14 I/O High-side driver upper supply rail. Connect a 100-nF capacitor between SW pin and CBOOT. An internal diode connects to VCC and allows CBOOT to charge while SW node is low.

www.ti.com SNVSBM0 –MARCH 2020 Product Folder Links: LM61435-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (3) A voltage of 2 V below GND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%. (4) Do not exceed pin’s voltage rating.

7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of -40℃ to +150℃ (unless otherwise noted)(1) PARAMETER MIN MAX UNIT Input Voltage VIN1, VIN2 to AGND, PGND -0.3 42 V RBOOT to SW -0.3 5.5 V CBOOT to SW -0.3 5.5 V BIAS to AGND, PGND -0.3 16 V EN/SYNC to AGND, PGND -0.3 42 V RT to AGND, PGND -0.3 5.5 V FB to AGND, PGND -0.3 16 V PGOOD to AGND, PGND 0 20 V PGND to AGND(2) -1 2 V Output Voltage SW to AGND, PGND(3) -0.3 VIN+0.3 V VCC to AGND, PGND -0.3 5.5 V Current PGOOD sink current(4) 10 mA TJ Junction temperature -40 150 °C Tstg Storage temperature -40 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) Device HBM Classification Level 2 ±2000 V Charged device model (CDM), per AEC Q100-011 Device CDM Classification Level C5 ±750 (1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics table. (2) Under no conditions should the output voltage be allowed to fall below zero volts. (3) Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See Application section for details.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted) (1) MIN NOM MAX UNIT Input voltage Input voltage range after start-up 3 36 V Output voltage Output voltage range for adjustable version (2) 1 0.95 * VIN V Frequency Frequency adjustment range 200 2200 kHz Sync frequency Synchronization frequency range 200 2200 kHz Load current Output DC current range (3) 0 3.5 A Temperature Operating junction temperature TJ range –40 150 °C

SNVSBM0 –MARCH 2020 www.ti.com Product Folder Links: LM61435-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application.

7.4 Thermal Information

The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application. For example, with a 4-layer PCB, a RΘJA = 25℃/W can be achieved. For design information see Maximum Ambient Temperature versus Output Current. THERMAL METRIC (1) (2) LM61435-Q1 UNITRJR (QFN)

14 PINS

RθJA Junction-to-ambient thermal resistance 59 °C/W RθJC(top) Junction-to-case (top) thermal resistance 19 °C/W RθJB Junction-to-board thermal resistance 19.2 °C/W ΨJT Junction-to-top characterization parameter 1.4 °C/W ΨJB Junction-to-board characterization parameter 19 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance - °C/W (1) Parameter specified by design, statistical analysis and production testing of correlated parameters.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is converter output voltage. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND CURRENT VIN_OPERATE Input operating voltage(1) Needed to start up 3.95 V Once operating 3.0 VIN_OPERATE_H Hysteresis(1) 1 V ISD Shutdown quiescent current; measured at VIN pin EN = 0 V, TJ = 25℃ 0.6 6 µA ENABLE VEN Enable input threshold voltage - rising 1.263 V VEN-ACC Enable input threshold voltage - rising deviation from typical -8.1 8.1 % VEN-HYST Enable threshold hysteresis as percentage of VEN (TYP) 24 28 32 % VEN-WAKE Enable wake-up threshold 0.4 V IEN Enable pin input current VIN = EN = 13.5 V 2.3 µA VEN_SYNC Edge height necessary to sync using EN/SYNC pin Rise/fall time <30 ns 2.4 V LDO - VCC VCC Internal VCC voltage VBIAS > 3.4 V, CCM Operation(1) 3.3 V VBIAS = 3.1 V, Non-switching 3.1 VCC_UVLO Internal VCC input under voltage lock-out VCC rising under voltage threshold 3.6 V VCC_UVLO_HYST Internal VCC input under voltage lock-out Hysteresis below VCC_UVLO 1.1 V

www.ti.com SNVSBM0 –MARCH 2020 Product Folder Links: LM61435-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is converter output voltage. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) High side current limit is a function of duty factor. High side current limit value is highest at small duty factor and less at higher duty factors. FEEDBACK VFB_acc Initial reference voltage accuracy VIN = 3.3 V to 36 V, TJ = 25℃, FPWM Mode -1 1 % IFB Input current from FB to AGND Adjustable versions only, FB = 1 V 10 nA OSCILLATOR fADJ Minimum adjustable frequency by RT or SYNC RT = 66.5 kΩ 0.18 0.2 0.22 MHz Adjustable frequency by RT or SYNC with 400 kHz setting RT = 33.2 kΩ 0.36 0.4 0.44 MHz Maximum adjustable frequency by RT or SYNC RT = 5.76 kΩ 1.98 2.2 2.42 MHz fSSS Frequency span of spread spectrum operation - largest deviation from center frequency Spread spectrum active 2 % fPSS Spread spectrum pattern frequency(1) Spread spectrum active, fSW = 2.1 MHz 1.5 Hz MOSFETS RDS(ON)_HS Power switch on-resistance High side MOSFET RDS(ON) 41 82 mΩ RDS(ON)_LS Power switch on-resistance Low side MOSFET RDS(ON) 21 45 mΩ VBOOT_UVLO Voltage on CBOOT pin compared to SW which will turn off high-side switch 2.1 V CURRENT LIMITS IL-HS High side switch current limit(2) Duty cycle approaches 0% 6 7 8.1 A IL-LS Low side switch current limit 3.7 4.8 5.4 A IL-ZC Zero-cross current limit. Positive current direction is out of SW pin Auto Mode, static measurement 0.25 A IL-NEG Negative current limit FPWM and SYNC Modes. Positive current direction is out of SW pin. FPWM operation -2 A IPK_MIN_0 Minimum peak command in Auto Mode / device current rating Pulse duration < 100 ns 25 % IPK_MIN_100 Minimum peak command in Auto Mode / device current rating Pulse duration > 1 µs 12.5 % VHICCUP Ratio of FB voltage to in-regulation FB voltage Not during soft start 40 % POWER GOOD PGDOV PGOOD upper threshold - rising % of VOUT setting 105 107 110 % PGDUV PGOOD lower threshold - falling % of VOUT setting 92 94 96.5 % PGDHYST PGOOD upper threshold (rising & falling) % of VOUT setting 1.3 % VIN(PGD_VALID) Input voltage for proper PGOOD function 1.0 V

SNVSBM0 –MARCH 2020 www.ti.com Product Folder Links: LM61435-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is converter output voltage. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VPGD(LOW) Low level PGOOD function output voltage 46 µA pullup to PGOOD pin, VIN = 1.0 V, EN = 0 V 0.4 V1 mA pullup to PGOOD pin, VIN = 13.5 V, EN = 0 V 0.4 2 mA pullup to PGOOD pin, VIN = 13.5 V, EN = 3.3 V 0.4 RPGD RDS(ON) of PGOOD output 1 mA pullup to PGOOD pin, EN = 0 V 17 40 Ω 1 mA pullup to PGOOD pin, EN =

3.3 V 40 90 Ω

Pull down current at the SW node under over voltage condition 0.5 mA THERMAL SHUTDOWN TSD_R Thermal shutdown rising threshold(1) 158 168 180 ℃ TSD_HYST Thermal shutdown hysteresis(1) 10 ℃ (1) Parameter specified using design, statistical analysis and production testing of correlated parameters; not tested in production.

7.6 Timing Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. Parameter Test Condition MIN TYP MAX UNIT SWITCH NODE tON_MIN Minimum HS switch on time VIN = 20 V, IOUT = 2 A, RBOOT short to CBOOT 55 70 ns tON_MAX Maximum HS switch on time 9 μs tOFF_MIN Minimum LS switch on time VIN = 4.0 V, IOUT = 1 A, RBOOT short to CBOOT 65 85 ns tSS Time from first SW pulse to VREF at 90% VIN ≥ 4.2 V 3.5 5 7 ms tSS2 Time from first SW pulse to release of FPWM lockout if output not in regulation VIN ≥ 4.2 V 9.5 13 17 ms tW Short circuit wait time ("Hiccup" time) 80 ms ENABLE tEN Turn-on delay(1) CVCC = 1 µF, time from EN high to first SW pulse if output starts at 0 V 0.7 ms tB Blanking of EN after rising or falling edges(1) 4 28 µs tSYNC_EDGE Enable sync signal hold time after edge for edge recognition 100 ns POWER GOOD tPGDFLT(rise) Delay time to PGOOD high signal 1.5 2 2.5 ms tPGDFLT(fall) Glitch filter time constant for PGOOD function 120 µs

www.ti.com SNVSBM0 –MARCH 2020 Product Folder Links: LM61435-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) See detailed description for the meaning of this specification and how it can be calculated.

7.7 Systems Characteristics

The following values are specified by design provided that the component values in the typical application circuit are used. Limits apply over the junction temperature range of -40°C to +150°C, unless otherwise noted. Minimum and Maximum limits are derived using test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is output setting. These parameters are not tested in production. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EFFICIENCY ƞ5V_2p1MHz Typical 2.1 MHz efficiency VOUT = 5 V, IOUT = 3.5 A, RBOOT = 0 Ω 93 VOUT = 5 V, IOUT = 100 µA, RBOOT = 0 Ω 73 ƞ5V_400kHz Typical 400 kHz efficiency VOUT = 5 V, IOUT = 3.5 A, RBOOT = 0 Ω 95 VOUT = 5 V, IOUT = 100 µA, RBOOT = 0 Ω 76 RANGE OF OPERATION VVIN_MIN1 VIN for full functionality at reduced load, after start-up. VOUT set to 3.3 V 3.0 V VVIN_MIN2 VIN for full functionality at 100% of maximum rated load, after start-up. VOUT set to 3.3 V 3.95 V IQ-VIN Operating quiescent current(1) VOUT = 3.3 V, IOUT = 0 A, Auto mode, RFBT=1 MΩ 7 µA VOUT = 5 V, IOUT = 0 A, Auto mode, RFBT=1 MΩ 10 DMAX Maximum switch duty cycle fSW =1.85 MHz 87 % While in frequency fold back 98 % RBOOT tRISE SW node rise time RBOOT = 0 Ω, IOUT = 2 A (10% to 80%) 2.15 ns RBOOT = 100 Ω, IOUT = 2 A (10% to 80%) 2.7 ns

7.8 Typical Characteristics

Unless otherwise specified, VIN = 13.5 V and fSW = 400 kHz. Figure 1. Non-Switching Input Supply Current Figure 2. Shutdown Supply Current Figure 3. Feedback Voltage Figure 4. LM61435-Q1 High-side and Low-side Current Figure 5. Switching Frequency Set by RT Resistor Figure 6. High-side and Low-side Switches RDS_ON

Unless otherwise specified, VIN = 13.5 V and fSW = 400 kHz. Figure 7. Enable Thresholds Figure 8. PGOOD Thresholds

8 Detailed Description

8.1 Overview

The LM61435-Q1 is a wide input, synchronous peak-current mode buck regulator designed for a wide variety of automotive applications. The regulator can operate over a wide range of switching frequencies including sub-AM band at 400 kHz and above the AM band at 2.1 MHz. This device operates over a wide range of conversion ratios. If minimum on-time or minimum off-time does not support the desired conversion ratio, frequency is reduced automatically, allowing output voltage regulation to be maintained during input voltage transients with a high operating-frequency setting. The LM61435-Q1 has been designed for low EMI and is optimized for both above and below AM band operation:

Hotrod™ package minimizes switch node ringing
Parallel input path minimizes parasitic inductance
Adjustable SW node rise time These features together can eliminate shielding and other expensive EMI mitigation measures. This device is designed to minimize end-product cost and size while operating in demanding automotive environments. The LM61435-Q1 can be set to operate in the range of 200 kHz through 2.2 MHz using its RT pin. Operation at 2.1 MHz allows for the use of small passive components. State of the art current limit function allow the use of the inductors that are optimized for 3.5-A regulators. In addition, this device has low unloaded current consumption, desirable for off-battery, always on applications. The low shutdown current and high maximum operating voltage also allows for the elimination of an external load switch and input transient protection. To further reduce system cost, an advanced PGOOD output is provided, which can often eliminate the use of an external reset or supervisory device. The LM61435-Q1 devices are AEC-Q100 qualified and have electrical characteristics guaranteed up to a maximum junction temperature of 150°C.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 EN/SYNC Uses for Enable and VIN UVLO

Figure 9. VIN UVLO Using the EN pin Resistor values can be calculated using Equation 1. See the External UVLO section for additional information.

VON is the desired typical start-up input voltage for the circuit being designed (1) Note that since the EN/SYNC pin can also be used as an external synchronization clock input. A blanking time, tB, is applied to the enable logic after a clock edge is detected. Any logic change within the blanking time is ignored. Blanking time is not applied when the device is in shutdown mode. The blanking time ranges from 4 µs to 28 µs. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs.

8.3.2 EN/SYNC Pin Uses for Synchronization

Figure 10. Typical Implementation Allowing Synchronization Using the EN Pin higher amplitude pulse signal coupled through a 1-nF capacitor, CSYNC, is suggested. Figure 11. Typical SYNC/EN Waveform overrides spread spectrum, turning it off, and the clock switches to the applied clock frequency.

8.3.3 Clock Locking

adjusted over a few tens of cycles so that rising synchronization edges correspond to rising SW node pulses.

the device transitions from Auto Mode to FPWM. Figure 12. Synchronization Process

8.3.4 Adjustable Switching Frequency

for Synchronization section. Figure 13. Setting Clock Frequency

8.3.5 PGOOD Output Operation

and load transients. Output voltage excursions that are shorter than tPGDFLT_FALL do not trip the power-good flag. Power-good operation can be best understood by referring to Figure 14. as long as the input voltage is ≥ 1 V (typical).

or tSS2 has passed since initiation. Figure 14. PGOOD Timing Diagram (Excludes OV Events) Table 1. Conditions That Cause PGOOD to Signal a Fault (Pull Low)

8.3.6 Internal LDO, VCC UVLO, and BIAS Input

directly powers the internal LDO. of the LDO are used to derive minimum VIN_OPERATE and VIN_OPERATE_H values.

8.3.7 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)

charging sequence turning on the low-side switch before attempting to turn on the HS switch.

8.3.8 Adjustable SW Node Slew Rate

used to turn on the high-side power MOSEFT. Figure 15. Simplified Circuit Showing How RBOOT Functions and common mode chokes in many applications. Note that rise time increases with increasing input voltage. rate also decreases the efficiency.

8.3.9 Spread Spectrum

spreading these emissions across a wider range of frequencies rather than a part with fixed frequency operation. less than 1 dB, while peaks in the FM band are typically reduced by more than 6 dB. (LFSR). This intelligent pseudo-random generator limits cycle-to-cycle frequency changes to limit output ripple. The pseudo-random pattern repeats at less than 1.5 Hz, which is below the audio band.

The clock is slowed during dropout.
The clock is slowed at light load in auto mode. In FPWM mode, spread spectrum is active even if there is no load.
At high input voltage/low output voltage ratio when the device operates at minimum on time the internal clock is slowed disabling spread spectrum. See the Timing Characteristics section.

The clock is synchronized with an external clock.

8.3.10 Soft Start and Recovery From Dropout

Power is applied to the VIN pin of the IC, releasing UVLO.
EN is used to turn on the device.
Recovery from a hiccup waiting period.
Recovery from shutdown due to overtemperature protection. Once soft start is triggered, the IC takes the following actions:
The reference used by the IC to regulate output voltage is slowly ramped. The net result is that output voltage takes tSS to reach 90% of its desired value.
Operating mode is set to auto, activating diode emulation. This allows start-up without pulling output low if there is a voltage already present on output. These actions together provide start-up with limited inrush currents and also allow the use of larger output capacitors and higher loading conditions that cause current to border on current limit during start-up without triggering hiccup. See Figure 16. Soft start works with both output voltage starting from 0 V on the left curves, or if there is already voltage on the output, as shown on right. In either case, output voltage must reach within 10% of the desired value tSS after soft start is initiated. During soft start, FPWM and hiccup are disabled. Both hiccup and FPWM are enabled once output reaches regulation or tSS2, whichever happens first.

Figure 16. Soft-Start Operation

The reference voltage is set to approximately 1% above what is needed to achieve the existing output voltage.
Hiccup is allowed if output voltage is less than 0.4 times its set point. Note that during dropout regulation itself, hiccup is inhibited.
FPWM mode is allowed during recovery from dropout. If the output voltage were to suddenly be pulled up by an external supply, the LM61435-Q1 can pull down on the output. Despite being called recovery from dropout, this feature is active whenever output voltage drops to a few percent lower than the set point. This primarily occurs under the following conditions:
Dropout: When there is insufficient input voltage for the desired output voltage to be generated
Overcurrent: When there is an overcurrent event that is not severe enough to trigger hiccup

for more than 128 clock cycles. Figure 17. Recovery From Dropout

8.3.11 Output Voltage Setting

A feedback resistor divider network between the output voltage and the FB pin is used to set output voltage level. Figure 18. Setting Output Voltage of Adjustable Versions MΩ and reduced current consumption compared to lower resistance values.

8.3.12 Overcurrent and Short Circuit Protection

side and the low-side MOSFETs.

turned on again as long as at least one clock period has passed since the last time the HS device has turned on. Figure 19. Current Limit Waveforms

Output voltage is below approximately 0.4 times the output voltage set point.
Greater than tSS2 has passed since soft start has started; see the Soft Start and Recovery From Dropout section.
The part is not operating in dropout, which is defined as having minimum off-time controlled duty cycle. In hiccup mode, the device shuts itself down and attempts to soft start after tW. Hiccup mode helps reduce the device power dissipation under severe over-current conditions and short circuits. See Figure 20. Once the overload is removed, the device recovers as though in soft start; see Figure 21.

Figure 20. Inductor Current Bursts During Hiccup Figure 21. Short Circuit Recovery

8.3.13 Thermal Shutdown

when the IC junction temperature exceeds 165°C (typical). Thermal shutdown does not trigger below 158°C. While the LM61435-Q1 is shut down due to high junction temperature, power continues to be provided to VCC. milliamperes during thermal shutdown.

8.3.14 Input Supply Current

current is drawn from the output. This current is reduced at the input by the ratio of VOUT / VIN.

IQ_VIN(SW) is the current consumed by the operating (switching) buck converter while unloaded.
IQ_VIN is the non-switching input current. See IQ_VIN in the Electrical Characteristics.
IEN is current drawn by the EN terminal. Include this current if EN is connected to VIN. See IEN in the Electrical Characteristics. Note that this current drops to a very low value if connected to a voltage less than 5 V.
Idiv is the current drawn by the feedback voltage divider used to set output voltage.
ηeff is the light-load efficiency of the buck converter with IQ_VIN removed from the input current of the buck converter. ηeff = 0.8 is a conservative value that can be used under normal operating conditions. (4)

8.4 Device Functional Modes

8.4.1 Shutdown Mode

the quiescent current drops to typically 0.6 µA.

8.4.2 Standby Mode

The internal LDO has a lower EN threshold than the output of the converter. When the EN pin voltage is above 1.1 V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the VCC voltage at 3.3 V typical. The precision enable circuitry is ON once VCC is above its UVLO. The internal power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable threshold. The LM61435-Q1 also employs UVLO protection. If the VCC voltage is below its UVLO level, the output of the converter is turned off.

8.4.3 Active Mode

The LM61435-Q1 is in active mode whenever the EN pin is above VEN, VIN is high enough to satisfy VIN_OPERATE, and no other fault conditions are present. The simplest way to enable the operation is to connect the EN pin to VIN which allows self start-up when the applied input voltage exceeds the minimum VIN_OPERATE. In active mode, depending on the load current, input voltage, and output voltage, the LM61435-Q1 is in one of five modes:

Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the inductor current ripple.
Auto Mode - Light Load Operation: PFM when switching frequency is decreased at very light load.
FPWM Mode - Light Load Operation: Discontinuous conduction mode (DCM) when the load current is lower than half of the inductor current ripple.
Minimum on-time: At high input voltage, low output voltages the switching frequency is reduced to maintain regulation.
Dropout mode: When switching frequency is reduced to minimize voltage dropout.

8.4.3.1 CCM Mode

The following operating description of the LM61435-Q1 refers to the Functional Block Diagram and to the waveforms in Figure 22. In CCM, the LM61435-Q1 supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on-time, the SW pin voltage, VSW, swings up to approximately VIN, and the inductor current, iL, increases with a linear slope. The HS switch is turned off by the control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of the HS switch over the switching period: D = TON / TSW (5) In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN (6)

Figure 22. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

8.4.3.2 Auto Mode - Light Load Operation

Table. Note that all parts operate in FPWM mode when synchronizing frequency to an external signal.

Diode emulation, which allows DCM operation
Frequency reduction Note that while these two features operate together to create excellent light load behavior, they operate independently of each other.

8.4.3.2.1 Diode Emulation

regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.

that diode emulation is active. Figure 23. PFM Operation mode of operation is called PFM mode regulation.

8.4.3.2.2 Frequency Reduction

operation. Output voltage must be approximately 1% high when the part is completely unloaded. increases so that output voltage is 1% high while the buck is completely unloaded. Figure 24. Steady State Output Voltage versus Output Current in Auto Mode dummy load at VOUT or FPWM Mode can be used to reduce or eliminate this offset.

8.4.3.3 FPWM Mode - Light Load Operation

Like auto mode operation, FPWM mode operation during light load operation is selected as a factory option. Characteristics for reverse current limit values. In FPWM mode, Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple. Figure 25. FPWM Mode Operation

8.4.3.4 Minimum On-time (High Input Voltage) Operation

1.85 MHz

In valley control mode, minimum inductor current is regulated, not peak inductor current. Figure 26. Valley Current Mode Operation

8.4.3.5 Dropout

recovery from dropout, reference Figure 17. output voltage at approximately 110 kHz, input voltage tracks output voltage. Figure 27. Frequency and Output Voltage in Dropout

value. As a result, frequency drops. This frequency drop is limited by tON_MAX. Figure 28. Dropout Waveforms

5 V to 36 V input

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

components for the LM61435-Q1.

9.2 Typical Application

component values for some of the common configurations. Figure 29. Example Application Circuit

9.2.1 Design Requirements

Table 2. Detailed Design Parameters

Table 3. Typical External Component Values

9.2.2 Detailed Design Procedure

The following design procedure applies to Figure 29 and Table 2.

9.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size. Lower switching frequency implies reduced switching losses and usually results in higher system efficiency. approximately 100-mm x 80-mm in board area. Figure 30. Maximum Ambient Temperature versus Output Figure 31. Maximum Ambient Temperature versus Output requiring constant frequency operation.

/0.5 Â VOUT fSW L= fSW Â.Â,OUT(MAX) VIN Å9OUT ÂVOUT VIN VINeff(MIN2) = VIN(MIN2) ± IOUT(MAX) Â(RDS(ON)_HS(MAX) + DCR(MAX)) LM61435-Q1 www.ti.com SNVSBM0 –MARCH 2020 Product Folder Links: LM61435-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated where:

DCR(MAX) = Maximum DCR of Inductor
tOFF_MIN(MAX) = see the Electrical Characteristics
RDS(ON)_HS(MAX) = see the Electrical Characteristics (8) The fourth constraint is the rated frequency range of the IC. See fADJ in the Electrical Characteristics. All previously stated constraints (thermal, VIN(MAX2), VIN(MIN2), and device-specified frequency range) must be considered when selecting frequency. Many applications require that the AM band can be avoided. These applications tend to operate at either 400 kHz below the AM band or 2.1 MHz above the AM band. In this example, 400 kHz is chosen.

9.2.2.2 Setting the Output Voltage

The output voltage of LM61435-Q1 is externally adjustable using a resistor divider network. The range of recommended output voltage is found in the Recommended Operating Conditions table. The divider network is comprised of RFBT and RFBB, and closes the loop between the output voltage and the converter. The converter regulates the output voltage by holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the divider is a compromise between excessive noise pickup and excessive loading of the output. Smaller values of resistance reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for RFBT is 100 kΩ with a maximum value of 1 MΩ. If 1 MΩ is selected for RFBT, then a feedforward capacitor must be used across this resistor to provide adequate loop phase margin (see CFF and RFF Selection). Once RFBT is selected, Equation 3 is used to select RFBB. VREF is nominally 1 V. For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ are chosen.

9.2.2.3 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load current for systems with a fixed input voltage and 25% for systems with a variable input voltage such as the 12 volt battery in a car. Note that when selecting the ripple current for applications with much smaller maximum load than the maximum available from the device, the maximum device current must still be used. Equation 9 can be used to determine the value of inductance. The constant K is the percentage of inductor current ripple. For this example, K = 0.25 was chosen and an inductance of approximately 10 µH was found. The next standard value of 8.2 μH was selected. (9) The saturation current rating of the inductor must be at least as large as the high-side switch current limit, IL-HS (see the Electrical Characteristics section). This ensures that the inductor does not saturate even during a short circuit on the output. When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly. Although the valley current limit, IL-LS, is designed to reduce the risk of current run-away, a saturated inductor can cause the current to rise to high values very rapidly. This can lead to component damage; do not allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powdered iron cores exhibit a soft saturation, allowing some relaxation in the current rating of the inductor. However, they have more core losses at frequencies typically above 1 MHz. In any case, the inductor saturation current must not be less than the device high-side current limit, IL-HS (see the Electrical Characteristics section). To avoid subharmonic oscillation, the inductance value must not be less than that given in . The maximum inductance is limited by the minimum current ripple required for the current mode control to perform correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device maximum rated current under nominal conditions. (10)

being needed to manage large load transients. See the Output Capacitor Selection section.

9.2.2.4 Output Capacitor Selection

performance is desired giving 2 x 47 µF ceramic as the output capacitor and 22 pF as CFF. Table 4. Recommended Output Ceramic Capacitors and CFF Values

3.3 V OUTPUT 5 V OUTPUT

2.1 MHz Minimum 3 x 22 µF 10 pF 2 x 22 µF 22 pF

2.1 MHz Better Transient 2 x 47 µF 33 pF 3 x 22 µF 33 pF

recommended output ceramic capacitance CFF values when using an electrolytic capacitor. Table 5. Recommended Electrolytic and Ceramic Capacitor and CFF Values

9.2.2.5 Input Capacitor Selection

one at each VIN/PGND location. A single 10-μF can also be used on one side of the package.

IRMS §IOUT LM61435-Q1 www.ti.com SNVSBM0 –MARCH 2020 Product Folder Links: LM61435-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Many times, it is desirable and necessary to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially true if long leads or traces are used to connect the input supply to the converter. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high impedance. Most of the input switching current passes through the ceramic input capacitors. The approximate worst case RMS value of this current can be calculated from Equation 11 and must be checked against the manufacturers' maximum ratings. (11)

9.2.2.6 BOOT Capacitor

The LM61435-Q1 requires a bootstrap capacitor connected between the CBOOT pin and the SW pin. This capacitor stores energy that is used to supply the gate drivers for the high side power MOSFET. A high-quality (X7R) ceramic capacitor of 100 nF and at least 10 V is required.

9.2.2.7 BOOT Resistor

A BOOT resistor can be connected between the CBOOT and RBOOT pins. Unless EMI for the application being designed is critical, these two pins can be shorted. A 100-Ω resistor between these pins eliminates overshoot. Even with 0 Ω, overshoot and ringing are minimal, less than 2 V if input capacitors are placed correctly. A boot resistor of 100 Ω, which corresponds to approximately 2.7 ns SW node rise time and decreases efficiency by approximately 0.5% at 2 MHz. To maximize efficiency, 0 Ω is chosen for this example. Under most circumstances, selecting an RBOOT resistor value above 100 Ω is undesirable since the resulting small improvement in EMI is not enough to justify further decreased efficiency.

9.2.2.8 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the converter. This output requires a 1-μF, 16-V ceramic capacitor connected from VCC to AGND for proper operation. In general, avoid loading this output with any external circuitry. However, this output can be used to supply the pullup for the power-good function (see the PGOOD Output Operation section). A pullup resistor with a value of 100 kΩ is a good choice in this case. Note, VCC remains high when VEN_WAKE< EN < VEN. The nominal output voltage on VCC is 3.3 V. Do not short this output to ground or any other external voltage.

9.2.2.9 BIAS

Because VOUT = 5 V in this design, the BIAS pin is tied to VOUT to reduce LDO power loss. The output voltage is supplying the LDO current instead of the input voltage. The power saving is ILDO × (VIN – VOUT). The power saving is more significant when VIN >> VOUT and with higher frequency operation. To prevent VOUT noise and transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, can be added between VOUT and BIAS. A bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise. Note, the maximum allowed voltage on the BIAS pin is 16 V.

9.2.2.10 CFF and RFF Selection

A feedforward capacitor, Cff, is used to improve phase margin and transient response of circuits which have output capacitors with low ESR. Since this capacitor can conduct noise from the output of the circuit directly to the FB node of the IC, a 1-kΩ resistor, Rff, must be placed in series with Cff. If the ESR zero of the output capacitor is below 200 kHz, no Cff should be used. If output voltage is less than 2.5 V, Cff has little effect so can be omitted. If output voltage is greater than 14 V, Cff must not be used since it will introduce too much gain at higher frequencies.

9.2.2.11 External UVLO

voltage divider should consume. RENB can be calculated using Equation 12. Figure 32. UVLO Using EN

VON = VIN turnon voltage
VOFF = VIN turnoff voltage
IDIVIDER = voltage divider current (13)

9.2.3 Application Curves

Figure 29, with the appropriate BOM from Table 6. Figure 33. LM61435-Q1 Efficiency Figure 34. LM61435-Q1 Efficiency Figure 35. LM61435-Q1 Efficiency Figure 36. LM61435-Q1 Efficiency Figure 37. LM61435-Q1 Load and Line Regulation Figure 38. LM61435-Q1 Load and Line Regulation

10 Power Supply Recommendations

The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded converter. The average input current can be estimated with Equation 14. where

η is the efficiency (14) If the converter is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the converter. The parasitic inductance, in combination with the low-ESR, ceramic input capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to the converter or tripping UVLO. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the converter to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the distance from the input supply to the converter and use an aluminum input capacitor in parallel with the ceramics. The moderate ESR of this type of capacitor helps damp the input resonant circuit and reduce any overshoot or undershoot at the input. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help hold the input voltage steady during large load transients. In some cases, a transient voltage suppressor (TVS) is used on the input of converters. One class of this device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the output voltage of the converter, the output capacitors discharge through the device back to the input. This uncontrolled current flow can damage the TVS and cause large input transients. The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If this scenario is considered likely, then a Schottky diode between the input supply and the output must be used.

11 Layout

11.1 Layout Guidelines

Figure 73. This loop carries large transient currents that can cause large transient voltages when reacting with parasitic inductance. shows a recommended layout for the critical components for the circuit of the LM61435-Q1.

Place the input capacitor or capacitors as close as possible input pin pairs: VIN1 to PGND1 and VIN2 to PGND2. Each pair of pins are adjacent, simplifying the input capacitor placement. With the VQFN-HR package, there are two VIN/PGND pairs on either side of the package. This provides for a symmetrical layout and helps minimize switching noise and EMI generation. Use a wide VIN plane on a lower layer to connect both of the VIN pairs together to the input supply.
Place bypass capacitor for VCC close to the VCC pin and AGND pins: This capacitor must routed with short, wide traces to the VCC and AGND pins.
Use wide traces for the CBOOT capacitor: Place the CBOOT capacitor as close to the device with short, wide traces to the CBOOT and SW pins. It is important to route the SW connection under the device through the gap between VIN2 and RBOOT pins, reducing exposed SW node area. If an RBOOT resistor is used, place as close as possible to CBOOT and RBOOT pins. If high efficiency is desired, RBOOT and CBOOT pins can be shorted. This short must be placed as close as possible to RBOOT and CBOOT pins as possible.
Place the feedback divider as close as possible to the FB pin of the device: Place RFBB, RFBT, and CFF, if used, physically close to the device. The connections to FB and AGND through RFBB must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the converter.
Layer 2 of the PCB must be a ground plane: This plane acts as a noise shield and a heat dissipation path. Using layer 2 reduces the inclosed area in the input circulating current in the input loop, reducing inductance.
Provide wide paths for VIN, VOUT, and GND: These paths must be wide and direct as possible to reduce any voltage drops on the input or output paths of the converter and maximizes efficiency.
Provide enough PCB area for proper heat sinking: Enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB layers with two-ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note that the package of this device dissipates heat through all pins. Wide traces must be used for all pins except where noise considerations dictate minimization of area.
Keep switch area small: Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.

Figure 73. Input Current Loop

11.1.1 Ground and Thermal Considerations

must be used for sensitive routes.

11.2 Layout Example

Figure 74. Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

Texas Instruments, Designing High Performance, Low-EMI, Automotive Power Supplies Application Report
Texas Instruments, LM61460-Q1 EVM User's Guide
Texas Instruments, 30 W Power for Automotive Dual USB Type-C Charge Port Reference Design
Texas Instruments, EMI Filter Components and Their Nonidealities for Automotive DC/DC Regulators Technical Brief
Texas Instruments, AN-2020 Thermal Design by Insight, Not Hindsight Application Report
Texas InstrumentsOptimizing the Layout for the TPS54424/TPS54824 HotRod QFN Package for Thermal Performance Application Report
Texas Instruments, AN-2162 Simple Success With Conducted EMI From DC-DC Converters Application Report
Texas Instruments, Practical Thermal Design With DC/DC Power Modules Application Report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

Hotrod, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com SNVSBM0 –MARCH 2020 Product Folder Links: LM61435-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. space (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) space (3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. space (5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

13.1 Package Option Addendum

13.1.1 Packaging Information

Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish(3) MSL Peak Temp (4) Op Temp (°C) Device Marking(5)(6) LM61435AANQRJRRQ1 PRE_PRO D VQFN-HR RJR 14 3000 Green (RoHS & no Br/Sb) SN Level-2-260C-1 YEAR -40 to 150 61440-Q1 AAN LM61435AASQRJRRQ1 PREVIEW VQFN-HR RJR 14 3000 Green (RoHS & no Br/Sb) SN Level-2-260C-1 YEAR -40 to 150 61440-Q1 AAS LM61435AFSQRJRRQ1 PRE_PRO D VQFN-HR RJR 14 3000 Green (RoHS & no Br/Sb) SN Level-2-260C-1 YEAR -40 to 150 61440-Q1 AFS

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed LM61435-Q1 SNVSBM0 –MARCH 2020 www.ti.com Product Folder Links: LM61435-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

13.1.2 Tape and Reel Information

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LM61435AANQRJRRQ LM61435AASQRJRRQ LM61435AFSQRJRRQ

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H LM61435-Q1 www.ti.com SNVSBM0 –MARCH 2020 Product Folder Links: LM61435-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM61435AANQRJRRQ1 VQFN-HR RJR 14 3000 370.0 355.0 55.0 LM61435AASQRJRRQ1 VQFN-HR RJR 14 3000 370.0 355.0 55.0 LM61435AFSQRJRRQ1 VQFN-HR RJR 14 3000 370.0 355.0 55.0

www.ti.com PACKAGE OUTLINE C1.0 0.8

0.1 MIN

0.05 0.00 2X 0.525 2X 1.15 0.35 0.25 2X 0.45 2X 1.6 2X 0.625 2X 0.5 (0.05)

0.1 C A B

0.05 C 4X 0.45 0.35 0.05 C 6X 0.3 0.2 0.05 C 2X 0.45 0.35 0.05 C 2X 0.45 0.35 0.45 0.35 7X 0.6 0.4 2X 0.6 0.4 2X 0.9 0.7 2.2 0.05 2X 0.7 0.5 2X 0.55 0.05 C 0.4 0.3 B 4.1 3.9 A 3.6 3.4 (0.2) TYP VQFN-HR - 1 mm max heightRJR0014A PLASTIC QUAD FLATPACK - NO LEAD 4223976/D 11/2019 PIN 1 INDEX AREA SEATING PLANE 0.08 C SYMM PKG PIN 1 ID NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 3.200 SCALE 30.000SECTION A-A SECTION A-A TYPICAL LM61435-Q1 SNVSBM0 –MARCH 2020 www.ti.com Product Folder Links: LM61435-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND0.07 MAX ALL AROUND (R0.05) TYP (2.4) (0.4) (3.2) (1) (0.45) 2X (1) (0.4) 7X (0.7) 6X (0.25) (1.85) (2.9) 4X (1) 4X (0.4) 2X (0.7) (0.35) (0.3) (0.625) (0.5) (0.525) 2X (0.8) (0.4) VQFN-HR - 1 mm max heightRJR0014A PLASTIC QUAD FLATPACK - NO LEAD 4223976/D 11/2019 NOTES: (continued) 3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK DEFINED EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE: 25X SYMM PKG SEE SOLDER MASK DETAIL EXPOSED METAL METAL EDGE SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAIL EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING LM61435-Q1 www.ti.com SNVSBM0 –MARCH 2020 Product Folder Links: LM61435-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP (3.2) (1.85) (0.45) (2.9) (0.35) (1.65) 2X (1.1) 2X (0.4) 2X (1) (0.4) 7X (0.7) 6X (0.25) (0.525) (0.3) 4X (1) 4X (0.35) 2X (0.7) (0.3) (0.625) (0.5) 2X (0.8) (0.35) VQFN-HR - 1 mm max heightRJR0014A PLASTIC QUAD FLATPACK - NO LEAD 4223976/D 11/2019 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL PADS 1, 5, 9 & 11: 90% PRINTED SOLDER COVERAGE BY AREA SCALE: 25X EXPOSED METAL TYP EXPOSED METAL PKG LM61435-Q1 SNVSBM0 –MARCH 2020 www.ti.com Product Folder Links: LM61435-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

www.ti.com 12-Mar-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM61435AANQRJRRQ1 ACTIVE VQFN-HR RJR 14 3000 Green (RoHS & no Sb/Br) SN Level-2-260C-1 YEAR -40 to 150 61435Q AAN LM61435AASQRJRRQ1 ACTIVE VQFN-HR RJR 14 3000 Green (RoHS & no Sb/Br) SN Level-2-260C-1 YEAR -40 to 150 61435Q AAS LM61435AFSQRJRRQ1 ACTIVE VQFN-HR RJR 14 3000 Green (RoHS & no Sb/Br) SN Level-2-260C-1 YEAR -40 to 150 61435Q AFS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 12-Mar-2020 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated

Product Information

LM61435AANQRJRRQ1 specifications and overview.

Summary

LM61435-Q1 Automotive 3-V to 36-V, 3.5-A, Low EMI Synchronous Step-Down Converter

Description

LM61435-Q1 Automotive 3-V to 36-V, 3.5-A, Low EMI Synchronous Step-Down Converter

Source title LM61435AANQRJRRQ1 Datasheet(PDF) - Texas Instruments

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