LM6132 TI | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community LM6132,LM6134 SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 LM6132/LM6134DualandQuadLowPower10MHzRail-to-RailI/OOperationalAmplifiers
1 Features 3 Description
The LM6132/34 provides new levels of speed vs. 1• (For 5V Supply, Typ Unless Noted) power performance in applications where low voltage• Rail-to-Rail Input CMVR −0.25 V to 5.25 V supplies or power limitations previously made
- Rail-to-Rail Output Swing 0.01V to 4.99V compromise necessary. With only 360 μA/amp supply current, the 10 MHz gain-bandwidth of this device• High Gain-Bandwidth, 10 MHz at 20 kHz supports new portable applications where higher• Slew Rate 12 V/μs power devices unacceptably drain battery life.• Low Supply Current 360 μA/Amp The LM6132/34 can be driven by voltages that• Wide Supply Range 2.7 V to over 24 V exceed both power supply rails, thus eliminating
- CMRR 100 dB concerns over exceeding the common-mode voltage range. The rail-to-rail output swing capability provides• Gain 100 dB with RL = 10 k the maximum possible dynamic range at the output.• PSRR 82 dB This is particularly important when operating on low supply voltages. The LM6132/34 can also drive large2 Applications capacitive loads without oscillating.
- Battery Operated Instrumentation Operating on supplies from 2.7 V to over 24 V, the
- Instrumentation Amplifiers LM6132/34 is excellent for a very wide range of applications, from battery operated systems with• Portable Scanners large bandwidth requirements to high speed• Wireless Communications instrumentation.• Flat Panel Display Driver Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM6132 SOIC (8) 4.90 mm x 3.91 mm LM6132 PDIP (8) 9.81 mm x 6.35 mm LM6134 SOIC (14) 8.65 mm x 3.91 mm LM6134 PDIP (14) 19.177 mm x 6.35 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Offset Voltage vs. Supply VoltageSupply Current vs. Supply Voltage An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM6132,LM6134 SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (February 2013) to Revision E Page Changes from Revision C (February 2013) to Revision D Page
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Product Folder Links: LM6132 LM6134
LM6132,LM6134 www.ti.com SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014
5 Pin Configuration and Functions
8-Pin SOIC/PDIP 14-Pin SOIC/PDIP Packages D and P Packages D and NFF Top View Top View Pin Functions PIN LM6132 LM6134 I/O DESCRIPTION NAME D/NFF0014D/P A -IN A 2 2 I ChA Inverting Input +IN A 3 3 I ChA Non-inverting Input -IN B 6 6 I ChB Inverting Input +IN B 5 5 I ChB Non-inverting Input -IN C 9 I ChC Inverting Input +IN C 10 I ChC Non-inverting Input -IN D 13 I ChD Inverting Input +IN D 12 I ChD Non-inverting Input OUT A 1 1 O ChA Output OUT B 7 7 O ChB Output OUT C 8 O ChC Output OUT D 14 O ChD Output V- 4 11 I Negative Supply V+ 8 4 I Positive Supply Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM6132 LM6134
LM6132,LM6134 SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Differential Input Voltage ±15 V (V+)+0.3Voltage at Input/Output Pin V(V−)−0.3 Supply Voltage (V+–V−) 35 V Current at Input Pin ±10 mA Current at Output Pin(3) ±25 mA Current at Power Supply Pin 50 mA Lead Temp. (soldering, 10 sec.) 260 °C Junction Temperature(4) 150 °C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical characteristics. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. (3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. (4) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA)/RθJA. All numbers apply for packages soldered directly into a PC board.
6.2 Handling Ratings
Tstg Storage temperature range −65 +150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2500V(ESD) Electrostatic discharge Vpins(1) (1) Human Body Model, 1.5 kΩ in series with 100 pF .JEDEC document JEP155 states that 2500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply Voltage 1.8 ≤ V+ ≤ 24 V Operating Temperature Range: LM6132, LM6134 −40 +85 °C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical characteristics.
6.4 Thermal Information, 8-Pin
D (SOIC) P (PDIP) THERMAL METRIC(1) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 193 115 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information, 14-Pin
D (SOIC) NFF (PDIP) THERMAL METRIC(1) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 126 81 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: LM6132 LM6134
LM6132,LM6134 www.ti.com SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 6.6 5.0V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 5.0V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extremes LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) VOS Input Offset Voltage 2 6 mV0.25 4 8 max TCVOS Input Offset Voltage Average Drift 5 μV/C IB Input Bias Current 0V ≤ VCM ≤ 5V 140 180 nA110 300 350 max IOS Input Offset Current 30 30 nA3.4 50 50 max RIN Input Resistance, CM 104 MΩ CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 4V 75 75100 70 70 dB min0V ≤ VCM ≤ 5V 60 6080 55 55 PSRR Power Supply Rejection Ratio ±2.5V ≤ V+ ≤ ±12V 78 78 dB82 75 75 min VCM −0.25 0 0Input Common-Mode Voltage Range V5.25 5.0 5.0 AV Large Signal Voltage Gain RL = 10k 25 15 V/mV100 8 6 min ISC Output Short Circuit Current Sourcing 2 2 mA4LM6132 2 1 min Sinking 1.8 1.8 mA3.5 1.8 1 min ISC Output Short Circuit Current Sourcing 2 2 mA3LM6134 1.6 1 min Sinking 1.8 1.8 mA3.5 1.3 1 min IS Supply Current Per Amplifier 400 400 μA360 450 450 max (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM6132 LM6134
LM6132,LM6134 SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 www.ti.com 6.7 5.0V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 5.0V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extremes LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) SR Slew Rate ±4V @ VS = ±6V 8 8 V/μs14RS < 1 kΩ 7 7 min GBW Gain-Bandwidth Product f = 20 kHz 7.4 7.4 MHz10 7 7 min θm Phase Margin RL = 10k 33 deg Gm Gain Margin RL = 10k 10 dB en Input Referred Voltage Noise f = 1 kHz 27 nV/√Hz in Input Referred Current Noise f = 1 kHz 0.18 pA/√Hz (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. 6.8 2.7V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extreme LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) VOS Input Offset Voltage 2 6 mV0.12 8 12 max IB Input Bias Current 0V ≤ VCM ≤ 2.7V 90 nA IOS Input Offset Current 2.8 nA RIN Input Resistance 134 MΩ CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 2.7V 82 dB PSRR Power Supply Rejection Ratio ±1.35V ≤ V+ ≤ ±12V 80 dB VCM Input Common-Mode Voltage Range 2.7 2.7 V 0 0 AV Large Signal Voltage Gain RL = 10k 100 V/mV IS Supply Current Per Amplifier 330 μA (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. 6.9 2.7V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. LM6134AI LM6134BI TYP LM6132AI LM6132BIPARAMETER TEST CONDITIONS UNIT(1) LIMIT LIMIT (2) (2) GBW Gain-Bandwidth Product RL = 10k, f = 20 kHz 7 MHz θm Phase Margin RL = 10k 23 deg Gm Gain Margin 12 dB (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis.
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Product Folder Links: LM6132 LM6134
LM6132,LM6134 www.ti.com SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 6.10 24V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 24V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extreme LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) VOS Input Offset Voltage 3 7 mV1.7 5 9 max IB Input Bias Current 0V ≤ VCM ≤ 24V 125 nA IOS Input Offset Current 4.8 nA RIN Input Resistance 210 MΩ CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 24V 80 dB PSRR Power Supply Rejection Ratio 2.7V ≤ V+ ≤ 24V 82 dB VCM Input Common-Mode Voltage Range −0.25 0 0 V min 24.25 24 24 V max AV Large Signal Voltage Gain RL = 10k 102 V/mV VO Output Swing RL = 10k V max0.075 0.15 0.15 23.86 23.8 23.8 V min IS Supply Current Per Amplifier 450 450 μA390 490 490 max (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. 6.11 24V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 24V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) GBW Gain-Bandwidth Product RL = 10k, f = 20 kHz 11 MHz θm Phase Margin RL = 10k 23 deg Gm Gain Margin RL = 10k 12 dB THD + N Total Harmonic Distortion and Noise AV = +1, VO = 20VP-P 0.0015%f = 10 kHz (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM6132 LM6134
6.12 Typical Performance Characteristics
Figure 1. Supply Current vs. Supply Voltage Figure 2. Offset Voltage vs. Supply Voltage Figure 3. dVOS vs. VCM Figure 4. dVOS vs. VCM Figure 5. dVOS vs. VCM Figure 6. IBIAS vs. VCM
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Figure 13. dVOS vs. Output Voltage Figure 14. dVOS vs. Output Voltage Figure 15. CMRR vs. Frequency Figure 16. Output Voltage vs. Sinking Current Figure 17. Output Voltage vs. Sinking Current Figure 18. Output Voltage vs. Sinking Current
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Figure 25. Gain and Phase vs. Frequency Figure 26. Gain and Phase vs. Frequency Figure 27. Gain and Phase vs. Frequency Figure 28. GBW vs. Supply Voltage at 20 kHz
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7 Application and Implementation
7.1 Application Information
eliminates concern over exceeding the common-mode voltage range. important when operating on low supply voltages. consumption previously reduced battery life to unacceptable levels.
7.2 Enhanced Slew Rate
phase reversal and allows the slew rate to be a function of the input signal amplitude. the current mirrors through the collectors of Q1–Q2, Q3–Q4 when the input levels are normal. the two additional transistors, (Q5, Q6), directly into the current mirrors. The rerouting of excess signal allows the slew-rate to increase by a factor of 10 to 1 or more. (See Figure 29). slew rate to around 25V to 30 V/μs. Figure 29. Slew Rate vs. Differential VIN This speed-up action adds stability to the system when driving large capacitive loads.
7.2.1 Driving Capacitive Loads
input voltage drops down and the amplifier settles rapidly. Figure 30. Internal Block Diagram
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Figure 33. Cap Load Test Circuit resistor RO at the output and a feedback capacitor CFdirectly between the output and the inverting input pin. size of the load capacitance, the value of ROis typically chosen to be between 100 Ω to 1 kΩ. Figure 34. Capacitive Loading Compensation Technique
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7.3 Typical Applications
7.3.1 Three Op Amp Instrumentation Amp with Rail-to-Rail Input and Output
Using the LM6134, a 3 op amp instrumentation amplifier with rail-to-rail inputs and rail to rail output can be made. These features make these instrumentation amplifiers ideal for single supply systems. as well. Using the LM6134, all of these problems are eliminated. maintain the CMR set by the matching of R1–R2 with R3–R4. Figure 35. Instrumentation Amplifier
7.3.2 Flat Panel Display Buffering
highly capacitive loads that are characteristic of LCD display drivers. eliminates the need to search for multiple sources for new designs.
8 Device and Documentation Support
8.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 1. Related Links
8.2 Trademarks
All trademarks are the property of their respective owners.
8.3 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
8.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM6132AIM/NOPB Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 LM61 32AIM LM6132AIMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132AIMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132AIMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132BIMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6132 BIN LM6132BIN/NOPB.A Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6132 BIN LM6132BIN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6132 BIN LM6134AIM/NOPB Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 LM6134AIM LM6134AIMX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM6134AIM LM6134AIMX/NOPB.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM6134AIM LM6134AIMX/NOPB.B Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI -40 to 85 LM6134BIM/NOPB Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 LM6134BIM LM6134BIMX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM6134BIM LM6134BIMX/NOPB.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM6134BIM LM6134BIMX/NOPB.B Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI -40 to 85 LM6134BIN/NOPB Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6134BIN LM6134BIN/NOPB.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6134BIN LM6134BIN/NOPB.B Active Production PDIP (N) | 14 25 | TUBE - Call TI Call TI -40 to 85 Addendum-Page 1
www.ti.com 7-Oct-2025 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM6132AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM6132BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM6134AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LM6134BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM6132BIN/NOPB P PDIP 8 40 502 14 11938 4.32 LM6132BIN/NOPB.A P PDIP 8 40 502 14 11938 4.32 LM6132BIN/NOPB.B P PDIP 8 40 502 14 11938 4.32 LM6134BIN/NOPB N PDIP 14 25 502 14 11938 4.32 LM6134BIN/NOPB.A N PDIP 14 25 502 14 11938 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C TYP6.2 5.8
1.75 MAX
12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800
www.ti.com EXAMPLE BOARD LAYOUT (5.4)
0.07 MAX
0.07 MIN
14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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