LM6132 TI1 | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community LM6132,LM6134 SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 LM6132/LM6134DualandQuadLowPower10MHzRail-to-RailI/OOperationalAmplifiers
1 Features 3 Description
The LM6132/34 provides new levels of speed vs. 1• (For 5V Supply, Typ Unless Noted) power performance in applications where low voltage• Rail-to-Rail Input CMVR −0.25 V to 5.25 V supplies or power limitations previously made
- Rail-to-Rail Output Swing 0.01V to 4.99V compromise necessary. With only 360 μA/amp supply current, the 10 MHz gain-bandwidth of this device• High Gain-Bandwidth, 10 MHz at 20 kHz supports new portable applications where higher• Slew Rate 12 V/μs power devices unacceptably drain battery life.• Low Supply Current 360 μA/Amp The LM6132/34 can be driven by voltages that• Wide Supply Range 2.7 V to over 24 V exceed both power supply rails, thus eliminating
- CMRR 100 dB concerns over exceeding the common-mode voltage range. The rail-to-rail output swing capability provides• Gain 100 dB with RL = 10 k the maximum possible dynamic range at the output.• PSRR 82 dB This is particularly important when operating on low supply voltages. The LM6132/34 can also drive large2 Applications capacitive loads without oscillating.
- Battery Operated Instrumentation Operating on supplies from 2.7 V to over 24 V, the
- Instrumentation Amplifiers LM6132/34 is excellent for a very wide range of applications, from battery operated systems with• Portable Scanners large bandwidth requirements to high speed• Wireless Communications instrumentation.• Flat Panel Display Driver Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM6132 SOIC (8) 4.90 mm x 3.91 mm LM6132 PDIP (8) 9.81 mm x 6.35 mm LM6134 SOIC (14) 8.65 mm x 3.91 mm LM6134 PDIP (14) 19.177 mm x 6.35 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Offset Voltage vs. Supply VoltageSupply Current vs. Supply Voltage An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM6132,LM6134 SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (February 2013) to Revision E Page Changes from Revision C (February 2013) to Revision D Page
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Product Folder Links: LM6132 LM6134
LM6132,LM6134 www.ti.com SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014
5 Pin Configuration and Functions
8-Pin SOIC/PDIP 14-Pin SOIC/PDIP Packages D and P Packages D and NFF Top View Top View Pin Functions PIN LM6132 LM6134 I/O DESCRIPTION NAME D/NFF0014D/P A -IN A 2 2 I ChA Inverting Input +IN A 3 3 I ChA Non-inverting Input -IN B 6 6 I ChB Inverting Input +IN B 5 5 I ChB Non-inverting Input -IN C 9 I ChC Inverting Input +IN C 10 I ChC Non-inverting Input -IN D 13 I ChD Inverting Input +IN D 12 I ChD Non-inverting Input OUT A 1 1 O ChA Output OUT B 7 7 O ChB Output OUT C 8 O ChC Output OUT D 14 O ChD Output V- 4 11 I Negative Supply V+ 8 4 I Positive Supply Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM6132 LM6134
LM6132,LM6134 SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Differential Input Voltage ±15 V (V+)+0.3Voltage at Input/Output Pin V(V−)−0.3 Supply Voltage (V+–V−) 35 V Current at Input Pin ±10 mA Current at Output Pin(3) ±25 mA Current at Power Supply Pin 50 mA Lead Temp. (soldering, 10 sec.) 260 °C Junction Temperature(4) 150 °C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical characteristics. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. (3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. (4) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA)/RθJA. All numbers apply for packages soldered directly into a PC board.
6.2 Handling Ratings
Tstg Storage temperature range −65 +150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2500V(ESD) Electrostatic discharge Vpins(1) (1) Human Body Model, 1.5 kΩ in series with 100 pF .JEDEC document JEP155 states that 2500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply Voltage 1.8 ≤ V+ ≤ 24 V Operating Temperature Range: LM6132, LM6134 −40 +85 °C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical characteristics.
6.4 Thermal Information, 8-Pin
D (SOIC) P (PDIP) THERMAL METRIC(1) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 193 115 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information, 14-Pin
D (SOIC) NFF (PDIP) THERMAL METRIC(1) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 126 81 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: LM6132 LM6134
LM6132,LM6134 www.ti.com SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 6.6 5.0V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 5.0V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extremes LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) VOS Input Offset Voltage 2 6 mV0.25 4 8 max TCVOS Input Offset Voltage Average Drift 5 μV/C IB Input Bias Current 0V ≤ VCM ≤ 5V 140 180 nA110 300 350 max IOS Input Offset Current 30 30 nA3.4 50 50 max RIN Input Resistance, CM 104 MΩ CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 4V 75 75100 70 70 dB min0V ≤ VCM ≤ 5V 60 6080 55 55 PSRR Power Supply Rejection Ratio ±2.5V ≤ V+ ≤ ±12V 78 78 dB82 75 75 min VCM −0.25 0 0Input Common-Mode Voltage Range V5.25 5.0 5.0 AV Large Signal Voltage Gain RL = 10k 25 15 V/mV100 8 6 min ISC Output Short Circuit Current Sourcing 2 2 mA4LM6132 2 1 min Sinking 1.8 1.8 mA3.5 1.8 1 min ISC Output Short Circuit Current Sourcing 2 2 mA3LM6134 1.6 1 min Sinking 1.8 1.8 mA3.5 1.3 1 min IS Supply Current Per Amplifier 400 400 μA360 450 450 max (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM6132 LM6134
LM6132,LM6134 SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 www.ti.com 6.7 5.0V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 5.0V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extremes LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) SR Slew Rate ±4V @ VS = ±6V 8 8 V/μs14RS < 1 kΩ 7 7 min GBW Gain-Bandwidth Product f = 20 kHz 7.4 7.4 MHz10 7 7 min θm Phase Margin RL = 10k 33 deg Gm Gain Margin RL = 10k 10 dB en Input Referred Voltage Noise f = 1 kHz 27 nV/√Hz in Input Referred Current Noise f = 1 kHz 0.18 pA/√Hz (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. 6.8 2.7V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extreme LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) VOS Input Offset Voltage 2 6 mV0.12 8 12 max IB Input Bias Current 0V ≤ VCM ≤ 2.7V 90 nA IOS Input Offset Current 2.8 nA RIN Input Resistance 134 MΩ CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 2.7V 82 dB PSRR Power Supply Rejection Ratio ±1.35V ≤ V+ ≤ ±12V 80 dB VCM Input Common-Mode Voltage Range 2.7 2.7 V 0 0 AV Large Signal Voltage Gain RL = 10k 100 V/mV IS Supply Current Per Amplifier 330 μA (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. 6.9 2.7V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. LM6134AI LM6134BI TYP LM6132AI LM6132BIPARAMETER TEST CONDITIONS UNIT(1) LIMIT LIMIT (2) (2) GBW Gain-Bandwidth Product RL = 10k, f = 20 kHz 7 MHz θm Phase Margin RL = 10k 23 deg Gm Gain Margin 12 dB (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis.
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Product Folder Links: LM6132 LM6134
LM6132,LM6134 www.ti.com SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014 6.10 24V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 24V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extreme LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) VOS Input Offset Voltage 3 7 mV1.7 5 9 max IB Input Bias Current 0V ≤ VCM ≤ 24V 125 nA IOS Input Offset Current 4.8 nA RIN Input Resistance 210 MΩ CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 24V 80 dB PSRR Power Supply Rejection Ratio 2.7V ≤ V+ ≤ 24V 82 dB VCM Input Common-Mode Voltage Range −0.25 0 0 V min 24.25 24 24 V max AV Large Signal Voltage Gain RL = 10k 102 V/mV VO Output Swing RL = 10k V max0.075 0.15 0.15 23.86 23.8 23.8 V min IS Supply Current Per Amplifier 450 450 μA390 490 490 max (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. 6.11 24V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ = 24V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. LM6134AI LM6134BI PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT LIMIT(2) LIMIT(2) GBW Gain-Bandwidth Product RL = 10k, f = 20 kHz 11 MHz θm Phase Margin RL = 10k 23 deg Gm Gain Margin RL = 10k 12 dB THD + N Total Harmonic Distortion and Noise AV = +1, VO = 20VP-P 0.0015%f = 10 kHz (1) Typical Values represent the most likely parametric normal. (2) All limits are guaranteed by testing or statistical analysis. Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM6132 LM6134
6.12 Typical Performance Characteristics
Figure 1. Supply Current vs. Supply Voltage Figure 2. Offset Voltage vs. Supply Voltage Figure 3. dVOS vs. VCM Figure 4. dVOS vs. VCM Figure 5. dVOS vs. VCM Figure 6. IBIAS vs. VCM
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Figure 13. dVOS vs. Output Voltage Figure 14. dVOS vs. Output Voltage Figure 15. CMRR vs. Frequency Figure 16. Output Voltage vs. Sinking Current Figure 17. Output Voltage vs. Sinking Current Figure 18. Output Voltage vs. Sinking Current
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Figure 25. Gain and Phase vs. Frequency Figure 26. Gain and Phase vs. Frequency Figure 27. Gain and Phase vs. Frequency Figure 28. GBW vs. Supply Voltage at 20 kHz
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7 Application and Implementation
7.1 Application Information
eliminates concern over exceeding the common-mode voltage range. important when operating on low supply voltages. consumption previously reduced battery life to unacceptable levels.
7.2 Enhanced Slew Rate
phase reversal and allows the slew rate to be a function of the input signal amplitude. the current mirrors through the collectors of Q1–Q2, Q3–Q4 when the input levels are normal. the two additional transistors, (Q5, Q6), directly into the current mirrors. The rerouting of excess signal allows the slew-rate to increase by a factor of 10 to 1 or more. (See Figure 29). slew rate to around 25V to 30 V/μs. Figure 29. Slew Rate vs. Differential VIN This speed-up action adds stability to the system when driving large capacitive loads.
7.2.1 Driving Capacitive Loads
input voltage drops down and the amplifier settles rapidly. Figure 30. Internal Block Diagram
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Figure 33. Cap Load Test Circuit resistor RO at the output and a feedback capacitor CFdirectly between the output and the inverting input pin. size of the load capacitance, the value of ROis typically chosen to be between 100 Ω to 1 kΩ. Figure 34. Capacitive Loading Compensation Technique
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7.3 Typical Applications
7.3.1 Three Op Amp Instrumentation Amp with Rail-to-Rail Input and Output
Using the LM6134, a 3 op amp instrumentation amplifier with rail-to-rail inputs and rail to rail output can be made. These features make these instrumentation amplifiers ideal for single supply systems. as well. Using the LM6134, all of these problems are eliminated. maintain the CMR set by the matching of R1–R2 with R3–R4. Figure 35. Instrumentation Amplifier
7.3.2 Flat Panel Display Buffering
highly capacitive loads that are characteristic of LCD display drivers. eliminates the need to search for multiple sources for new designs.
8 Device and Documentation Support
8.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 1. Related Links
8.2 Trademarks
All trademarks are the property of their respective owners.
8.3 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
8.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 9-Aug-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM6132AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM61 32AIM LM6132AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132AIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM61 32AIM LM6132AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132BIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM61 32BIM LM6132BIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM61 32BIM LM6132BIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LM6132 BIN LM6134AIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM6134AIM LM6134AIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134AIM LM6134AIMX NRND SOIC D 14 TBD Call TI Call TI -40 to 85 LM6134AIM LM6134AIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134AIM LM6134BIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM6134BIM LM6134BIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134BIM LM6134BIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134BIM LM6134BIN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LM6134BIN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
www.ti.com 9-Aug-2016 Addendum-Page 2 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM6132AIMX SOIC D 8 2500 367.0 367.0 35.0 LM6132AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM6132BIMX SOIC D 8 2500 367.0 367.0 35.0 LM6132BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM6134AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LM6134BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 Pack Materials-Page 2
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