LM5001SDX/NOPB.B

LM5001 TI | Alldatasheet

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+12V to +36V +48V Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LM5001,LM5001-Q1 SNVS484H –JANUARY 2007–REVISED JULY 2015 LM5001xHigh-VoltageSwitch-ModeRegulator

1 Features 3 Description

The LM5001 high-voltage switch-mode regulator 1• AEC-Q100 Qualified (TJ = –40°C to 125°C) features all of the functions necessary to implement• Integrated 75-V N-Channel MOSFET efficient high-voltage Boost, Flyback, SEPIC and

• Ultra-Wide Input Voltage Range from Forward converters, using few external components.

3.1 V to 75 V This easy-to-use regulator integrates a 75-V N-

Channel MOSFET with a 1-A peak current limit.• Integrated High Voltage Bias Regulator Current mode control provides inherently simple loop• Adjustable Output Voltage compensation and line-voltage feed-forward for

• 1.5% Output Voltage Accuracy superior rejection of input transients. The switching frequency is set with a single resistor and is• Current Mode Control with Selectable programmable up to 1.5 MHz. The oscillator can alsoCompensation be synchronized to an external clock. Additional• Wide Bandwidth Error Amplifier protection features include: current limit, thermal
• Integrated Current Sensing and Limiting shutdown, undervoltage lockout and remote shutdown capability.• Integrated Slope Compensation
• 85% Maximum Duty Cycle Limit Device Information(1)
• Single Resistor Oscillator Programming DEVICE NAME PACKAGE BODY SIZE
• Oscillator Synchronization Capability SOIC (8) 4.9 mm x 3.91 mm LM5001• Enable / Undervoltage Lockout (UVLO) Pin WSON (8) 4 mm x 4 mm
• Thermal Shutdown LM5001Q1 SOIC (8) 4.9 mm x 3.91 mm (1) For all available packages, see the orderable addendum at2 Applications the end of the datasheet.
• DC-DC Power Supplies for Industrial, Communications, and Automotive Applications
• Boost, Flyback, SEPIC and Forward Converter Topologies An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5001,LM5001-Q1 SNVS484H –JANUARY 2007–REVISED JULY 2015 www.ti.com Table of Contents

4 Revision History

Changes from Revision G (April 2014) to Revision H Page Changes from Revision F (March 2013) to Revision G Page Changes from Revision E (March 2013) to Revision F Page

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Product Folder Links: LM5001 LM5001-Q1

LM5001,LM5001-Q1 www.ti.com SNVS484H –JANUARY 2007–REVISED JULY 2015

5 Pin Configuration and Functions

SOIC (D) 8 Pins Top View WSON (NGT) 8 Pins Top View Pin Functions PIN NAME TYPE DESCRIPTION SOIC WSON 1 3 SW Switch pin The drain terminal of the internal power MOSFET. 2 4 VIN Input supply pin Nominal operating range: 3.1 V to 75 V. VCC tracks VIN up to 6.9 V. Above VIN = 6.9 V, VCC is regulated to 6.9 V. A 0.47-µF or greater ceramic decoupling Bias regulator output, or input for external capacitor is required. An external voltage (7 V – 12 V) can3 5 VCC bias supply be applied to this pin which disables the internal VCC regulator to reduce internal power dissipation and improve converter efficiency. Internal reference for the regulator control functions and the4 6 GND Ground power MOSFET current sense resistor connection. The internal oscillator is set with a resistor, between this pin and the GND pin. The recommended frequency range is 50 Oscillator frequency programming and KHz to 1.5 MHz. The RT pin can accept synchronization5 7 RT optional synchronization pulse input pulses from an external clock. A 100-pF capacitor is recommended for coupling the synchronizing clock to the RT pin. This pin is connected to the inverting input of the internalFeedback input from the regulated output6 8 FB error amplifier. The 1.26-V reference is internally connectedvoltage to the non-inverting input of the error amplifier. The loop compensation network should be connected between the COMP pin and the FB pin. COMP pull-up isOpen drain output of the internal error7 1 COMP provided by an internal 5-kΩ resistor which may be used toamplifier bias an opto-coupler transistor (while FB is grounded) for isolated ground applications. An external voltage divider can be used to set the line Enable / Undervoltage Lock-Out / undervoltage lockout threshold. If the EN pin is left8 2 EN Shutdown input unconnected, a 6-µA pull-up current source pulls the EN pin high to enable the regulator. Exposed metal pad on the underside of the package with a resistive connection to pin 6. It is recommended to connectNA EP EP Exposed Pad, WSON only this pad to the PC board ground plane in order to improve heat dissipation. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5001 LM5001-Q1

LM5001,LM5001-Q1 SNVS484H –JANUARY 2007–REVISED JULY 2015 www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN to GND 76 V SW to GND (Steady State) –0.3 76 V VCC, EN to GND 14 V COMP, FB, RT to GND –0.3 7 V Maximum Junction Temperature 150 °C Storage Temperature Range, Tstg -65 150 °C

6.2 ESD Ratings

Human-body model (HBM), per AEC Q100-002(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per AEC Q100-011 ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

VIN 3.1 75 V Operating Junction Temperature −40 125 °C

6.4 Thermal Information

THERMAL METRIC SOIC SOIC WSON UNIT (8 PINS) RθJA Junction-to-ambient thermal resistance 140 140 40 °C/W RθJCtop Junction-to-case (top) thermal resistance 32 32 4.5

6.5 Electrical Characteristics

Minimum and Maximum limits are ensured through test, design, or statistical correlation, over the junction temperature (TJ) range of –40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VVIN = 10 V, RRT = 48.7 kΩ unless otherwise stated(1). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Startup Regulator VVCC-REG VCC Regulator Output 6.55 6.85 7.15 V VCC Current Limit VVCC = 6 V 15 20 mA VCC UVLO Threshold VVCC increasing 2.6 2.8 3 V VCC Undervoltage Hysteresis 0.1 Bias Current (IIN) VFB = 1.5 V 3.1 4.5 mA IQ Shutdown Current (IIN) VEN = 0V 95 130 µA (1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).

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LM5001,LM5001-Q1 www.ti.com SNVS484H –JANUARY 2007–REVISED JULY 2015 Electrical Characteristics (continued) Minimum and Maximum limits are ensured through test, design, or statistical correlation, over the junction temperature (TJ) range of –40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VVIN = 10 V, RRT = 48.7 kΩ unless otherwise stated(1). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN Thresholds EN Shutdown Threshold VEN increasing 0.25 0.45 0.65 EN Shutdown Hysteresis 0.1 V EN Standby Threshold VEN increasing 1.2 1.26 1.32 EN Standby Hysteresis 0.1 EN Current Source 6 µA MOSFET Characteristics MOSFET RDS(ON) plus LM5001 490 800 ID = 0.5 A mΩCurrent Sense Resistance LM5001-Q1 490 880 MOSFET Leakage Current VSW = 75 V 0.05 5 µA MOSFET Gate Charge VVCC = 6.9 V 4.5 nC Current Limit ILIM Cycle by Cycle Current Limit 0.8 1.0 1.2 A Cycle by Cycle Current Limit Delay 100 200 ns Oscillator FSW1 Frequency1 RRT = 48.7 kΩ 225 260 295 KHz FSW2 Frequency2 RRT = 15.8 kΩ 660 780 900 VRT-SYNC SYNC Threshold 2.2 2.6 3.2 V SYNC Pulse Width Minimum VRT > VRT-SYNC + 0.5 V 15 ns PWM Comparator Maximum Duty Cycle 80% 85% 90% Min On-time VCOMP > VCOMP-OS 35 ns Min On-time VCOMP < VCOMP-OS 0 VCOMP-OS COMP to PWM Comparator Offset 0.9 1.30 1.55 V Error Amplifier VFB-REF Internal referenceFeedback Reference Voltage 1.241 1.260 1.279 VVFB = VCOMP FB Bias Current 10 nA DC Gain 72 dB COMP Sink Current VCOMP = 250 mV 2.5 mA COMP Short Circuit Current VFB = 0, VCOMP = 0 0.9 1.2 1.5 COMP Open Circuit Voltage VFB = 0 4.8 5.5 6.2 V COMP to SW Delay 50 ns Unity Gain Bandwidth 3 MHz Thermal Shutdown TSD Thermal Shutdown Threshold 165 Thermal Shutdown Hysteresis 20 Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM5001 LM5001-Q1

6.6 Typical Characteristics

Figure 1. Efficiency, Boost Converter Figure 2. VFB vs Temperature Figure 3. IQ (Non-Switching) vs VIN Figure 4. VCC vs VIN Figure 5. RDS(ON) vs VCC Figure 6. RDS(ON) vs Temperature

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(Leading Edge Blanking) RAMP S R Q VCC ENABLE ENABLE Disable VCCENABLE CSCS RAMP CS SLOPE COMP RAMP 450 mV Disable ENABLE CLK CURRENT LIMIT 1.5V 1.3V +5V 1.26V CURRENT SENSE 50 m/c3a 1.26V +5V +6.9V 2.8V 0.45V6 /c50A REFERENCE GENERATOR Av = 30 0.7 THERMAL STANDBY (165oC) OSCILLATOR WITH SYNC CAPABILITY 1.26V LM5001,LM5001-Q1 SNVS484H –JANUARY 2007–REVISED JULY 2015 www.ti.com

7 Detailed Description

7.1 Overview

The LM5001 high voltage switching regulator features all the functions necessary to implement an efficient boost, flyback, SEPIC or forward current mode power converter. The operation can be best understood by referring to the block diagram. At the start of each cycle, the oscillator sets the driver logic and turns on the power MOSFET to conduct current through the inductor or transformer. The peak current in the MOSFET is controlled by the voltage at the COMP pin. The COMP voltage increases with larger loads and decrease with smaller loads. This voltage is compared with the sum of a voltage proportional to the power MOSFET current and an internally generated Slope Compensation ramp. Slope Compensation is used in current mode PWM architectures to eliminate sub-harmonic current oscillation that occurs with static duty cycles greater than 50%. When the summed signal exceeds the COMP voltage, the PWM comparator resets the driver logic, turning off the power MOSFET. The driver logic is then set by the oscillator at the end of the switching cycle to initiate the next power period. The LM5001 has dedicated protection circuitry to protect the IC from abnormal operating conditions. Cycle-by- cycle current limiting prevents the power MOSFET current from exceeding 1 A. This feature can also be used to soft-start the regulator. Thermal Shutdown circuitry holds the driver logic in reset when the die temperature reaches 165°C, and returns to normal operation when the die temperature drops by approximately 20°C. The EN pin can be used as an input voltage undervoltage lockout (UVLO) during start-up to prevent operation with less than the minimum desired input voltage.

7.2 Functional Block Diagram

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RT = 13.1 x 109 x FSW - 83 ns LM5001,LM5001-Q1 www.ti.com SNVS484H –JANUARY 2007–REVISED JULY 2015

7.3 Feature Description

7.3.1 High-Voltage VCC Regulator

The LM5001 VCC Low Drop Out (LDO) regulator allows the LM5001 to operate at the lowest possible input voltage. The VCC pin voltage is very nearly equal to the input voltage from 2.8 V up to approximately 6.9 V. As the input voltage continues to increase, the VCC pin voltage is regulated at the 6.9 V set-point. The total input operating range of the VCC LDO regulator is 3.1 V to 75 V. The output of the VCC regulator is current limited to 20 mA. During power up, the VCC regulator supplies current into the required decoupling capacitor (0.47 µF or greater ceramic capacitor) at the VCC pin. When the voltage at the VCC pin exceeds the VCC UVLO threshold of 2.8 V and the EN pin is greater than 1.26 V the PWM controller is enabled and switching begins. The controller remains enabled until VCC falls below 2.7 V or the EN pin falls below 1.16 V. An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary voltage is greater than 6.9 V, the internal regulator essentially shuts off, and internal power dissipation decreases by the VIN voltage times the operating current. The overall converter efficiency improves if the VIN voltage is much higher than the auxiliary voltage. The externally applied VCC voltage should not exceed 14 V. The VCC regulator series pass MOSFET includes a body diode (Functional Block Diagram ) between VCC and VIN that should not be forward biased in normal operation. Therefore, the auxiliary VCC voltage should never exceed the VIN voltage. In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 76 V. Voltage ringing on the VIN line during line transients that exceeds the Absolute Maximum Ratings damages the IC. Both careful PC board layout and the use of quality bypass capacitors located close to the VIN and GND pins are essential.

7.3.2 Oscillator

A single external resistor connected between RT and GND pins sets the LM5001 oscillator frequency. To set a desired oscillator frequency (FSW), the necessary value for the RT resistor can be calculated from: (1) The tolerance of the external resistor and the frequency tolerance indicated in the Electrical Characteristics must be taken into account when determining the worst case frequency range.

7.3.3 External Synchronization

The LM5001 can be synchronized to the rising edge of an external clock. The external clock must have a higher frequency than the free running oscillator frequency set by the RT resistor. The clock signal should be coupled through a 100 pF capacitor into the RT pin. A peak voltage level greater than 2.6 V at the RT pin is required for detection of the sync pulse. The DC voltage across the RT resistor is internally regulated at 1.5 V. The negative portion of the AC voltage of the synchronizing clock is clamped to this 1.5 V by an amplifier inside the LM5001 with ~100 Ω output impedance. Therefore, the AC pulse superimposed on the RT resistor must have positive pulse amplitude of 1.1 V or greater to successfully synchronize the oscillator. The sync pulse width measured at the RT pin should have a duration greater than 15 ns and less than 5% of the switching period. The sync pulse rising edge initiates the internal CLK signal rising edge, which turns off the power MOSFET. The RT resistor is always required, whether the oscillator is free running or externally synchronized. The RT resistor should be located very close to the device and connected directly to the RT and GND pins of the LM5001.

7.3.4 Enable / Standby

The LM5001 contains a dual level Enable circuit. When the EN pin voltage is below 450 mV, the IC is in a low current shutdown mode with the VCC LDO disabled. When the EN pin voltage is raised above the shutdown threshold but below the 1.26 V standby threshold, the VCC LDO regulator is enabled, while the remainder of the IC is disabled. When the EN pin voltage is raised above the 1.26 V standby threshold, all functions are enabled and normal operation begins. An internal 6 µA current source pulls up the EN pin to activate the IC when the EN pin is left disconnected. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM5001 LM5001-Q1

Zener voltage, however the Zener current should be limited to less than 4 mA.

7.3.5 Error Amplifier and PWM Comparator

COMP pin allowing the user to add loop compensation, typically a Type II network, as illustrated in Figure 13. amplifier output voltage at the COMP pin. Figure 13. Type II Compensator connecting the FB pin to GND. This allows the COMP pin to be driven directly by the collector of an opto-coupler. regulator with an opto-coupler is shown in Figure 19.

7.3.6 Current Amplifier and Slope Compensation

the current limit comparator is triggered, the SW output pin immediately switches to a high impedance state.

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LM5001,LM5001-Q1 www.ti.com SNVS484H –JANUARY 2007–REVISED JULY 2015 Feature Description (continued) The current sense signal is reduced to a scale factor of 1.05 V/A for the PWM comparator signal. The signal is then summed with a 450 mV peak slope compensation ramp. The combined signal provides the PWM comparator with a control signal that reaches 1.5 V when the MOSFET current is 1 A. For duty cycles greater than 50%, current mode control circuits are subject to sub-harmonic oscillation (alternating between short and long PWM pulses every other cycle). Adding a fixed slope voltage ramp signal (slope compensation) to the current sense signal prevents this oscillation. The 450 mV ramp (zero volts when the power MOSFET turns on, and 450 mV at the end of the PWM clock cycle) adds a fixed slope to the current sense ramp to prevent oscillation. To prevent erratic operation at low duty cycle, a leading edge blanking circuit attenuates the current sense signal when the power MOSFET is turned on. When the MOSFET is initially turned on, current spikes from the power MOSFET drain-source and gate-source capacitances flow through the current sense resistor. These transient currents normally cease within 50 ns with proper selection of rectifier diodes and proper PC board layout.

7.3.7 Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the IC in the event the maximum junction temperature is exceeded. When the 165°C junction temperature threshold is reached, the regulator is forced into a low power standby state, disabling all functions except the VCC regulator. Thermal hysteresis allows the IC to cool down before it is re-enabled. Note that since the VCC regulator remains functional during this period, the soft-start circuit shown in Figure 17 should be augmented if soft-start from Thermal Shutdown state is required.

7.3.8 Power MOSFET

The LM5001 switching regulator includes an N-Channel MOSFET with 440-mΩ on-resistance. The on-resistance of the LM5001 MOSFET varies with temperature as shown in the Typical Characteristics graph. The typical total gate charge for the MOSFET is 4.5 nC which is supplied from the VCC pin when the MOSFET is turned on.

8 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

This information is intended to provide guidelines for the power supply designer using the LM5001.

8.1.1 VIN

The voltage applied to the VIN pin can vary within the range of 3.1 V to 75 V. The current into the VIN pin depends primarily on the gate charge of the power MOSFET, the switching frequency, and any external load on the VCC pin. It is recommended the filter shown in Figure 14 be used to suppress transients which may occur at the input supply. This is particularly important when VIN is operated close to the maximum operating rating of the LM5001. When power is applied and the VIN voltage exceeds 2.8 V with the EN pin voltage greater than 0.45 V, the VCC regulator is enabled, supplying current into the external capacitor connected to the VCC pin. When the VIN voltage is between 2.8 V and 6.9 V, the VCC voltage is approximately equal to the VIN voltage. When the voltage on the VCC pin exceeds 6.9 V, the VCC pin voltage is regulated at 6.9 V. In typical flyback applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 6.9 V to shut off the internal start-up regulator. The current requirements from this winding are relatively small, typically less than 20 mA. If the VIN voltage is much higher than the auxiliary voltage, the auxiliary winding significantly improves conversion efficiency. It also reduces the power dissipation within the LM5001. The externally applied VCC voltage should never exceed 14 V. Also the applied VCC should never exceed the VIN voltage to avoid reverse current through the internal VCC to VIN diode shown in the LM5001 block diagram. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM5001 LM5001-Q1

Figure 14. Input Transient Protection

8.1.2 SW Pin

Attention must be given to the PC board layout for the SW pin which connects to the power MOSFET drain. connections, the transformer or inductor terminals, and their respective return paths, should be minimized.

8.1.3 EN / UVLO Voltage Divider Selection

Two dedicated comparators connected to the EN pin are used to detect under-voltage and shutdown conditions. where VPWR is the desired turn-on voltage and IDIVIDER is an arbitrary current through R1 and R2.

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Figure 15. Basic EN (UVLO) Configuration circuitry powered by VCC remains functional. Figure 16. Remote Standby and Disable Control

8.1.4 Soft-Start

Figure 17. The COMP discharge MOSFET conducts during Shutdown and Standby modes to keep the COMP only sink current, the internal COMP pull-up resistor (~5 kΩ) supplies the charging current to the SS capacitor. shutdown, the VCC diode discharges the SS capacitor.

Figure 17. Soft-Start

8.2 Typical Applications

8.2.1 Non-Isolated Flyback

The Non-Isolated Flyback converter (Figure 18) utilizes the internal voltage reference for the regulation setpoint.

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Figure 18. Non-Isolated Flyback

8.2.2 Isolated Flyback

at 1 A and the input voltage ranges from 16 V to 42 V. The switching frequency is set to 250 kHz. Figure 19. Isolated Flyback

8.2.3 Boost

because the power MOSFET cannot interrupt the path between the input and the output.

Figure 20. Boost created by adding a winding on L2 and a diode into the VCC pin. Figure 21. 24-V SEPIC

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Figure 22. 12-V SEPIC

LM5001,LM5001-Q1 SNVS484H –JANUARY 2007–REVISED JULY 2015 www.ti.com

9 Layout

9.1 Layout Guidelines

The LM5001 Current Sense and PWM comparators are very fast and may respond to short duration noise pulses. The components at the SW, COMP, EN and the RT pins should be as physically close as possible to the IC, thereby minimizing noise pickup on the PC board tracks. The SW output pin of the LM5001 should have a short, wide conductor to the power path inductors, transformers and capacitors in order to minimize parasitic inductance that reduces efficiency and increases conducted and radiated noise. Ceramic decoupling capacitors are recommended between the VIN pin to the GND pin and between the VCC pin to the GND pin. Use short, direct connections to avoid clock jitter due to ground voltage differentials. Small package surface mount X7R or X5R capacitors are preferred for high frequency performance and limited variation over temperature and applied voltage. If an application using the LM5001 produces high junction temperatures during normal operation, multiple vias from the GND pin to a PC board ground plane helps conduct heat away from the IC. Judicious positioning of the PC board within the end product, along with use of any available air flow helps reduce the junction temperatures. If using forced air cooling, avoid placing the LM5001 in the airflow shadow of large components, such as input capacitors, inductors or transformers.

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10 Device and Documentation Support

10.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 1. Related Links

10.2 Trademarks

All trademarks are the property of their respective owners.

10.3 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

10.4 Glossary

This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM5001IDQ1 Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5001 IDQ1 LM5001IDQ1.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5001 IDQ1 LM5001IDQ1.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5001 IDQ1 LM5001IDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5001 IDQ1 LM5001IDRQ1.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5001 IDQ1 LM5001IDRQ1.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5001 IDQ1 LM5001MA/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5001 MA LM5001MA/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5001 MA LM5001MA/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5001 MA LM5001MAX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5001 MA LM5001MAX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5001 MA LM5001MAX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5001 MA LM5001SD/NOPB Active Production WSON (NGT) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 LM5001SD/NOPB.A Active Production WSON (NGT) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 LM5001SD/NOPB.B Active Production WSON (NGT) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 LM5001SDE/NOPB Active Production WSON (NGT) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 LM5001SDE/NOPB.A Active Production WSON (NGT) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 LM5001SDE/NOPB.B Active Production WSON (NGT) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 LM5001SDX/NOPB Active Production WSON (NGT) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 LM5001SDX/NOPB.A Active Production WSON (NGT) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 Addendum-Page 1

www.ti.com 23-May-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM5001SDX/NOPB.B Active Production WSON (NGT) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM5001 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM5001, LM5001-Q1 :

• Catalog : LM5001
• Automotive : LM5001-Q1 NOTE: Qualified Version Definitions: Addendum-Page 2

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• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5001IDRQ1 SOIC D 8 2500 367.0 367.0 35.0 LM5001MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5001SD/NOPB WSON NGT 8 1000 208.0 191.0 35.0 LM5001SDE/NOPB WSON NGT 8 250 208.0 191.0 35.0 LM5001SDX/NOPB WSON NGT 8 4500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM5001IDQ1 D SOIC 8 95 495 8 4064 3.05 LM5001IDQ1.A D SOIC 8 95 495 8 4064 3.05 LM5001IDQ1.B D SOIC 8 95 495 8 4064 3.05 LM5001MA/NOPB D SOIC 8 95 495 8 4064 3.05 LM5001MA/NOPB.A D SOIC 8 95 495 8 4064 3.05 LM5001MA/NOPB.B D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 8X 0.35 0.25 3 0.05 2.4 2.6 0.05 6X 0.8

0.8 MAX

0.05 0.00 8X 0.5 0.3 A 4.1 3.9 B 4.1 3.9 (0.2) TYP WSON - 0.8 mm max heightNGT0008A PLASTIC SMALL OUTLINE - NO LEAD 4214935/A 08/2020 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 PIN 1 ID

0.1 C A B

0.05 C THERMAL PAD EXPOSED SYMM SYMM9 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.3) (3) (3.8) 6X (0.8) (2.6) ( 0.2) VIA TYP (1.05) (1.25) 8X (0.6) (R0.05) TYP WSON - 0.8 mm max heightNGT0008A PLASTIC SMALL OUTLINE - NO LEAD 4214935/A 08/2020 SYMM 4 5 LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SYMM 9 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP (1.31) (0.675) 8X (0.3) 8X (0.6) (1.15) (3.8) (0.755) 6X (0.8) WSON - 0.8 mm max heightNGT0008A PLASTIC SMALL OUTLINE - NO LEAD 4214935/A 08/2020 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 4 5 METAL TYP SYMM

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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