LM3248 TI1 | Alldatasheet

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VCC_PA 1.8V Logic FB_ BUCK BOOST BUCK SW_ BUCK PVIN_ BUCK OUT_ BOOST SW_ BOOST SGND_ BOOST BYPASS CONTROL ENABLE BOOST_ GATE MODE PGND PVIN_ BOOST DGND ACB SGND_ BUCK VDD_ BOOST VDD1_ BUCK VCON VDD2_ BUCK 1.5 /c1dH 1.0 /c1dH 10 /c1dF 10 /c1dF 10 /c1dF 1 /c1dF Low ESL VBATT 2.7V to 5.5V FB 1 nF ACB BGND LM3248 www.ti.com SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 LM32482.7MHz,2.5AAdjustableBoost-BuckDC/DCConverter withBoostandActiveCurrentAssistandAnalogBypass(ACB) Check for Samples: LM3248 1FEATURES DESCRIPTION The LM3248 is a PWM/PFM Boost-Buck DC/DC 2• Output Voltage VOUT Adjustable from 0.4V to

  • Boost-Buck and Buck (Boost-Bypass) systems that demand dynamic voltage and current to support converged power amplifier architecturesOperating Modes with Seamless Transition operating in 2G/3G/4G and 3GPP/LTE modes. For• 2.5A Load Current Capability example, the LM3248 is designed to produce higher• High Conversion Efficiency (> 90% typ.) output voltages while maintaining PFM mode as
  • High-Efficiency PFM/PWM Modes with required by some new reduced-power CMOS PAs. The extremely fast Boost-Buck function reduces RFSeamless Transition PA overhead power dissipation, extending battery talk• Very Fast Transient Response: 10 µs time. The device will operate at input voltage VIN
  • ACB Reduces Inductor Size Requirements range of 2.7V to 5.5V and an adjustable output
  • Dither to aid RX Band Noise Compliance voltage VOUT range of 0.4V to 4.0V at a maximum current load of 2.5A. APPLICATIONS The LM3248 is available in a 30-bump, lead-free thin DSBGA package.• Multi-mode 2G/3G/4G and 3GPP/LTE Smart- phones and Tablets
  • Hand-Held Radios
  • RF Mobile Devices Typical Application Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

highest efficiency operation with minimal dropout voltage when the Boost is not needed. Frequency Modulation (PFM) modes for high-efficiency operation with both full and light load conditions. Figure 1. 30-Bump Thin DSBGA Package (0.4 mm pitch)

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www.ti.com SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 Pin Descriptions Pin # Name I/O Description A1 VDD_BOOST - Power supply voltage input for Boost Analog blocks. Connected to VBATT supply. PVIN_BOOST - Power supply voltage input for Boost Bypass FET. A4 Boost converter output. When Boost and Buck are active, OUT_BOOST must be externally connected to PVIN_BUCK. A 10 µF capacitor must be placed between this node and GND.OUT_BOOST O Internally connected to BUCK voltage input and feedback to inverting input of Boost errorA5 amplifier. Digital input. A Low-to-High transition wakes up the boost converter and positions it to a highB1 BOOST_GATE I level in preparation for a possible VCON change. B2 SGND_BOOST - Analog Ground for the Boost Analog blocks. Boost converter switch node. When Boost and Buck are active, SW_BOOST is typicallyB4 SW_BOOST I/O connected to VBATT supply through external power inductor. C1 MODE I Digital input. Low = 3G/4G (PWM/PFM) operation; High = 2G (PWM only) operation. Power supply voltage input for Buck Analog PWM blocks. Internally connected to PVIN_BUCK C2 VDD1_BUCK when used with Boost. If Buck-only mode is used then must be directly connected to VBATT supply. C3 SGND_BUCK - Analog Ground for the Buck Analog Blocks. PGND - Power Ground for output FETs. Input. Chip enable. Setting ENABLE = High biases up the Buck and initiates VCON regulationD1 ENABLE I by the Buck. D2 VCON I Analog voltage control input which controls Buck output voltage. D3 NC - No connect; leave this pin floating. SW_BUCK O Buck converter switch node for external filter inductor connection. E1 ATB1 - Test pin. Connect to SGND or System Ground. Feedback input to inverting input of error amplifier. Connect Buck output voltage directly to thisE2 FB_BUCK - node. E3 DGND - Ground for Boost, Buck, and RFFE digital blocks. E4 Power supply input for Buck PFET and ACB FET. A 10 µF capacitor must be placed betweenPVIN_BUCK - this node and PGND. Must be externally connected to OUT_BOOST.E5 F1 ATB2 - Test pin. Connect to SGND or System Ground. Power supply voltage input for Buck Analog PWM blocks. Internally connected to PVIN_BUCKF2 VDD2_BUCK - when used with Boost. F3 BGND - Ground for ACB bypass circuit. F4 Active Current assist and Bypass output. Connected to the Buck converter output filterACB - capacitor.F5 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM3248

SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) VBATT pins to GND (PVIN_BOOST, VDD_BOOST, SW_BOOST, PVIN_BUCK, VDD1_BUCK, VDD2_BUCK, SW_BUCK, ACB, SGND_BOOST, SGND_BUCK, BGND, PGND) −0.2V to +6.0V BOOST_GATE, MODE, ENABLE, OUT_BOOST, FB_BUCK, VCON (GND −0.2V to PVIN_BOOST +0.2V) Junction Temperature (TJ-MAX) +150°C Storage Temperature Range −65°C to +150°C Continuous Power Dissipation (3) Internally Limited Maximum Lead Temperature (Soldering, 10 sec) +260°C ESD Rating (4) Human Body Model 2 kV (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the potential at the GND pins. The LM3248 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller, and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.5V. (3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ < 130°C (typ.). (4) The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) RECOMMENDED OPERATING CONDITIONS (1) Input Voltage Range VBATT 2.7V to 5.5V Boost Output, Buck Input Range 2.7V to 5.5V Recommended Load Current 0A to 2.5A Junction Temperature (TJ) Range −30°C to +125°C Ambient Temperature (TA) Range −30°C to +90°C (1) All voltages are with respect to the potential at the GND pins. The LM3248 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller, and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.5V. THERMAL PROPERTIES Junction-to-Ambient Thermal Resistance (θJA) (1) 30-bump DSBGA 38°C/W (1) Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7 and is board dependent.

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www.ti.com SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (BOOST) Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA ≤ +90°C). Unless otherwise noted, all specifications apply with VBATT = 3.0V and Buck in IDLE state. Symbol Parameter Condition Min Typ Max Units Open Loop (1), VCON = 1.44V,ILIM-BOOST,PFET PFET valley current limit 4.1 AVOUT_BUCK = 3.6V Boost internal oscillatorFOSC-Boost 2G/3G/4G mode, PWM mode, average 2.7 MHzfrequency (1) Current limit is built-in, fixed, and not adjustable. SYSTEM CHARACTERISTICS (BOOST) The following spec table entries are specified by design and verifications providing the component values in the Typical 1µF (Taiyo Yuden LWK107B7105KA-T) + 10 µF (Murata GRM155R61A106M). These parameters are not verified by production testing.(1) (The Boost stage output voltage equation is given in (2).) Min and Max values are specified over the ambient temperature range TA = −30°C ≤ TA ≤ 90°C. Unless otherwise noted, typical values are specified at VBATT = 3.0V, Buck in IDLE, and TA = 25°C. Symbol Parameter Condition Min Typ Max Units Boost Bypass mode 2.7 5.5 V VCON = 1.60V , MODE = LOW (3G/4G), 4.45VOUT_BOOST Boost output voltage Load = 100 mA (2) VCON = 1.46V , MODE = HIGH (2G), 4.65Load = 100 mA (2) MODE = LOW; BOOST_GATE = HIGH; mV SW_BOOST = switching; –50 0 37 VCON = (VBATT - VGOTOBOOST)/2.5 VGOTOBOOST Boost turn-on threshold voltage MODE = HIGH; BOOST_GATE = HIGH; SW_BOOST = switching; 125 VCON = (VBATT - VGOTOBOOST)/2.5 Minimum time from ENABLE =TENABLE to Initially in Idle State: Boost in 0% duty cycleHIGH (and remains steady) to 25 BOOST_GATE (bypass)BOOST_GATE rising edge µs TBOOST_GATE_Active Minimum time to assert BOOST_GATE signal must remain HIGHBOOST_GATE signal before 45during this intervalnext TTI slot boundary Max input current averaged VBATT = 2.7V, VOUT_BOOST = 4.2VIIN-BOOST-MAX 3.5 Aacross a 2G burst (RMS) PA active during GSM burst (2) Duty CycleMAX- PWM maximum duty cycle IOUT-BOOST < 1 mA 70 % BOOST VBATT = 3.4V to 3.7V, ΔV = ±300 mV, VLINE-TR Line transient response TR =TF = 10 µs, VOUT_BUCK = 3.7V, 150 RLOAD_BUCK = 4Ω, MODE = 3G/4G (2) mVppVBATT = 2.7V, IOUT_BUCK = 10 mA to 850 mA,VLOAD-TR Load transient response 600IOUT, TR = TF = 10 µs VOUT_BUCK = 3.7V, MODE = 3G/4G (2) VBATT = 2.7V, VBOOST = 3.4V, IOUT = 2A,Boost ripple voltage at worst-VBOOST-RIPPLE 2G mode (Sufficient overhead between 100 mVppcase conditions VBOOST and VOUT ) (1) Parameter is specified by design, characterization testing, or statistical analysis. Typical numbers are not verified by production testing, but do represent the most likely norm. (2) VOUT-BOOST = VCON * 2.5 + [≈ 450 mV(3G/4G) or ≈ 950 mV(2G)]. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM3248

SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (BUCK) Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA ≤ +90°C). Unless otherwise noted, all specifications apply with VBATT = 3.8V. Symbol Parameter Condition Min Typ Max Units VFB,MIN Feedback voltage at low setting VCON = 0.16V, MODE = HIGH (1) (2) 0.35 0.4 0.45 ILIM,PFET,Steady Positive steady state peak current VOUT = 1.5V (3) 1.34 1.45 1.65 State limit NFET Switch negative peakILIM,NFET VCON = 1.0V (3) −1.50 −1.31current limit ISHDN Shutdown supply current IBATT ENABLE = LOW (4) 0.02 4 IQ_PFM ENABLE = HIGH 260 350 µA DC bias current from VBATT IQ_PWM ENABLE = HIGH 1010 1100 FOSC Internal oscillator frequency 2G/3G/4G mode, PWM mode, average 2.484 2.7 2.916 MHz (1) The parameters in the electrical characteristics table are tested under open loop conditions at VBATT = 3.8V unless otherwise specified. For performance over the input voltage range and closed-loop results, refer to the datasheet curves. (2) VOUT-BOOST = VCON * 2.5 + [≈ 450 mV(3G/4G) or ≈ 950 mV(2G)]. (3) Current limit is built-in, fixed, and not adjustable. (4) Shutdown current includes leakage current of PFET.

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www.ti.com SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 SYSTEM CHARACTERISTICS (BUCK) The following spec table entries are specified by design and verification providing the component values in the Typical 10 µF + 4.7 µF (Murata GRM155R61A106A, GRM155R61A475MEAA) + 4 x 1.0 µF (Murata GRM033R60J105M). These parameters are not verified by production testing.(1) Min and Max values are specified over the ambient temperature range TA = −30°C ≤ TA ≤ +90°C. Typical values are specified at VBATT = 3.8V and TA = 25°C unless otherwise stated. Symbol Parameter Condition Min Typ Max Units Time Delay required after TWarm-Up BOOST_GATE = HIGH (before ENABLE = High 30 µs VCON can change) Time for VOUT to rise from 0V to VBATT = 3.8V, RLOAD = 68Ω, 3.4V (90% or 3.06V) VCON = 0V to 1.36V Time for VOUT to fall from 3.4V to VBATT = 3.8V, RLOAD = 68Ω, 0V (10% or 0.34V) VCON = 1.36V to 0V Time for VOUT to rise from 0.8V to VBATT = 3.8V, RLOAD = 20Ω, 3.3V (90% or 3.05V) VCON = 0.32V to 1.32V Time for VOUT to fall from 3.3V to VBATT = 3.8V, RLOAD = 20Ω, 0.8V (10% or 1.05V) VCON = 1.32 to 0.32V Time for VOUT to rise from 1.4V to VBATT = 3.8V, RLOAD = 6.8Ω,TRESPONSE µs 3.4V (90% or 3.2V) VCON = 0.56V to 1.36V Time for VOUT to fall from 3.4V to VBATT = 3.8V, RLOAD = 6.8Ω, 1.4V (10% or 1.6V) VCON = 1.36V to 0.56V Positive transient peak currentILIM,PFET,Transient VOUT = 1.5V (2) 1.9 2.1 Alimit VBATT ≥ 2.88V, VCON = 1.48V (VOUT = 3.7V), PWM mode, switcher plus ACB 2.0 current Maximum load current in PWMIOUT_MAX, PWM VBATT ≥ 3.0V, VCON = 1.48V (VOUT = 3.7V), Amode 2.3PWM mode, switcher plus ACB current VCON = 1.2V (VOUT = 3.0V), PWM mode, 2.5switcher plus ACB current Maximum load current to enterIOUT_MAX, PFM D < 0.85 or SW_BOOST = switching 85 mAinto PFM mode Maximum output transient pullupIOUT,PU 3.0current limit PWM mode (2), switcher plus ACB current A PWM maximum output transientIOUT,PD_PWM −3.0pulldown current limit VOUT accuracy over output voltageVOUT_ACC VOUT = 0.6V to 3.6V (3) −3 +3 %range (1) Parameter is specified by design, characterization testing, or statistical analysis. Typical numbers are not verified by production testing, but do represent the most likely norm. (2) Current limit is built-in, fixed, and not adjustable. (3) Accuracy limits are ±3% or ±50 mV, whichever is larger. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM3248

SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 www.ti.com SYSTEM CHARACTERISTICS (BUCK) (continued) The following spec table entries are specified by design and verification providing the component values in the Typical 10 µF + 4.7 µF (Murata GRM155R61A106A, GRM155R61A475MEAA) + 4 x 1.0 µF (Murata GRM033R60J105M). These parameters are not verified by production testing.(1) Min and Max values are specified over the ambient temperature range TA = −30°C ≤ TA ≤ +90°C. Typical values are specified at VBATT = 3.8V and TA = 25°C unless otherwise stated. Symbol Parameter Condition Min Typ Max Units Ripple voltage at no pulse VOUT = 0.4V to 3.6V, ROUT = 2.2Ω, 4 10skipping condition 2G mode (4) VBATT = 4.2V to dropout,Ripple voltage at pulse skippingVOUT_RIPPLE VOUT = 3.6V, ROUT = 2.2Ω, 14 20 mVppcondition 2G mode (4) VOUT = 1.0V,PFM ripple voltage 9 15IOUT = 40 mA (4) VBATT = 3.6V to 4.2V, VLINE-TR Line transient response TR = TF = 10 µs, 70 VOUT = 1.0V, IOUT = 600 mA mVpk VOUT = 3.0V, VLOAD-TR Load transient response TR = TF = 10 µs, IOUT = 0A to 1.2A, 150 2G mode VBATT = 3.2V, VOUT = 1.0V,FSW_PFM Minimum PFM frequency 100 kHzIOUT = 10 mA (4) Ripple voltage should be measured at COUT node on a well-designed PC board, using suggested inductor and capacitors. Ripple voltage is defined as the maximum peak-to-peak output voltage variation measured over a 100 µs period. SYSTEM CHARACTERISTICS (BOOST-BUCK) See SYSTEM CHARACTERISTICS (BOOST) and SYSTEM CHARACTERISTICS (BUCK) for test conditions. Symbol Parameter Condition Min Typ Max Units VBATT = 4.0V, VOUT = 3.4V, 86IOUT = 2A (2G, PWM mode) VBATT = 4.0V, VOUT = 2.5V, 89IOUT = 800 mA (2G, PWM mode) VBATT = 4.0V, VOUT = 3.0V, 93IOUT = 400 mA (2G, PWM mode) VBATT = 3.4V, VOUT = 4.0V, 90IOUT = 850 mA (3G/4G, PWM mode) VBATT = 3.4V, VOUT = 3.0V,η Boost-Buck Efficiency 94 %IOUT = 500 mA (3G/4G, PWM mode) VBATT = 3.4V, VOUT = 2.5V, 90IOUT = 70 mA (3G/4G, PFM mode) VBATT = 3.4V, VOUT = 0.9V, 86IOUT = 200 mA (3G/4G, PWM mode) VBATT = 3.6V, VOUT = 3.3V, 92IOUT = 20 mA (3G/4G PFM mode) VBATT = 3.4V, VOUT = 0.6V, 78IOUT = 20 mA (3G/4G, PFM mode) TRESPONSE 15 µs

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before BOOST_GATE is brought HIGH. VOUT settles to within 90% of final value. BOOST_GATE must transition HIGH min. before the start of the next Tx slot. (−30°C ≤ TA ≤ +90°C). Unless otherwise noted, all specifications apply with VBATT = 2.7V to 5.5V. Figure 2. Startup + Optional Boost Timing Sequence

For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8.

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For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20.

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addition, supports higher power 2G functionality. Figure 27. Typical Application: Boost-Buck input battery voltage. The Boost converter can be operated in either Boost or Boost-Bypass (Buck Only) modes. BOOST_GATE transitions from LOW to HIGH (see Figure 2). reduces unnecessary battery drain caused by boost bias circuits and improves efficiency.

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Boost-Bypass conditions are not met. This functionality is described below. the new (possibly higher) Buck output level is updated, ensuring a smooth transition between levels. Figure 28. Boost Operation showing VCON-VBATT Relationship mode of operation is valid for 2.7V < VBATT < 5.5V.

SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 www.ti.com Buck Converter The Buck converter output voltage, VCC_PA, is directly proportional to the VCON control voltage, which level is determined by the applications processor, BBIC or RFIC RF output Power Amplifier control algorithm. The user can dynamically program the Buck output voltage from 0.4V to 4.0V (typ.) by adjusting the VCON voltage setting, per the equation: VCC_PA = VCON * 2.5. The LM3248 has been designed to make rapid, smooth VCC_PA output transitions required by fast 3G/4G and 2G burst ramp profiles. The current consumption of RF Power Amplifier modules (RF PAs) typically increases with supply voltage. Accordingly, DC/DC converter output power requirements increase as the RF PA module VCC_PA voltages increase. Two operating methods, Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM), are used to optimize system efficiency over a range of PA power levels. When the LM3248 is not needed, the device can be set to shutdown mode (ENABLE = LOW) to minimize battery current drain. Current overload protection and thermal overload shutdown are also provided. 2G vs. 3G/4G Modes The MODE pin enables selection of either constant PWM (2G) or automatic PWM/PFM (3G/4G) operation. To maintain higher efficiency at light loads, the 3G/4G mode setting is used. When in Boost-Bypass, and average inductor current drops below 45 to 90 mA (typ.), PFM operation is active. The switching frequency is reduced to improve efficiency. Conversely, the LM3248 transitions back to PWM operation from PFM when the average inductor current increases to values above 90 to 160 mA (typ.). Automatic transition into PWM operation also occurs if the output voltage falls more than 25 mV due to a load current increase. Active Current and Analog Bypass (ACB) Fast transient 2G power bursts require high current levels to be sourced or sunk from the LM3248 Buck DC/DC converter. The Active Current assist and analog Bypass (ACB) feature, built into the Buck DC/DC converter, enables smooth waveform transitions with load currents as high as 2.5A using smaller footprint inductors and meets all of the transient requirements when supplying VCC_PA voltages for the latest multi-mode RF Power Amplifier modules. The ACB circuit provides an additional current path when the load current exceeds 1.4A (typ.) or as the switcher approaches dropout. Similarly, the ACB circuit enables the LM3248 to respond with faster output voltage transition times by providing extra output current on rising and falling output edges. The LM3248 handles bypass events by sensing input voltage, output voltage, and load current conditions, and then automatically and seamlessly transitioning the converter into analog bypass, while maintaining output voltage regulation and low output voltage ripple. Full bypass (100% duty cycle) will occur if the total dropout resistance in bypass mode (≈ 50 mΩ) is insufficient to regulate the output voltage. Shutdown When the LM3248 ENABLE = LOW, the Buck and Boost DC/DC converters and control circuits are programmed into an OFF (Shutdown) state and the output power switches are placed in a tri-state condition. The Shutdown state reduces system current consumption to less than 4 µA. Output Current Protection The Buck DC/DC converter and the ACB circuit each have output current protection. The Buck converter includes a steady-state current limit which monitors load currents and enables the ACB circuit. During transient over-current conditions the peak current limit detector turns off the PFET switch within the current PWM cycle and initiates the timed output current limit. Timed Output Current Limit If the output load current rises above the ILIM,PFET,Transient threshold continuously for more than 11 μs, and the output voltage falls below 0.3V (typ.), the LM3248 Buck DC/DC converter switch node (SW_BUCK pin) is put into a high-impedance state, and the ACB circuit is disabled. The power switch then remains disabled for a period of 35 µs to force the inductor current to ramp down. If the short circuit condition continues, the cycle will repeat.

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t7.25mm t 3225 0816C2 0603 2016 1005 FB11005 Boost + Buck LM3248 IC 2.5 mm x 2.8 mm 1005 1005 t4.25mmt LM3248 www.ti.com SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 Thermal Overload Protection The LM3248 IC has thermal overload protection that disables the device, protecting it from short-term misuse and overload conditions. If the junction temperature exceeds 150°C (typ.), all of the power functions will be turned off. Normal operation resumes after the temperature drops below 130°C (typ.), and the LM3248 will attempt to return to the operating state before the over-temperature condition occurred. Prolonged operation in thermal overload condition may damage the device and is therefore not recommended. Digital Control Signals The BOOST_GATE, MODE and ENABLE pins are 1.8V logic-level inputs for controlling the LM3248. A logic LOW level applied to the ENABLE pin puts the LM3248 into a Shutdown state, where minimum current is drawn from the battery. The MODE pin allows the user to select whether PWM (2G) or PWM/PFM (3G/4G) operation is allowed. The BOOST_GATE pin enables the Boost DC/DC converter circuitry and related functionality. Manufacturing Considerations Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow techniques, as detailed in Texas Instruments Application Note AN-1112 (SNVA009). Please refer to the section Surface Mount Assembly Considerations. For best results in assembly, local alignment fiducial markers on the PC board should be used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that would otherwise form if the solder- mask and pad overlap, which would hold the device off the surface of the board and interfere with mounting. See The 30-bump(5x6) DSBGA package used for the LM3248 has the following Non-Solder Mask Defined (NSMD) mounting specifications:

  • Solder ball diameter: 0.265 mm
  • Copper pad size: 0.225 mm ± 0.02 mm
  • Solder mask opening: 0.325 ± 0.02 mm The trace to each pad should enter the pad with a 90°entry angle to prevent debris from being caught in deep corners. Symmetry is important to ensure the solder bumps re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1-A5, C4, C5, E4, E5, F4 and F5 since PVIN_BOOST, OUT_BOOST, PGND, PVIN_BUCK and ACB may be connected to large copper planes and inadequate thermal reliefs can result in inadequate re-flow of these bumps. Typical Solution Size Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LM3248

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APPLICATION INFORMATION

Recommended External Components Inductor Selection The LM3248 was designed to work with 1.0 µH and 1.5 µH buck inductors. The largest current magnitudes encountered with the LM3248 are in 2G mode (that is, 2.5A for 2G vs. <1A for 3G/4G). Because of the low duty cycles encountered with 2G transmission bursts, the maximum RMS current encountered is much less than the peak. Suitable inductors are typically rated for maximum current with two different numbers: 1. ΔL/L = 30% (or similar) which means the current level that causes a 30% drop in the inductance value (due to core saturation), and 2. ΔT = 40°C (or similar) which means the current level that causes a 40°C rise in the inductor's temperature. Because of the “peaky” nature of 2G current waveforms (low duty cycle, high peak-to-average ratio), the “ΔL/L=30%”(or similar) current limit will typically be reached long before the “ΔT=40°C”(or similar) current value. This means that selection of the inductor is saturation-limited. Another way of saying this is that the inductor core saturation is proportional to the peak current value, while the temperature rise is due to the RMS current value. As a result, candidate inductors which may appear too small for the application when looking at the “ΔT=40°C” (or similar) current specification, may be sufficiently sized, as long as the “ΔL/L = 30%”(or similar) current value is less than the peak current required for the application. If the “ΔL/L = 30%” (or similar) current value is not specified, or it is not clear whether the max current rating for the part refers to either one of these rules of measure, this information should be requested from the supplier. The LM3248 automatically manages the inductor peak and RMS current (or steady-state current peak) through the SW_BUCK pin. The SW_BUCK pin has two positive current limits. The first is the 1.45A typical (or 1.65A maximum) overcurrent protection which sets the upper steady-state inductor peak current (as detailed in the ELECTRICAL CHARACTERISTICS (BUCK) parameter "ILIM,PFET,SteadyState"). It is the dominant factor limiting currents from surpassing the buck inductor ISAT specification. The second is an over-limit current protection "ILIM,PFET,Transient" found in the SYSTEM CHARACTERISTICS (BUCK) table. It limits the maximum peak inductor output inductor, the user should insure that a minimum of 0.3 µH is maintained when peak currents reach the ILIM,PFET,Transient current limit. The ACB circuit automatically adjusts its output current to keep the steady-state inductor current below the ILIM,PFET,Steady State current limit. The inductor RMS current will always be less than this value during the transmit burst, thus keeping the inductor within its thermal operating limits. For good efficiency, the inductor's resistance should be less than 0.15Ω. Low DCR inductors (< 0.15Ω) are recommended. Table 1 suggests some inductors and their suppliers. The slightly larger inductors listed in Table 1 were observed to enhance efficiency 1 to 2% under some VIN/VOUT/Load conditions. Table 1. Suggested Inductors and Their Suppliers

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Table 2. Suggested Capacitors and Their Suppliers

SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 www.ti.com PCB LAYOUT CONSIDERATIONS Overview PC board layout is critical to successfully designing a DC-DC converter into a product. A properly planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final product yield. PCB Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or degraded performance of the converter. Energy Efficiency Minimize resistive losses by using wide traces between the power components and doubling up traces on multiple layers when possible. EMI By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3248, switches Ampere-level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is maintained within tolerable levels. To help minimize radiated noise:

  • Place the LM3248 DC-DC converter, its input capacitor, and output filter inductor and capacitor close together, and make the interconnecting traces as short as possible.
  • Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3248 and the inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3248 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half- cycles and reduces radiated noise.
  • Make the current loop area(s) as small as possible. Interleave doubled traces with ground planes or return paths, where possible, to further minimize trace inductances. To help minimize conducted noise in the ground-plane:
  • Reduce the amount of switching current that circulates through the ground plane by connecting the ground bumps of the LM3248 and the boost output/buck input filter capacitors together using generous component- side copper fill as a pseudo-ground plane. Then connect this copper fill to the system ground-plane by multiple vias. The multiple vias help to minimize ground bounce at the LM3248 by giving it a low-impedance ground connection. To help minimize coupling to the DC-DC converter's own voltage feedback trace:
  • Route noise sensitive traces, such as the voltage feedback path (FB_BUCK), as directly as possible from the switcher FB_BUCK pad to the VOUT pad of the output capacitor, but keep them away from noisy traces between the power components.

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Product Folder Links: LM3248

  • Use a star connection to route from the VBATT power source to the LM3248 PVIN_BOOST pins and to the PA device VBATT pins.
  • Include sufficient decoupling capacitance, for both low and high frequency, at the PA VBATT connections.
  • Route traces for minimum inductance (short, wide connections) between supply pins and bypass capacitor(s).
  • Route traces to minimize inductance between bypass capacitors and the ground plane.
  • Utilize necessary power supply trace inductance(s) to reduce coupling between function blocks.
  • Inserting a ferrite bead in series with the VBATT power supply trace may offer a favorable tradeoff between board area and additional shunt bypass capacitors, by attenuating noise that might otherwise propagate through the supply connections. 4. LM3248 RF Evaluation Board

Figure 29. Simplified LM3248 RF Evaluation Board Schematic

  1. Input Capacitor C2 should be placed closer to LM3248 than C1.
  2. Optional to add a 1 nF (C34) capacitor on the input of LM3248 for high frequency filtering.
  3. Bulk Output Capacitor C7 should be placed closer to LM3248 than C8.
  4. Connect GND terminals of C7, C8 and C34 directly to System RF GND layer of phone board.
  5. Connect GND terminals of boost output C27 and buck input C28 capacitors to copper PGND island on the

component side. This island is then tied to the system ground layer through several vias.

  1. Connect bumps SGND_BOOST(B2), SGND_BUCK(C3), DGND(E3), and BGND (F3) directly to system
  2. Small high-frequency filtering capacitors (e.g., C34) work better when they are connected to system ground

size for minimum footprint and best high frequency characteristics.

Figure 30. Top View of RF Evaluation Board Amplifier. These circuits are outlined in Figure 30.

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Figure 32. LM3248 Decoupling Cap Placement common mode switching currents that appear on these surfaces. junction of output inductor L3 and output capacitor C7 (see Figure 32). shielding. Connect output capacitors C7 and C8 directly to the system ground (not to the PGND copper island). Figure 33), which is acceptable, since they do not carry extremely fast (high di/dt) switching currents.

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SNVSA01A – JULY 2013– REVISED SEPTEMBER 2013 www.ti.com

REVISION HISTORY

Changes from Original (August 2013) to Revision A Page

  • Changed Product Brief for Full Datasheet; 2 figures: Boost/Buck Output Voltage Timing Diagram and Boost

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Product Folder Links: LM3248

www.ti.com 10-Oct-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM3248TME/NOPB ACTIVE DSBGA YFQ 30 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 90 3248 LM3248TMX/NOPB ACTIVE DSBGA YFQ 30 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 90 3248 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3248TME/NOPB DSBGA YFQ 30 250 210.0 185.0 35.0 LM3248TMX/NOPB DSBGA YFQ 30 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 Pack Materials-Page 2

www.ti.com TMD30XXX (Rev B) A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. NOTES: 4215085/A 12/12 D 0.600 ±0.075 E D: Max = E: Max = 2.829 mm, Min = 2.453 mm, Min = 2.769 mm 2.393 mm

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