LM3000

LM3000 NSC | Alldatasheet

Document overview

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Technical content

Features

■ VIN range from 3.3V to 18.5V ■ Output voltage from 0.6V to 80% of VIN ■ Remote differential output voltage sensing ■ 1% accuracy at FB pin ■ Interleaved operation reduces input capacitors ■ Frequency sync/adjust from 200 kHz to 1.5 MHz ■ Startup with pre-bias load ■ Independent power good, enable, soft-start and track ■ Programmable current limit without external sense resistor ■ Hiccup mode short circuit protection

Applications

■ DC Power Distribution Systems ■ Graphic Cards - GPU and Memory ICs ■ FPGA, CPLD, and ASICs ■ Embedded Processor ■ 1.8V and 2.5V I/O Supplies ■ Networking Equipment (Routers, Hubs) Simplified Application 300905a1 © 2009 National Semiconductor Corporation 300905 www.national.com LM3000 Dual Synchronous Emulated Current-Mode Controller

Ordering Information

Order Number Package Marking Package Type NSC Package Drawing Supplied As LM3000ASQ 3000A 32-Lead LLP SQA32A 1000 Units Tape and Reel LM3000ASQX 3000A 32-Lead LLP SQA32A 4500 Units Tape and Reel LM3000SQ 3000 32-Lead LLP SQA32A 1000 Units Tape and Reel LM3000SQX 3000 32-Lead LLP SQA32A 4500 Units Tape and Reel www.national.com 2 LM3000

Pin # Name Description 1 VSW2 Switch node sense for channel 2. 2 PGND2 Power ground for channel 2 low-side drivers.* 3 LG2 Channel 2 low-side gate drive for external MOSFET. 4 VIN Chip supply voltage, input to the VDD and VDR regulators. (3.3V to 18.5V) 5 VDR Supply for low-side gate drivers. 6 LG1 Channel 1 low-side gate drive for external MOSFET. 7 PGND1 Power ground for channel 1 low-side drivers.* 8 VSW1 Switch node sense for channel 1. 9 ILIM1 Current limit setting input for channel 1. 10 HG1 Channel 1 high-side gate drive for external MOSFET. 11 VCB1 Boost voltage for channel 1 high-side driver. 12 VDD Supply for control circuitry. 13 EA1_GND Error amplifier ground sense for channel 1.* 14 FB1 Error amplifier input for channel 1. 15 COMP1 Error amplifier output for channel 1. 16 PGOOD1 Power good signal for channel 1 under-voltage and over-voltage. 17 FREQ/SYNC Frequency set / synchronization input for internal PLL. 18 EN1 Channel 1 enable input. Used to set the emulated current slope for channel 1. 19 TRK1 Channel 1 track input. 20 SS1 Channel 1 soft-start. 21 TRK2 Channel 2 track input. 22 SS2 Channel 2 soft-start. 23 EN2 Channel 2 enable input. Used to set the emulated current slope for channel 2. 24 PGOOD2 Power good signal for channel 2 under-voltage and over-voltage. 25 COMP2 Error amplifier output for channel 2. 26 FB2 Error amplifier input for channel 2. 27 EA2_GND Error amplifier ground sense for channel 2.* 28 CLKOUT Output clock. CLKOUT is shifted 90 degrees from SYNC input. 29 SGND Local signal ground.* 30 VCB2 Boost voltage for channel 2 high-side driver. 31 HG2 Channel 2 high-side gate drive for external MOSFET. 32 ILIM2 Current limit setting input for channel 2. DAP Exposed die attach pad. Connect the DAP directly to SGND.* *The LM3000 offers true remote ground sensing to achieve very tight line and load regulation. For best layout practice, the EA1_GND, and EA2_GND should be tied to the ground end of the output capacitor (or output terminal) for VOUT1 and VOUT2 respectively. Inside the LM3000, the two power ground nodes PGND1 and PGND2 are physically isolated from each other and also isolated from the internal signal ground SGND. In order to achieve the best cross-channel noise rejection, it is advised to keep these three grounds isolated from each other for the most part in the board layout and only tie them together at the ground terminals. 3 www.national.com LM3000

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN to SGND, PGND -0.3V to 20V VSW1, VSW2 to SGND, PGND -3V to 20V VDD, VDR to SGND, PGND (Note 3) -0.3V to 5.5V VCB1, VCB2 to SGND ,PGND 24V VCB1 to VSW1, VCB2 to VSW2 5.5V FB1, FB2 to SGND, PGND -0.3V to 3.0V All other input pins to SGND, PGND (Note 4) -0.3V to 5.5V Junction Temperature (TJ-MAX) 150°C Storage Temperature Range -65°C to +150°C Maximum Lead Temperature Soldering, 5 seconds 260°C ESD Rating HBM (Note 2) 2000V Operating Ratings (Note 1) Input Voltage Range VDD = VDR = VIN (Note 3) 3.3V to 5.5V VIN 3.3V to 18.5V Junction Temperature (TJ) Range −40°C to +125°C Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise noted, VIN = 12.0V, IEN1 = IEN2 = 40 µA. Symbol Parameter Condition Min Typ Max Units VFB FB Pin Voltage FB1, FB2 (LM3000A) -20°C to +85°C 0.594 0.6 0.606 V 0.591 0.6 0.609 VFB FB Pin Voltage FB1, FB2 (LM3000) -20°C to +85°C 0.591 0.6 0.609 V 0.588 0.6 0.612 ΔVFB/VFB Line Regulation VDD = VIN = VDR 3.3V < VIN < 5.5, COMP = 1.5V 0.15 % Line Regulation VIN > 6V 6V < VIN < 18.5V, COMP = 1.5V 0.3 % Load Regulation VIN = 12.0V, 1.0V < COMP < 1.4V 0.1 % Iq VIN Operating Current 5 mA ISD VIN Shutdown Current IEN1 , IEN2 < 5 µA 50 µA IEN EN Input Threshold Current IEN Rising 15 35 µA Hysteresis 10 ILIM Source Current ILIM1, ILIM2 VILIM1, VILIM2 = 0V 17 20 23 µA ISS Soft-Start Pull-Up Current VSS = 0.5V 5.5 8.5 11.5 µA VHICCUP COMP Pin Hiccup Thresholds COMP Threshold High 2.85 V Hysteresis 50 mV tDELAY Hiccup Delay 16 Cycles tCOOL Cool-Down Time Until Restart 4096 Cycles VOVP Over-Voltage Protection Threshold As a % of Nominal Output Voltage 110 115 120 % Hysteresis 3 VUVP Under-Voltage Protection Threshold As a % of REF1, REF2 (see Block Diagram) 85 % GATE DRIVE ICB VCB Pin Leakage Current VCB - VSW = 5.5V 250 nA RDS1 Top FET Drive Pull-Up On-Resistance VCB - VSW = 4.5V, VCB - HG = 100 mV 3 Ω RDS2 Top FET Drive Pull-Down On-Resistance VCB - VSW = 4.5V, HG - VSW = 100 mV 2 Ω RDS3 Bottom FET Drive Pull-Up On- Resistance VDR - PGND = 5V, VDR - LG = 100 mV 2 Ω RDS4 Bottom FET Drive Pull-Down On- Resistance VDR - PGND = 5V, LG - PGND = 100 mV 1 Ω www.national.com 4 LM3000

Symbol Parameter Condition Min Typ Max Units OSCILLATOR fSW Switching Frequency RFRQ = 100 kΩ 230 kHz RFRQ = 42.2 kΩ 425 500 575 kHz RFRQ = 10 kΩ 1550 kHz VSYNC Threshold for Synchronization at the FREQ/SYNC Pin Rising 2.2 V Falling 0.6 fSYNC SYNC Range 200 1500 kHz tSYNC SYNC Pulse Width 100 ns tSYNC-TRS SYNC Rise/Fall Time 10 ns DMAX Maximum Duty cycle 85 % ERROR AMPLIFIER IFB FB Pin Bias Current FB = 0.6V 20 nA ISOURCE COMP Pin Source Current FB = 0.5V, COMP = 1.0V 80 µA ISINK COMP Pin Sink Current FB = 0.7V, COMP = 0.7V 80 µA VCOMP-HI COMP Pin Voltage High Clamp 2.80 3.0 3.2 V VCOMP-LO COMP Pin Voltage Low Clamp 0.48 V VOS-TRK Offset Using TRK Pin TRK = 0.45V -9.0 0 9.0 mV gm Transconductance 1400 µS fBW Unity Gain Bandwidth Frequency 10 MHz INTERNAL VOLTAGE REGULATOR VVDD Internal Core Regulator Voltage No External Load 5.15 V VVDD-ON UVLO Thresholds VDD Rising 2.12 V Hysteresis 0.14 VVDD-DO Internal Core Regulator Dropout Voltage No External Load 1.1 V IVDD-ILIM Internal Core Regulator Current Limit VDD Short to Ground 80 mA VVDR Regulator for External MOSFET Drivers IVDR = 100 mA 5.2 V VVDR-DO Driver Regulator Dropout Voltage IVDR = 100 mA 1.0 V IVDR-ILIM Driver Regulator Current Limit VDR Short to Ground 450 mA PGOOD OUTPUT RPG-ON PGOOD On-Resistance FB1 = FB2 = 0.47V 250 Ω IOH PGOOD High Leakage Current VPGOOD = 5V 100 nA THERMAL RESISTANCE θJA Junction-to-Ambient Thermal Resistance Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. For guaranteed specifications and conditions, see the Electrical Characteristics table. Note 2: Human Body Model (HBM) is 100 pF capacitor discharged through a 1.5k resistor into each pin. Applicable standard is JESD22-A114C. Note 3: VDD and VDR are outputs of the internal linear regulator. Under normal operating conditions where VIN > 5.5V, they must not be tied to any external voltage source. In an application where VIN is between 3.3V to 5.5V, it is recommended to tie the VDD, VDR and VIN pins together, especially when VIN may drop below 4.5V. In order to have better noise rejection under these conditions, a 10Ω, 1μF input filter may be used for the VDD pin. Note 4: HG1, HG2, LG1, LG2 and CLKOUT are all output pins and should not be tied to any external power supply. COMP1 and COMP2 are also outputs and should not be tied to any lower output impedance power source. PGOOD1 and PGOOD2 are open drain outputs, with a pull-down resistance of about 250Ω. Each of them may be tied to an external voltage source less than 5.5V through an external resister greater than 3kΩ, although 10kΩ and above are preferred to reduce the necessary signal ground current. Note 5: Tested on a four layer JEDEC board. Four vias provided under the exposed pad. See JEDEC standards JESD51-5 and JESD51-7. 5 www.national.com LM3000

Typical Performance Characteristics 3.3V Output Efficiency at 500 kHz 30090517 1.2V Output Efficiency at 500 kHz 30090519 3.3V Output Load and Line Regulation 30090518 1.2V Output Load and Line Regulation 30090520 FB1, FB2 Reference vs Temperature 30090503 VDD Voltage vs Temperature 30090505 www.national.com 6 LM3000

Pulse Skipping during Over-Current Condition 30090510 No Load Soft-Start with Pre-Bias 30090511 Output Short Circuit Hiccup 30090512 Soft-Start with Load 30090513 Switch Node Short Circuit Hiccup 30090514 7 www.national.com LM3000

External Clock Synchronization 30090515 External Tracking 30090516 Error Amplifier Transconductance vs Temperature 30090507 Enable Current Threshold vs Temperature 30090508 Switching Frequency vs Temperature 30090504 RFRQ vs Switching Frequency 30090506 www.national.com 8 LM3000

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FIGURE 9. Bootstrap Circuit proximately 3V, with 30 mV of hysteresis. below the rising trip point. current limit cycles occur, the part enters hiccup mode. two consecutive high-side current limit fault events. monitor the output status of the two channels independently. typical value of 100 kΩ is used to minimize loading on VDD. sation for the complete design method.

Application Information

The most common circuit controlled by the LM3000 is a non- isolated, synchronous buck regulator. The buck regulator steps down the input voltage and has a duty ratio D of: Where η is the estimated converter efficiency. The following is a design example selecting components for the Typical Application Schematic of Figure 24. The circuit is designed for two outputs of 3.3V at 8A and 1.2V at 15A from an input voltage of 6V to 18V. This circuit is typical of a ‘brick’ module and has a height requirement of 6.5mm or less. Other assumptions used to aid in circuit design are that the expected load is a small microprocessor or ASIC with fast load tran- sients, and that the type of MOSFETs used are in SO-8 or its equivalent packages such as PowerPAK ®, PQFN and LFPAK (LFPAK-i). SWITCHING FREQUENCY The selection of switching frequency is based on the tradeoff between size, cost and efficiency. In general, a lower fre- quency means larger, more expensive inductors and capac- itors. A higher switching frequency generally results in a smaller but less efficient solution, because the power MOS- FET gate capacitances must be charged and discharged more often in a given amount of time. For this application a frequency of 500 kHz is selected. 500 kHz is a good compro- mise between the size of the inductor and MOSFETs, tran- sient response and efficiency. Following the equation given for RFRQ in the Frequency Setting section, for 500 kHz oper- ation a 42.2 kΩ 1% resistor is used. MOSFETS Selection of the power MOSFETs is governed by a tradeoff between size, cost and efficiency. Buck regulators that use a controller IC and discrete MOSFETs tend to be most efficient for output currents of 4A to 20A. Losses in the high-side FET can be broken down into con- duction loss, gate charge loss and switching loss. Conduc- tion, or I2R loss is approximately: PCOND_HI = D x (IOUT2 x RDS(on)_HI x 1.3) (High-side FET) PCOND_LO = D x (IOUT2 x RDS(on)_LO x 1.3) (Low-side FET) In the above equations the factor 1.3 accounts for the in- crease in MOSFET RDS(on) due to self heating. Alternatively, the 1.3 can be ignored and the R DS(on) of the MOSFET esti- mated using the RDS(on) vs. Temperature curves in the MOS- FET datasheets. The gate charge loss results from the current driving the gate capacitance of the power MOSFETs, and is approximated as: PDR = VIN x (QG_HI + QG_LO) x fSW Where QG_HI and QG_LO are the total gate charge of the high- side and low-side FETs respectively at the typical 5V driver voltage. Gate charge loss differs from conduction and switch- ing losses in that the majority of dissipation occurs in the LM3000. The switching loss occurs during the brief transition period as the FET turns on and off, during which both current and volt- age are present in the channel of the FET. This can be approximated as the following: Where Q GD is the high-side FET Miller charge with a V DS swing between 0 to V IN; CISS is the input capacitance of the high-side MOSFET in its off state with VDS = VIN. α and β are fitting coefficient numbers, which are usually between 0.5 to 1, depending on the board level parasitic inductances and re- verse recovery of the low-side power MOSFET body diode. Under ideal condition, setting α = β = 0.5 is a good starting point. Other variables are defined as: IL_VL = IOUT - 0.5 x ΔIL IL_PK = IOUT + 0.5 x ΔIL RG_ON = 8.5 + RG_INT + RG_EXT RG_OFF = 2.8 + RG_INT + RG_EXT Switching loss is calculated for the high-side FET only. 8.5 and 2.8 represent the LM3000 high-side driver resistance in the transient region. RG_INT is the gate resistance of the high- side FET, and RG_EXT is the external gate resistance if appli- cable. RG_EXT may be used to damp out excessive parasitic ringing at the switch node. For this example, the maximum drain-to-source voltage ap- plied to either MOSFET is 18V. The maximum drive voltage at the gate of the high-side MOSFET is 5V, and the maximum drive voltage for the low-side MOSFET is 5V. The selected MOSFET must be able to withstand 18V plus any ringing from drain to source, and be able to handle at least 5V plus ringing from gate to source. If the duty cycle of the converter is small, then the high-side MOSFET should be selected with a low gate charge in order to minimize switching loss whereas the bottom MOSFET should have a low R DSONto minimize con- duction loss. For a typical input voltage of 12V and output currents of 8A and 12A, the MOSFET selections for the design example are HAT2168 for the high-side MOSFET and RJK0330DPB for the low-side MOSFET. A 3Ω resistor for RCBT is added in series with the VDR regu- lator output, as shown in Figure 24. This helps to control the MOSFET turn-on and ringing at the switch node, without af- fecting the MOSFET turn-off. To improve efficiency, 3A, 40V Schottky diodes are placed across the low-side MOSFETs. The external Schottky diodes have a much lower forward voltage than the MOSFET body diode, and help to minimize the loss due to the body diode recovery characteristic. www.national.com 14 LM3000

The first criterion for selecting an output inductor is the induc- tance itself. In most buck converters, this value is based on the desired peak-to-peak ripple current, ΔIL that flows in the inductor along with the load current. As with switching fre- quency, the selection of the inductor is a tradeoff between size and cost. Higher inductance means lower ripple current and hence lower output voltage ripple. Lower inductance results in smaller, less expensive devices. An inductance that gives a ripple current of 1/6 to 1/3 of the maximum output current is a good starting point. (ΔIL = (1/6 to 1/3) x IOUT). Minimum in- ductance is calculated from this value, using the maximum input voltage as: By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in micro henries. The inductor ripple current is found from the minimum induc- tance equation: The second criterion is inductor saturation current rating. The LM3000 has an accurately programmed valley current limit. During an instantaneous short, the peak inductor current can be very high due to a momentary increase in duty cycle. Since this is limited by the coarse high-side switch current limit, it is advised to select an inductor with a larger core saturation margin and preferably a softer roll off of the inductance value over load current. For the design example, standard values of 1.2 μH for the 1.2V, 15A output and 2.7 μH for the 3.3V, 8A output are cho- sen to fall within the ΔIL = (1/6 to 1/3) x IOUT range. The dc loss in the inductor is determined by its series resis- tance RL. The dc power dissipation is found from: PDC = IOUT2 x RL The ac loss can be estimated from the inductor manufacturer’s data, if available. The ac loss is set by the peak-to-peak ripple current ΔIL and the switching frequency fSW. OUTPUT CAPACITORS The output capacitors filter the inductor ripple current and provide a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM3000 that provide excellent performance. The best performance is typically obtained using aluminum electrolytic, tantalum, poly- mer, solid aluminum, organic or niobium type chemistries in parallel with a ceramic capacitor. The ceramic capacitor pro- vides extremely low impedance to reduce the output ripple voltage and noise spikes, while the aluminum or other capac- itors provide a larger bulk capacitance for transient loading and series resistance for stability. When selecting the value for the output capacitor the two per- formance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated as: Where ΔVO (V) is the peak to peak output voltage ripple, ΔIL (A) is the peak to peak inductor ripple current, R C (Ω) is the equivalent series resistance or ESR of the output capacitor, fSW (Hz) is the switching frequency, and C O (F) is the output capacitance. The amount of output ripple that can be tolerated is application specific. A general recommendation is to keep the output ripple less than 1% of the rated output voltage. The output capacitor selection will also affect the output voltage droop and overshoot during a load transient. The peak tran- sient of the output voltage during a load current step is de- pendent on many factors. Given sufficient control loop bandwidth an approximation of the transient voltage can be obtained from: Where VP (V) is the output voltage transient and ΔIO (A) is the load current step change. CO (F) is the output capacitance, L (H) is the value of the inductor and RC (Ω) is the series resis- tance of the output capacitor. VL (V) is the minimum inductor voltage, which is duty cycle dependent. For D < 0.5, VL = VOUT For D > 0.5, VL = VIN - VOUT This shows that as the input voltage approaches V OUT, the transient droop will get worse. The recovery overshoot re- mains fairly constant. The loss associated with the output capacitor series resis- tance can be estimated as: Output Capacitor Design Procedure For the design example V IN = 12V, VOUT = 3.3V, D = V OUT / To meet the transient voltage specification, the maximum RC is: For the design example, the maximum R C is 18.75 m Ω. Choose RC = 15 mΩ as the design limit. From the equation for VP, the minimum value of CO is: For D < 0.5, VL = VOUT For D > 0.5, VL = VIN - VOUT With RC = VP / ΔIO this reduces to: 15 www.national.com LM3000

With RC = 0 this reduces to: Since D < 0.5, V L = V OUT. With R C = 15 m Ω, the minimum value for CO is 218 μF. The minimum control loop bandwidth fC is given by: For the design example, the minimum value for fC is 39 kHz. A 220 μF, 15 mΩ polymer capacitor in parallel with a 22 μF, 3 mΩ ceramic will meet the target output voltage ripple and transient specification. For the 1.2V, 15A output, two 220 μF, 15 mΩ polymer capac- itors in parallel with a 22 μF, 3 mΩ ceramic are chosen to meet the target design specifications. INPUT CAPACITORS The input capacitors for a buck regulator are used to smooth the large current pulses drawn by the inductor and load when the high-side MOSFET is on. Due to this large ac stress, input capacitors are usually selected on the basis of their ac rms current rating rather than bulk capacitance. Low ESR is ben- eficial because it reduces the power dissipation in the capac- itors. Although any of the capacitor types mentioned in the Output Capacitor section can be used, ceramic capacitors are common because of their low series resistance. In general the input to a buck converter does not require as much bulk ca- pacitance as the output. The input capacitors should be selected for rms current rating and minimum ripple voltage. The equation for the rms current and power loss of the input capacitor in a single phase can be estimated as: Where IO (A) is the output load current and R CIN (Ω) is the series resistance of the input capacitor. Since the maximum values occur at D = 0.5, a good estimate of the input capacitor rms current rating in a single phase is one-half of the maxi- mum output current. Neglecting the series inductance of the input capacitance, the input voltage ripple for a single phase can be estimated as: By defining the maximum input voltage ripple, the minimum requirement for the input capacitance can be calculated as: For the dual output design operating 180° out of phase, the general equation for the input capacitor rms current is ap- proximated as: Where the output currents are I1, I2 and the duty cycles are D1, D2 respectively. D3 represents the overlapping effective duty cycle, which adds to the RMS current. If D > 0.5 for both or D < 0.5 for both, the worst case rms current occurs with one output at full load and the other at no load. The maximum rms current can be approximated as: If D > 0.5 for one and D < 0.5 for the other, the worst case rms current becomes: In most applications for point-of-load power supplies, the in- put voltage is the output of another switching converter. This output often has a lot of bulk capacitance, which may provide adequate damping. When the converter is connected to a remote input power source through a wiring harness, a resonant circuit is formed by the line impedance and the input capacitors. If step input voltage transients are expected near the maximum rating of the LM3000, a careful evaluation of the ringing and possible overshoot at the device VIN pin should be completed. To minimize overshoot make C IN > 10 x L IN. The characteristic source impedance and resonant frequency are: The converter exhibits a negative input impedance which is lowest at the minimum input voltage: The damping factor for the input filter is given by: Where RLIN is the input wiring resistance and RCIN is the series resistance of the input capacitors. The term ZS / ZIN will always be negative due to ZIN. When δ = 1, the input filter is critically damped. This may be difficult to achieve with practical component values. With δ < 0.2, the input filter will exhibit significant ringing. If δ is zero or www.national.com 16 LM3000

negative, there is not enough resistance in the circuit and the input filter will sustain an oscillation. When operating near the minimum input voltage, an alu- minum electrolytic capacitor across C IN may be needed to damp the input for a typical bench test setup. Any parallel capacitor should be evaluated for its rms current rating. The current will split between the ceramic and aluminum capaci- tors based on the relative impedance at the switching fre- quency. Using a square wave approximation, the rms current in each capacitor is found from: Input Capacitor Design Procedure Ceramic capacitors are sized to support the required rms cur- rent. Aluminum electrolytic capacitors are used for damping. Treating each phase separately, find the minimum value for the ceramic capacitor from: For the design example allowing 0.25V input voltage ripple, the worst case occurs for the 3.3V, 8A output at D = 0.5. The minimum value is CIN = 16 μF. For the 1.2V, 15A output, the rms current rating for each from: Using the same criteria, results are 4A rms for the 3.3V phase and 3A rms for the 1.2V phase. Manufacturer data for 10 μF, 25V, X5R capacitors in a 1206 package allows for 3A rms with a 20°C temperature rise. For the design example, using two ceramic capacitors for each phase will meet both the input voltage ripple and rms current target. Since the series resis- tance is so low at about 5 m Ω per capacitor, a parallel alu- minum electrolytic is used for damping. A good general rule is to make the damping capacitor at least five times the value of the ceramic. By sizing the aluminum such that it is primarily resistive at the switching frequency, the design is greatly sim- plified since the ceramic is primarily reactive. In this case the approximation for the rms current in the damping capacitor is: Where CIN2 is the damping capacitance, R CIN2 is its series resistance and C IN1 is the ceramic capacitance. A 150 μF, 50V, 0.18Ω, 670 mA capacitor in a 10 mm x 10.2 mm package is chosen for each input. Calculated rms current for the 3.3V phase is 322 mA, with 242 mA calculated for the 1.2V phase. CURRENT LIMIT For the design example, the desired current limit set point is chosen to be 150% of the maximum load current. To account for the tolerance of the internal current source and allowing RDS(on) = 4 mΩ for the low-side MOSFET at elevated temper- ature, a target of 23A is used for the 1.2V output, with 13A for the 3.3V output. Following the equation from the Current Limit section the values for RLIM are 4.64 kΩ, 1% for the 1.2V output and 2.67 kΩ, 1% for the 3.3V output. TRACK Tracking for the design example is configured such that VOUT1 is controlling VOUT2. The divider values are set so that both outputs will rise together, with V OUT2 reaching its final value just before VOUT1. Following the method in the Tracking section and allowing for a 120 mV offset between FB and TRK, standard 1% values are selected for R T1 = 10 k Ω and RT2 = 35.7 kΩ. SOFT START To prevent over-shoot, the soft start time is set to be longer than the time it would take to charge the output voltage at current limit. Following the equations in the Startup section for VOUT1 and VOUT2: tSS1(MIN) = (3.3V x 242 μF) / (13A - 8A) = 160 μs tSS2(MIN) = (1.2V x 462 μF) / (23A - 15A) = 69 μs Choosing a value of CSS1 = 27 nF, the soft start time is: tSS1 = (27 nF x 0.6V) / 8.5 μA = 1.9 ms To ensure that VOUT2 tracks VOUT1, tSS2 is set at two-thirds of tSS1 by making CSS2 = 18 nF. VDD, VDR and VCB CAPACITORS VDD is used as the supply for the internal control and logic circuitry. A 1 μF ceramic capacitor provides sufficient filtering for VDD. VDR provides power for both the high-side and low-side MOSGET gate drives, and is sized to meet the total gate drive current. Allowing for ΔVVDR = 100 mV of ripple, the minimum value for CVDR is found from: Using QG_HI = 15 nC and QG_LO = 30 nC with a 5V gate drive, the minimum value for CVDR = 0.45 μF. VCB provides power for the high-side gate drive, and is sized to meet the required gate drive current. Allowing for ΔVVCB = 100 mV of ripple, the minimum value for CBOOT is found from: To use the minimum number of different components, C VDR and CBOOT are also selected as 1 μF ceramic for the design example. 17 www.national.com LM3000

Where: In general, the goal of the compensation circuit is to give high dc gain, a bandwidth that is between one-fifth and one-tenth of the switching frequency, and at least 45° of phase margin. Control Loop Design Procedure Once the power stage design is complete, the power stage components are used to determine the proper frequency compensation. By equating the power stage transfer function to the error amplifier transfer function term by term, the control loop design procedure targets an ideal single-pole system re- sponse. The compensation components will scale from the feedback divider ratio and selection of the bottom feedback divider re- sistor. A maximum value for the divider current is typically set at 1 mA. Using a divider current of 200 μA will allow for a reasonable range of values. For the bottom feedback resistor RFBB = VREF / 200 μA = 3 kΩ. Choosing a standard 1% value of 2.94 kΩ, the top feedback resistor is found from: For VOUT = 3.3V and VREF = 0.6V, RFBT = 13.2 kΩ. Based on the previously defined power stage values, calcu- late general terms: For the design example D = 0.275, R i = 0.028Ω , T = 2 μs, KSW = 1.147 and KFB = 0.1818. Choose a target crossover frequency fC greater than the min- imum control loop bandwidth from the Output Capacitors section. This is typically set between 1/10 and 1/5 of the switching frequency. Choosing fC = 100 kHz for the design example ωC = 628 krad/ sec. The switching frequency ωSW = 3.14 Mrad/sec and the error amplifier bandwidth ωBW = 62.8 Mrad/sec. Calculate the parallel equivalent C O and R C at the target crossover frequency: For the design example X1 = 0.00723, X2 = 0.0723, Z = 0.01478 and A = 0.6304. The parallel equivalent C O = 183 μF and RC = 11.9 mΩ. Find the optimal value of the enable current: If IEN is not within the range of 40μA to 160μA use either the minimum or maximum limit. Find REN from: For the design example I EN = 95.5 μ A and R EN = 44.7 k Ω. Choosing a standard value of 43 kΩ, IEN = 94.4 μA. Calculate other general terms: For the design example K SL = 0.0978, K m = 10.7 and K D = 1.73. If the enable resistor has been adjusted from the nominal val- ue to provide more noise immunity or to meet the minimum input voltage limit, calculate the optimal value of RC. The min- imum value of R C to maintain adequate phase margin for stability is about half this value. Checking for the design example RC = 9.1 mΩ. 21 www.national.com LM3000

The total power dissipated in the power components can be obtained by adding together the loss as mentioned in the MOSFET, input capacitor, output capacitor and output induc- tor sections. The efficiency is defined as: The highest power dissipating components are the power MOSFETs. The easiest way to determine the power dissipat- ed in the MOSFETs is to measure the total conversion loss (PIN - POUT), then subtract the power loss in the capacitors, inductors and LM3000. The resulting power loss is primarily in the switching MOSFETs. Selecting MOSFETs with ex- posed pads will aid the power dissipation of these devices. Careful attention to RDS(on) at high temperature should be ob- served. LM3000 OPERATING LOSS This term accounts for the current drawn at the VIN pin, used for driving the logic circuitry and the power MOSFETs. For the LM3000, this current is equal to the steady state operating current Iq plus the MOSFET gate charge current IGC, which is defined as: IGC = (QG_HI + QG_LO) x fSW PD = VIN x (Iq + IGC) Where P D represents the total power dissipated in the LM3000. Iq is about 5 mA from the Electrical Characteristics table. The LM3000 has an exposed thermal pad to aid power dissipation. Layout Considerations To produce an optimal power solution with a switching con- verter, as much care must be taken with the layout and design of the printed circuit board as with the component selection. The following are several guidelines to aid in creating a good layout. KELVIN TRACES FOR GATE DRIVE AND SENSE LINES The HG and SW pins provide the gate drive and return for the high-side MOSFET. Likewise the LG and PGND pins provide the gate drive and return for the low-side MOSFET. These lines should run as parallel pairs to each MOSFET, being connected as close as possible to the respective MOSFET gate and source. Although it may be difficult in a compact de- sign, these lines should stay away from the output inductor if possible, to avoid stray coupling. The EA_GND pins should also be connected with a separate Kelvin trace, running from the output ground sense point. The sense output, which is connecting to the top of the feedback resistor divider, should also run with a dedicated Kelvin trace together with the EA_GND. Keep these lines away from the switch node and output inductor to avoid stray coupling. If possible, the FB and EA_GND traces should be shielded from the switch node by ground planes. If necessary, the feedback divider impedance may be lowered to improve noise immu- nity. SEPARATE PGND AND SGND Good layout techniques include a dedicated signal ground plane, usually on an internal layer adjacent to the LM3000 and signal component side of the board. Signal level components like the compensation and feedback resistors should be con- nected to this internal plane. The SGND pin should connect directly to the DAP, with vias from the DAP to the signal ground plane. Separate power ground plane areas for each phase should be made on the power component side of the board, as well as other layers. This allows separate lines for each PGND pin to connect to its respective power ground plane area at each low-side MOSFET source. The signal ground plane is then connected to a quiet point on each power ground plane area. These connections are typically made at the common input/output power terminals or capacitor re- turns. An equivalent schematic representation is shown in the Typical Application Schematic of Figure 24. MINIMIZE THE SWITCH NODE The copper area that connects the power MOSFETs and out- put inductor together radiates more EMI as it gets larger. Use just enough copper to give low impedance for the switching currents and provide adequate heat spreading for the MOS- FETs. LOW IMPEDANCE POWER PATH In a buck regulator the primary switching loop consists of the input capacitor connection to the MOSFETs. Minimizing the area of this loop reduces the stray inductance, which mini- mizes noise and possible erratic operation. The ceramic input capacitors should be placed as close as possible to the MOS- FETs, with the VIN side of the capacitors connected directly to the high-side MOSFET drain, and the PGND side of the capacitors connected as close as possible to the low-side source. The complete power path includes the input capaci- tors, power MOSFETs, output inductor, and output capaci- tors. Keep these components on the same side of the board and connect them with thick traces or copper planes. Avoid connecting these components through vias whenever possi- ble, as vias add inductance and resistance. In general, the power components should be kept close together, minimizing the circuit board losses. 23 www.national.com LM3000

FIGURE 24. Typical Application Schematic

Physical Dimensions inches (millimeters) unless otherwise noted 32-Lead LLP Package 25 www.national.com LM3000

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