LM2826

LM2826 NSC | Alldatasheet

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' - r National February 1990 = Semiconductor i LS) LM2926/LM2927 5 Low Dropout Regulator with Delayed Reset rs . . La} General Description N The LM2926 is a 5V, 500 mA, low dropout regulator with the L4947 and TLE4260 alternatives. The LM2926 is pin- | [7 delayed reset. The microprocessor reset flag is set low by _for-pin compatible with the LM2925. Qo thermal shutdown, short circuits, overvoltage conditions, = dropout, and power-up. After the fault condition is corrected, Features Oo the reset flag remains low for a delay time determined by @ 5% output accuracy over entire operating range = the delay capacitor. Hysteresis is included in the reset cir- @ Dropout voltage typically 350 mV at 500 mA output ° Cuit to prevent oscillations, and a reset output is guaranteed im Externally programmed reset dela no] down to 3.2V supply input. A latching comparator is used to 'y Prog' y ° discharge the delay capacitor, which guarantees a full reset Short circuit proof S pulse even when triggered by a relatively short fault condi. Reverse battery proof tion. A patented quiescent current reduction circuit drops | ™ Thermally protected be 8] — | the ground pin current to 8 mA at full load when the input- = LM2926 is pin-for-pin compatible with the LM2925 & output differential is 3V or more. ™ 100% electrical burn-in Cc Familiar PNP regulator features such as reverse battery pro- oo iy tection, transient protection, and overvoltage shutdown are Applications - included in the LM2926 making it suitable for use in automio-_@ Battery operated equipment fe} tive and battery operated equipment. @ Microprocessor-based systems = The LM2927 is electrically identical to the LM2926 buthas am Portable instruments = different pin-out. The LM2927 is pin-for-pin compatible with = a a Typical Application 9 Unregulated o Input > Cue < . w oO we a “Required if regulator is located far (> 2") from power supply filter. = tw **Co must be at least 10 uF to maintain stability. May be increased without Ps] bound to maintain regulation during transients. Locate as close as possible Delayed = 2 _ mA o to the regulator. This capacitor msut be rated over the same operating tem- onnt (2926 Vo = 5Y, 500 7 perature range as the regulator. The equivalent series resistance (ESR) of utp ale ci] this capacitor is critical; see curve under Typical Performance Character- i) ~ istics. Ceotay 14 GND]S 10 pF

10 Lian a

Connection Diagrams and Ordering Information 5-Lead TO-220 Front View Order Number LM2926T et OELAY CAPACITOR See NS Package Number TO5A _ > _ 3 GROUND

1 INPUT VOLTAGE (Vy)

Front View _———— 5 owtrut voitace (v9) Order Number LM2927T -——————— 4 vetay capacitor See NS Package Number TO5A _——————> _ 3 GROUND +> | INPUT VOLTAGE (Vy) TLIH/10750-14

Absolute Maximum Ratings (note 1) \\f Military/Aerospace specified devices are required, ESD Susceptibility (Note 2) 2kVv please contact the National Semiconductor Sales Power Dissipation (Note 3) Internally Limited Coa tnanuters for availability and specifications. Junction Temperature (Ty ax) 450°C input Voltage Storage Temperature Range —40°C to + 150°C t= 100ms 80v Lead Temperature (Soldering, 10 sec.) 260°C t=1ms —50V . . Continuous —18V to +26V Operating Ratings (note 1) Reset Output Sink Current 10 mA Junction Temperature Range (Ty) —40°C to + 125°C Maximum Input Voltage 26V Electrical Characteristics vy = 14.4v, Co = 10 pF, — 40°C < Ty < 125°C, unless otherwise specified. Typ Units Parameter Conditions (Note 4) (Limit) REGULATOR OUTPUT Output Voltage 5MA < Io < 500mA, 4.85 V (min) Ty = 25°C v

5.16 V (max)

5 mA < Io < 500mA 4.75 V (min) 5 Vv

5.25 Vv (max)

Line Regulation lo = 5MA, SV < Vin < 16V 1 mv mV (max) lo = 5MA,7V < Vin < 26V 3 mv mV (max) Load Regulation 5 mA < Io < 500mA mv 60 mV (max) Quiescent Current lo = 5mA mA mA (max) . Ig = 500 mA mA 30 mA (max) Quiescent Current at Low Vin, lo = 5mA, Vin = 5V 3 mA mA (max) Io = 500 mA, Vin = 6V mA mA (max) Dropout Voltage (Note 6) lo = 5mA, Ty = 25°C mV mvV (max) fonsma 800 ravi lo = 500 MA, Ty = 25°C mv 600 mV (max) lo = 500mA [| | 700 | mv (man Short Circuit Current Vin = 8V, RL = 19 800 mA (min) A

3 A (max)

Ripple Rejection SRIPPLE = 120 Hz, VrippLe = 1 Vrms, Io = 50 mA [| wi dB (min) Output impedance lo = 50 mAdc and 10 mArms @ 1 kHz | to | | ma Output Noise 10 Hz to 100 kHz, lp = 50 mA [1 [| mvims Long Term Stability a Maximum Operational nputVotlage | Continuous || a vein

Electrical Characteristics

Vin = 14.4V, Co = 10 pF, ~40°C < Ty < 125°C, unless otherwise specified (Continued) Typ Units Parameter nditions Gone! (Note 4) (Limit) REGULATOR OUTPUT (Continued) Peak Transient Input Voltage Vo < 7V, Ru = 1000, t = 100 ms ee ee) Reverse DC Input Voltage Vo = -0.6V, Ry = 1000 a ee Reverse Transient input Voltage | t, = 1ms,R, = 1009 ee ee RESET OUTPUT Threshold AVo Required for Reset Condition (Note 7) —80 mV (min) 250 mv ~ 400 mV (max) Output Low Voltage Isink = 1.6 mA, Vin = 3.2V 0.15 V (max) IntoralPultup Resistance | | | Delay Time CpeLay = 10 nF (See Timing Curve) | 2 | | ms _ Minimum Operational Vin Delayed Reset Output < 0.8V, v on Power Up Isink = 1.6 mA, RL = 1000 V (min) Minimum Operational Vo Delay Reset Output < 0.8V, 07 V on Power Down Isink = 10 pA, Vin = OV : DELAY CAPACITOR PIN Threshold Difference (AVpeLay) | Change in Delay Capacitor Voltage Required for 35 V (min) Reset Output to Return High 3.75 Vv

44 V (max)

Charging Current (Ipevay) BA (min) BA BA (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: Human body model; 100 pF discharged through a 1.5 kf resistor. Note 3: The maximum power dissipation is a function of Tyyax, and @ya, and Ts, and is limited by thermal shutdown. The maximum allowable power dissipation at any ambient temperature is Po = (Tyax-Ta)/0a. If this dissipation is exceeded, the die temperature will rise above 150°C and the device will go into thermal ‘shutdown. For the LM2926 and LM2927, the junction-to-ambient thermal resistance is 53°C/W, and the junction-to-case thermal resistance is 3°C/W. Note 4: Typicals are at T, = 25°C and represent the most likely parametric norm, Note 5: Limits are 100% guaranteed by production testing. Note 6: Dropout voltage is the input-output differential at which the circuit ceases to regulate against any further reduction in input voltage. Dropout voltage is ‘measured when the output voltage (Vo) has dropped 100 mV from the nominal value measured at Vin = 14.4V. Note 7: The reset flag is set LOW when the output voltage has dropped an amount, AVo, from the nominal value measured at Vin = 14.4V.

Typical Performance Characteristics soso Output Voltage , Low Voltage Behavior , Output at Voltage Extremes seal BOSnenn ecoe TT 5.080 | ttt s Bens 4 oe sett 5 ooo ay WA co on co ee a rie] | deg a a a ° _ oo rit CCP TTT as 0S 8S OS “1 23 4 8 6 7 “lg 200 4 6080 Supply Current Quiescent Current Quiescent Current “Tssonl ) Td ° 1 Tecoma TT elem | . : 50 - g % + cntt z Fy ! z Tons A | = i = wf jet t = 7 waa = © -+. | £ ! wre 5 Fa i i z [fra | 2 T= 25° Swept zB 8 V4 & - aps 3 e Y | g 1 eH ee) ene ; Sy /MGRGene | Dropout Voltage Output Current Limit Output Capacitor ESR a EEC Bee | 8 yi | To a en ee ee ee os ts 0 0 200 300 0 ato %0 Ripple Rejection 0 Ripple Rejection k Output Impedance SaiiiiaN «| LAN ea ses Ste = 7» Thi | ests oni = 7» | fT] € ecu ae are So TUTTI oe 2 ma Corton Frees cara 0 RY 8 \\ g ee 8 HA 3 oo TT TIN TT ra “| ESR=0.50 5 5 Co oe So QT ihe = =o LOU

2 CMB (Soe

a Le) a i 00 tk 10k 100K Mm °o 6 8 W 12 14 16 18 20 ‘00 the 10k 100k M FREQUENCY (Hz) INPUT VOLTAGE (¥). FREQUENCY (Hz) TUrs0759-3

Typical Performance Characteristics (continued) Maximum Power Line Transient Response Load Transient Response Dissipation (TO-220) so = | WFINTTE HEAT Swix] = TT ee fee TTT i oo Va 3g [TTT ir 3g He s % Saeeeae Pn ee 2 [| Fe) See | [TTT TTT TT = tN ere 30 . SPT wer near sun \\ ] ge | | [TTT | ae aH a a gs tht LT 8s ol | YT § «| PTS EB ob £3 +f is oI Eg -s eee Ey-10 See {Soars a8 LU TT TT LEP T Ty A . 0 0 6 wo . wo ww “so 25025 80 75 100 125 TE (us) TIME (ys) AMBIENT TEMPERATURE, T, (°C) Reset Delay Reset Delay bed 5 5H se eee “ Bai oee Seta Pt _ 0 »” & vo t Camy = 1008 g ae oat a” PS] ow Tg | | | | Bains cee atii aa Pe ' ar eT 0-5 0 8 75 100 12S DELAY CAPACITOR (nF) JUNCTION TEMPERATURE, T, (9C) Tunri07se-4 Typical Circuit Waveforms 80V Load=dump Transient input vena 2ev 26v teas of Input Voltage | 42V Power-up Input Voltage ‘Shutdown Output Voltage Lila | fr lseley Delay Capacttor 3.75V Voltage 1 | 1 { | Delayed Reset Output ov 1 — rot 1 . TUH/10759-5

EXTERNAL CAPACITORS As shown in Figure 1, the delayed reset output is pulled low The LM2926/7 output capacitor is required for stability. by an NPN transistor (Q2), and pulled high to Vo by an Without it, the regulator output will oscillate at amplitudes as internal 30 kQ resistor (R3) and PNP transistor (Q3). The high as several volts peak-to-peak at frequencies up to reset output will operate when Vo is sufficient to bias Q2 500 kHz. Although 10 uF is the minimum recommended (0.7V or more). At lower voltages the reset output will be ina value, the actual size and type may vary depending upon high impedance condition. Because of differences in the the application load and temperature range. Capacitor Vee of Q2 and Q3 and the values of R1 and R2, Q2 is equivalent series resistance (ESR) also affects stability. The guaranteed by design to bias before Q3, providing a smooth region of stable operation is shown in the Typical Perform- transition from the high impedance state when Vo < 0.7V, ance Characteristics (Output Capacitor ESR curve). to the active low state when Vo > 0.7V. Output capacitors can be increased in size to any desired value above 10 .F. One possible purpose of this would be Yo to maintain the output voltage during brief conditions of in- put transients that might be characteristic of a particular system. R2 External Pull-up RI 100 ka Resistor Capacitors must also be rated at all ambient temperatures Soka RS expected in the system. Many aluminum electrolytics freeze = 50ka at temperatures below — 30°C, reducing their effective ca- Delayed Reset Output pacitance to zero. To maintain regulator stability down to —40°C, capacitors rated at that temperature (such as tanta- —_ we tums) must be used. RESET eo 01 DELAYED RESET _L = The delayed reset output is designed to hold a microproces- = sor in a reset state on system power-up for a programmable TUH/10759-6 time interval to allow the system clock and other powered FIGURE 1. Delay Reset Output circuitry to stabilize. A full reset interval is also generated The static reset characteristics are shown in Figure 2. This whenever the output voltage falls out of regulation. The cir- shows the relationship between the input voltage, the regul- cuit is tripped whenever the output voltage of the regulator tor output and reset output. Plots are shown for various ex- is out of regulation by the Reset Threshold value. This can ternal pull-up resistors ranging in value from 3 kQ. to an be caused by low input voltages, over current conditions, open circuit. Any external pull-up resistance causes the re- over-voltage shutdown, thermal shutdown, and by both set output to follow the regulator output until Q2 is biased power-up and power-down sequences. When the reset cir- ON. Cpe.ay has no effect on this characteristic. cuit detects one of these conditions, the delay capacitor is discharged by an SCR and held in a discharged state by a § Ta = 1008 WY saturated NPN switch. As long as the delay capacitor is held 5 {Co= 10uF low, the reset output is also held low. Because of the action Bee of the SCR, the reset output cannot glitch on noise or tran- s 4 Hf sient fault conditions. A full reset pulse is obtained for any 8 3 || Wii i fault condition that trips the reset circuit. = | fron rm | When the output regains regulation, the SCR is switched off S 3 4. and a small current (IpeLay = 2 A) begins charging the LA] pwd | | delay capacitor. When the capacitor voltage increases 1 Va2na an 3.75V (AVp_ELay) from its discharged value, the reset output ° VA hi is again set HIGH. The delay time is calculated by: © 200 400 600 800 1000 1200 1400 delay time = CDELAY AVDELAY «) TME (3) IDELAY TL/H/10759-7 or FIGURE 2. Reset Output Behavior during Power-Up delay time = 1.9 x 108 Cogtay 2) Figure 2 is useful for determing reset performance at any The constant, 1.9 x 108, has a +20% tolerance from de- Particular input voltage. Dynamic performance at power-up Vice to device. The total delay time error budget is the sum will closely follow the characteristics illustrated in Figure 2, of the 20% device tolerance and the tolerance of the exter- except for the delay added by CpgLay when Vo reaches 5V nal capacitor. For a 20% timing capacitor tolerance, the The dynamic reset characteristics at power-down are illus- worst case total timing variation would amount to + 40%, or trated by the curve shown in Figure 3. At time t=0 the input a ratio of 2.33:1. In most applications the minimum expected voltage is instantaneously brought to OV, leaving the output reset pulse is of interest. This occurs with minimum CpeLay, powered by Co. As the voltage on Co decays (discharged minimum AVpecay. and maximum IpeLay- AVpeLay and by a 10021 load resistor), the reset output is held low. As Vo IDELAy are fully specified in the Electrical Characteristics. drops below 0.7V, the reset rises up slightly should there be Graphs showing the relationship between delay time and any external pull-up resistance. With no external resistance, both temperature and Cpg.ay are shown in the Typical the reset line stays low throughout the entire power down Performance Characteristics. cycle. If the input voltage does not fall instantaneously, the reset signal will tend to follow the performance characteris- tics shown in Figure 2.

FIGURE 3. Reset Output Behavior during Power-Down >) plied by the LM 2926/7 may fail to bring the processor un- .

Applications Information (continued) Using the Reset to De-Activate Power Loads. The LM1921 is a Fully Protected 1 Amp High-Side Driver. 1 uF =a Delayed Your _5V¥/500 mA Reset 1M2926/27 o Output Cdotay GNO + T tour o os Input 2 LI Besar ve =e = = a vot po fe ~ TLH/10759-11 Generating an Active High Reset Signal Using the Reset to Ensure an Accurate Display on Power-Up or Power-Down Vy ~ 1m2926/27 © Your a 1 uF r tod EO = Coetay [ND [Delayed = Delayed Your _5V¥/500mA = 001 wr" Reset Reset het 2926/27 ° mr utp = = Cdeiey GND + 1k tour = w il TL/H/10759-12 = Reset Yoo uP nD Suu = ve = BEEEEGEE Kaa spay Kaif aw | TL/H/10759-13

7] . . . Lit #107996

2 Physical Dimensions inches (mitimeters)

x 0.395-0.420 SEATING PLANE 3 (10.03-10.57) eT OIA 0.180 -0.005 > (0435 0080 (asra-0127 @ | 0.050 -0.002 o oo I arare-o08n [a] 0.250 -0.010 <= 4 (350-0254) | = 0.110 -0.010 Y i cor Ky 0.340 +0.010 yeaes. - (w36-0.254) (oJ = rk e Ly | ec ~ 0.540 0.015 4 3716-0380) a a ’ 0.015 “ho02 (0.889 +0.127) +02 3 (2667 “p31 nn 0.067 -0.005 “N I Groene N $ earn oa 5-Lead TO-220 Outline Drawing ~N Order Number LM2926T or LM2927T o NS Package Number T0SA N o By al LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury Y to the user. MAR 1 2 1991 ces awe ZA National Semiconductor ‘National Semiconductor NS Japan Ltd. National Semiconductor, National Semicondutores: National Semiconductor, Corporation GmoH Sanseco B19. 5 Hong Kong Lis. Do Brast Lica. (Austra) PTY, Lt 2500 Somsconductor Dove _Industiestass0 10 415 Neh Shrpky—St S13 80h Floor AY. Bog. ana Lia, 1989 Yet Flor 441 St Kile Ro. 7.0 ox 56000 D.8080 Furstonilruck — Shwkerku Chinachem Golden Ptaza, 66 Andor Con, 62 Motourne, 2004 Sania Gara, CA 95052-8090 West Germany oryo 160, Japan 77 Mody Road, Tsemshatas East, 01451 Seo Paulo SP. Bask Vitor. Asan Tet (408) 721-5000 Yor (081-41) 1090 Ter'3200-700' Kowloon, Hong Kong Tot (55/19) 242.5066 Tor (09) 267-5000 TW (610) 399.9240 Tole: 527-649 Fax 3299-7000 Tor 9.7291290 Fae (65/11) 241-181 NSBR BR Fax 61-9-2677458 Fax (08441) 109554 Tol. 52006 NSSEA HX Fax 32112506, Nabona doos not assure any respons ous fay utr desenbed no crc “en ro imped and Nationa rseres te ght at anytime witout noice to change acct and specications