LM2715_06 NSC | Alldatasheet
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Technical content
Features
n 1.3A, 0.18Ω, internal power switch n VIN operating range: 2.2V to 12V n 1.25MHz switching frequency step-up DC/DC converter n Inrush current limiting circuitry n Internal 7Ω PMOS switch n PMOS switch control pin n PMOS switch delay pin n Vcom amplifier n Gamma buffer n 16 pin TSSOP or 24 pin LLP packages
Applications
Typical Application Circuit 20058431 April 2006 LM2715 TFT Panel Module © 2006 National Semiconductor Corporation DS200584 www.national.com
TJMAX = 125˚C,θJA = 120˚C/W(Note 1) Top View 20058494 LLP 24 package TJMAX = 125˚C,θJA = 33.2˚C/W(Note 1) Pin Description (TSSOP) Pin Name Function 1 Vcom+ Vcom Amplifier positive input. 2 Vcom− Vcom Amplifier negative input. 3 Vcom Vcom Amplifier output. 4 AGND Analog Ground. Connect to AGND plane. 5 Delay PMOS switch delay. C Boost Compensation Network Connection. 7 FB Output Voltage Feedback input. 8 PGND Power Ground. Connect to PGND plane. LM2715 www.national.com 2
Pin Description (TSSOP) (Continued) Pin Name Function 9 SW NMOS power switch input. 10 V IN Main power input, step-up and switch circuitry. 11 SWI PMOS switch input. 12 SWO PMOS switch output. 13 SWC PMOS switch control pin. 14 AV IN Analog power input (buffers). 15 GMA Gamma buffer output. 16 GMA+ Gamma buffer input. Pin Description (LLP) Pin Name Function 1 Vcom- Vcom Amplifier negative input. 2 Vcom Vcom Amplifier output. 3 AGND Analog Ground. Connect to AGND plane. 4 Delay PMOS switch delay. C Boost Compensation Network Connection. 6 FB Output Voltage Feedback input. 7 PGND Power Ground. Connect to PGND plane. 8 PGND Power Ground. Connect to PGND plane. 9 NC Not internally connected. Leave floating or connect to Ground. 10 NC Not internally connected. Leave floating or connect to Ground. 11 SW NMOS power switch input. 12 SW NMOS power switch input. 13 SW NMOS power switch input. 14 V IN Main power input, step-up and switch circuitry. 15 SWI PMOS switch input. 16 SWO PMOS switch output. 17 SWC PMOS switch control pin. 18 AV IN Analog power input (buffers). 19 GMA Gamma buffer output. 20 GMA+ Gamma buffer input. 21 NC Not internally connected. Leave floating or connect to Ground. 22 NC Not internally connected. Leave floating or connect to Ground. 23 NC Not internally connected. Leave floating or connect to Ground. 24 Vcom+ Vcom Amplifier positive input. DAP DAP Center Die Attach Pad. Connect directly to AGND and PGND pins beneath the device. Pin Functions Vcom+: Positive input terminal of Vcom amplifier. Vcom−: Negative input terminal of Vcom amplifier. Vcom: Output terminal of Vcom amplifier. AGND: Analog ground connection for LM2715. Connect all sensitive circuitry, ie. feedback resistors, delay capacitor, and compensation network to its own dedicated AGND plane which connects directly to this pin. Delay: PMOS switch delay control pin. See Operation sec- tion for setting the delay time. The delay time begins when the output voltage of the DC/DC switching regulator reaches 85% of its true output voltage. This corresponds to a FB voltage of about 1.1V. The PMOS switch is controlled with both the delay time and the switch control pin, SWC. If no Cdelay capacitor is used, the PMOS switch is controlled solely with the SWC pin. V C: Compensation Network for Boost switching regulator. Connect resistor/capacitor network between V C pin and AGND for boost switching regulator AC compensation. FB: Feedback pin. Set the output voltage by selecting values of R1 and R2 using: Connect the ground of the feedback network to the AGND plane, which should be tied directly to the PGND pin. LM2715 www.national.com3
Pin Functions (Continued) PGND:Connect all power ground components to a PGND plane which should also connect directly to this pin. Use a trace or via to connect the AGND plane to the PGND plane. Please see Layout Considerations under the Operation sec- tion for more details on layout suggestions. SW: This is the drain of the internal NMOS power switch. Minimize the metal trace area connected to this pin to mini- mize EMI. V IN: Input Supply Pin. Bypass this pin with a capacitor as close to the device as possible. The capacitor should con- nect between V IN and PGND. SWI: PMOS switch input. Source connection of PMOS de- vice. SWO: PMOS switch output. Drain connection of PMOS device. SWC: PMOS switch control pin. This pin creates an AND function with the delay time after the output of the switching regulator has reached 85% of its nominal value. To ensure the PMOS switch is in the correct state, apply a voltage above 1.5V to this pin to turn on the PMOS switch and apply a voltage below 0.7V to turn off the PMOS switch. AV IN: Supply pin for the Vcom opamp and the Gamma buffer. Bypass this pin with a capacitor as close to the device as possible, about 100nF, if connected directly to the output of the boost DC/DC switching regulator. The capacitor should connect between AV IN and PGND. GMA: Gamma Buffer output pin. GMA+: Gamma Buffer input pin. Ordering Information (TSSOP) Order Number Package Type NSC Package Drawing Supplied As LM2715MT-ADJ TSSOP-16 MTC16 73 Units, Rail LM2715MTX-ADJ TSSOP-16 MTC16 2500 Units, Tape and Reel Ordering Information (LLP) Order Number Spec Package Type NSC Package Drawing Supplied As LM2715SQ-ADJ LLP-24 SQA24B 1000 Units, Tape and Reel LM2715SQX-ADJ LLP-24 SQA24B 4500 Units, Tape and Reel LM2715SQ-ADJ NOPB LLP-24 SQA24B 1000 Units, Tape and Reel LM2715SQX-ADJ NOPB LLP-24 SQA24B 4500 Units, Tape and Reel LM2715 www.national.com 4
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Absolute Maximum Ratings(Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V IN -0.3V to 12V SW Voltage -0.3V to 18V FB Voltage -0.3V to 2V V C Voltage 0.96V to 1.56V SWC Voltage -0.3V to 12V Supply Voltage, AV IN -0.3V to 12V Amplifier/Buffer Input Voltage Rail-to-Rail Amplifier/Buffer Output Voltage Rail-to-Rail Delay GND to 1.3V SWI -0.3V to 30V SWO -0.3V to 30V ESD Ratings (Note 3) Human Body Model 2kV Operating Conditions Operating Temperature −40˚C to +125˚C Storage Temperature −65˚C to +150˚C Supply Voltage, V IN 2.2V to 12V SW Voltage 17.5V Supply AV IN 4V to 12V SWI 2.2V to 30V Electrical Characteristics — Switching Regulator Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified VIN =2.2V, AVIN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. Switching Regulator Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units IQ Quiescent Current Not Switching, FB = 2V 1.6 2.3 mASwitching, switch open, FB = 0.1V 3.6 4.3 VFB Feedback Voltage 1.239 1.265 1.291 V %VFB/∆VIN Feedback Voltage Line Regulation 0.01 0.1 %/V ICL Switch Current Limit (Note 6) VIN = 2.5V, VOUT =8 V 1.29 A RDSON Switch RDSON (Note 7) V IN = 2.5V 178 m Ω IB FB Pin Bias Current (Note 8) 60 200 nA VIN Input Voltage Range 2.2 12 V TSS Internal Soft Start Ramp Time 7m S gm Error Amp Transconductance ∆I = 5µA 85 110 270 µmho AV Error Amp Voltage Gain 135 V/V DMAX Maximum Duty Cycle 78 85 % fS Switching Frequency 1.0 1.25 1.5 MHz IL Switch Leakage Current V SW = 18V 0.1 20 µA UVP On Threshold 1.79 1.92 2.05 V Off Threshold 1.69 1.82 1.95 V Hysteresis 100 mV LM2715 www.national.com 6
Electrical Characteristics — Vcom Amplifier Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified VIN =2.2V, AVIN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. Vcom Amplifier Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units VOS Input Offset Voltage (Note 9) V CM = 1V 3.5 10 mVVCM = 7.5V 3 10 IB Input Bias Current V CM = 1V 55 200 nAVCM = 7.5V (Note 8) 190 300 IOS Input Offset Current V CM = 1V 40 130 nAVCM = 7.5V 5 110 CMVR Input Common-mode Voltage Range 08 V VOUT Swing R L=10k, Vo min. 0.003 .02 VRL=10k, Vo max. 7.94 7.98 RL=2k, Vo min. 0.003 .02 RL=2k, Vo max. 7.9 7.95 AVOL Large Signal Voltage Gain No Load, Vo = 2V to 7V 74.8 87.6 dBRL=10 kΩ,V o=2 Vt o7 V 66.8 75.1 RL=2 kΩ, Vo = 2V to 7V 55.8 AVIN Supply Voltage 41 2 V CMRR Common Mode Rejection Ratio VCM stepped from 0V to 0.9V 72 93.5 dBVCM stepped from 3V to 8V 80 105 VCM stepped from 0V to 8V 57 80.7 PSRR Power Supply Rejection Ratio VCM = 0.5V, AVIN =4t o1 2 V 70 77 dB Is+ Supply Current (Amplifier + Buffer) V o=A VIN/2, No Load 2.5 4.3 mA ISC Output Short Circuit Current Source 45 60 mASink 40 50 Electrical Characteristics — Gamma Buffer Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified VIN =2.2V, AVIN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. Gamma Buffer Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units VOS Input Offset Voltage (Note 9) 1 10 mV IB Input Bias Current (Note 8) 170 300 nA VGR Gamma Input Voltage Range 08 V VOUT Swing R L=10k, Vo min. 0.05 0.075 VRL=10k, Vo max. 7.9 7.94 RL=2k, Vo min. 0.05 0.075 RL=2k, Vo max. 7.865 7.9 AVCL Voltage Gain No Load, Vo = 2V to 7V 0.995 0.999 V/VRL=10 kΩ,V o=2 Vt o7 V 0.995 0.999 RL=2 kΩ,V o=2 Vt o7 V 0.993 0.998 PSRR Power Supply Rejection Ratio AVIN =4t o1 2 V 70 77 dB AVIN Supply Voltage 41 2 V LM2715 www.national.com7
Electrical Characteristics — Gamma Buffer (Continued) Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified VIN =2.2V, AVIN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. Gamma Buffer Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units Is+ Supply Current (Amplifier + Buffer) V o=A VIN/2, No Load 2.5 4.3 mA ISC Output Short Circuit Current Source 50 66 mASink 40 56 Electrical Characteristics — PMOS Switch Logic Control Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified VIN =2.2V, AVIN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. PMOS Switch Logic Control Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units IDELAY Delay Current 4.7 5.7 6.4 µA RDSON PMOS Switch ON Resistance 7 20 Ω ISWO PMOS Switch Current Switch ON 20 mA ISWI PMOS Switch Input Current SWC = 0V, SWO Open, SWI = 30V 50 100 µASWC = 1.7V, SWO Open, SWI = 30V 175 350 VSWC Switch ON 1.5 1.1 VSwitch OFF 1.1 0.7 Note 1: The maximum allowable power dissipation is a function of the maximum junction temperature, T J(MAX), the junction-to-ambient thermal resistance, θJA, and the ambient temperature, T A. The maximum allowable power dissipation at any ambient temperature is calculated using: P D (MAX) = (T J(MAX) −T A)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Note 2: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Ch aracteristics. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k Ω resistor into each pin. Note 4: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested or guaranteed through statistical analysis. All limits at temperature extremes are guaranteed via correlation using standard St atistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 5: Typical numbers are at 25˚C and represent the most likely norm. Note 6: Duty cycle affects current limit due to ramp generator. SeeTypical Performance Characteristicsfor a graph of Power Switch Current Limit vs. VIN and Power Switch Current Limit vs. Temp. Note 7: See Typical Performance Characteristicssection for Tri-Temperature data for RDSON vs. VIN. Note 8: Bias current flows into pin. Note 9: Refer to the graphs titled "Input Offset Voltage vs. Common Mode Voltage". LM2715 www.national.com 8
Typical Performance Characteristics Efficiency vs. Load Current (VOUT = 8V) Efficiency vs. Load Current (VOUT = 10V) 20058426 20058473 Frequency vs. VIN Power Switch Current Limit vs. Temperature (VOUT = 8V) 20058425 20058420 Power Switch Current Limit vs. VIN RDSON vs. VIN (ISW = 1A) 20058422 20058427 LM2715 www.national.com9
Typical Performance Characteristics (Continued) IQ vs. VIN (not switching) IQ vs. VIN (switching) 20058421 20058429 Feedback Current vs. Temperature Delay Current vs. V IN 20058463 20058465 PMOS RDSON vs. SWI Voltage SWI Current vs. SWI Voltage (PMOS ON) 20058466 20058467 LM2715 www.national.com 10
Typical Performance Characteristics (Continued) SWI Current vs. SWI Voltage (PMOS OFF) Load Transient Response 20058468 20058416 VOUT = 8V, VIN = 2.5V 1) Load, 80mA to 145mA to 80mA 2) I L, 500mA/div, DC 3) VOUT, 100mV/div, AC T = 50µs/div Load Transient Response PMOS Switching Waveform 20058490 VOUT = 10V, VIN = 2.5V 1) Load, 100mA to 300mA to 100mA, DC 2) I L, 500mA/div, DC 3) VOUT, 200mV/div, AC T = 50µs/div 20058458 VOUT = 8V, VIN = 2.5V, RLOAD =4 0Ω CD = 100nF, RSW = 10k\\1.5k, SWI = 30V, 10% duty cycle 1) SWC, 1V/div, DC 2) SWO, 10V/div, DC T = 2.5µs/div PMOS Rising Edge PMOS Falling Edge 20058459 VOUT = 8V, VIN = 2.5V, RLOAD =4 0Ω CD = 100nF, RSW = 10k\\1.5k, SWI = 30V 1) SWC, 1V/div, DC 2) SWO, 10V/div, DC T = 50ns/div 20058460 VOUT = 8V, VIN = 2.5V, RLOAD =4 0Ω CD = 100nF, RSW = 10k\\1.5k, SWI = 30V 1) SWC, 1V/div, DC 2) SWO, 10V/div, DC T = 50ns/div LM2715 www.national.com11
Typical Performance Characteristics (Continued) Internal Soft Start and PMOS Delay Input Offset Voltage vs. Common Mode Voltage (Vcom, 3 units) 20058461 VOUT = 8V, VIN = 2.5V, RLOAD =3 2Ω CD = 100nF, RSW = 10k\\1.5k, SWI = 30V, SWC = V IN 1) VIN, 2V/div, DC 2) VOUT, 5V/div, DC 3) IL, 500mA/div, DC 4) SWO, 20V/div, DC T = 5ms/div 20058474 Input Offset Voltage vs. Common Mode Voltage (Vcom Over Temperature) Input Offset Voltage vs. Common Mode Voltage (Gamma, 3 units) 20058475 20058476 Input Offset Voltage vs. Common Mode Voltage (Gamma Over Temperature) Input Bias Current vs. Common Mode Voltage (Vcom) 20058477 20058478 LM2715 www.national.com 12
Typical Performance Characteristics (Continued) Input Bias Current vs. Common Mode Voltage (Gamma) Output Voltage vs. Output Current (Vcom or Gamma, sinking) 20058479 20058480 Output Voltage vs. Output Current (Vcom or Gamma, sourcing) Supply Current vs. Common Mode Voltage (Both Amplifiers) 20058481 20058482 Large Signal Step Response Negative Slew Rate vs. Capacitive Load (Vcom or Gamma) 20058483 20058484 LM2715 www.national.com13
Typical Performance Characteristics (Continued) Positive Slew Rate vs. Capacitive Load (Vcom or Gamma) Phase Margin vs. Capacitive Load (Vcom) 20058485 20058492 Unity Gain Frequency vs. Capacitive Load (Vcom) CMRR vs. Frequency (Vcom) 20058493 20058488 PSRR vs. Frequency (Vcom) 20058489 LM2715 www.national.com 14
The ratio of these two cycles determines the output voltage. internal soft-start circuitry, typically 7ms. until a desired amount of time after the switcher starts up. FIGURE 1. Simplified Boost Converter Diagram
The LM2715 contains a current mode PWM boost converter. great, the circuit will be unstable above duty cycles of 50%. be necessary to increase the inductance by as much as 2X. tion for other design requirement. components will be chosen to produce stability. The inductor ripple current is important for a few reasons. ripples are also affected by the total ripple current. FIGURE 2. (a) Inductor current. (b) Diode current.
Operation (Continued) exceed the switch current limit. Using Schottky diodes with lower forward voltage drop will decrease power dissipation and increase efficiency. DC GAIN AND OPEN-LOOP GAIN Since the control stage of the converter forms a complete feedback loop with the power components, it forms a closed- loop system that must be stabilized to avoid positive feed- back and instability. A value for open-loop DC gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover frequency and the phase margin. A high phase margin (greater than 45˚) is desired for the best stability and transient response. For the purpose of stabilizing the LM2715, choosing a crossover point well be- low where the right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and checking the crossover using the DC gain will follow. INPUT AND OUTPUT CAPACITOR SELECTION The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is required to reduce the input ripple and noise for proper operation of the regulator. The size used depends on the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of the regulator is very close to the source output. The size will generally need to be larger for applications where the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value of 10µF should be used for the less stressful conditions while a 22µF to 47µF capacitor may be required for higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very low ripple on the input source voltage. The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted R ESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require more compen- sation which will be explained later on in the section. The ESR is also important because it determines the peak to peak output voltage ripple according to the approximate equation: OUT ) 2∆iLRESR (in Volts) A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output capaci- tor you can determine a pole-zero pair introduced into the control loop by the following equations: Where RL is the minimum load resistance corresponding to the maximum load current. The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the High Output Capacitor ESR Compensationsection. RIGHT HALF PLANE ZERO A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90˚ in the phase plot. This can cause undesirable effects if the control loop is influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be designed to have a bandwidth of less than 1/6 the frequency of the RHP zero. This zero occurs at a frequency of: where ILOAD is the maximum load current. SELECTING THE COMPENSATION COMPONENTS The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in the control loop. Simply choose values for RC and CC within the ranges given in the Introduction to Compensationsection to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is determined by the equation: where R O is the output impedance of the error amplifier, approximately 1MΩ. Since R C is generally much less than RO, it does not have much effect on the above equation and can be neglected until a value is chosen to set the zero f ZC. fZC is created to cancel out the pole created by the output capacitor, fP1. The output capacitor pole will shift with differ- ent load currents as shown by the equation, so setting the zero is not exact. Determine the range of f P1 over the ex- pected loads and then set the zero f ZC to a point approxi- mately in the middle. The frequency of this zero is deter- mined by: Now R C can be chosen with the selected value for C C. Check to make sure that the pole f PC is still in the 10Hz to 500Hz range, change each value slightly if needed to ensure both component values are in the recommended range. After checking the design at the end of this section, these values can be changed a little more to optimize performance if desired. This is best done in the lab on a bench, checking the load step response with different values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should produce a stable, high performance circuit. For improved transient response, higher values of R C should be chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to tran- sients. If more detail is required, or the most optimal perfor- mance is desired, refer to a more in depth discussion of compensating current mode DC/DC switching regulators. LM2715 www.national.com17
Operation (Continued) HIGH OUTPUT CAPACITOR ESR COMPENSATION When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding another capaci- tor, C C2, directly from the compensation pin VC to ground, in parallel with the series combination of R C and CC. The pole should be placed at the same frequency as f Z1, the ESR zero. The equation for this pole follows: To ensure this equation is valid, and that C C2 can be used without negatively impacting the effects of R C and CC,f PC2 must be greater than 10f ZC. CHECKING THE DESIGN The final step is to check the design. This is to ensure a bandwidth of 1/6 or less of the frequency of the RHP zero. This is done by calculating the open-loop DC gain, A DC. After this value is known, you can calculate the crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/ decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is less than 1/6 the RHP zero, the phase margin should be high enough for stability. The phase margin can also be improved by adding C C2 as discussed earlier in the section. The equation for A DC is given below with additional equations required for the calculation: mc ) 0.181fs (in V/s) where RL is the minimum load resistance, V IN is the mini- mum input voltage, g m is the error amplifier transconduc- tance found in the Electrical Characteristics table, and R D- SON is the value chosen from the graph "R DSON vs. VIN "i n the Typical Performance Characteristicssection. LAYOUT CONSIDERATIONS Vcom AND Gamma If the supply input, AV IN, of the Vcom amplifier and Gamma buffer is tied directly to the output of the boost DC/DC converter, a 100nF bypass capacitor should be connected close to the device between AV IN and PGND. If the AV IN supply is connected to an external source, a larger bypass capacitor may be required for desired performance depend- ing on the external supply voltage ripple and noise. The Gamma buffer and Vcom amplifier input signal traces should be routed away from the SW pin. Routing these traces near the SW pin may inject noise into the device and affect the performance of the amplifier and/or buffer. If resis- tor dividers are used to drive the inputs of either the Vcom amplifier or Gamma buffer the ground connections for them should be made to AGND to minimize noise. BOOST SWITCHING REGULATOR The LM2715 uses two ground connections, PGND and AGND. The feedback, delay, and compensation networks should be connected directly to their own dedicated analog ground plane and this ground plane must connect to the AGND pin, as shown in Figure 3. No other circuits should connect to this AGND plane. If no analog ground plane is available then the ground connections of the feedback, de- lay, and compensation networks must tie directly to the AGND pin, as show in Figure 4. Connecting these networks to the PGND plane can inject noise into the system and effect performance. The input bypass capacitor C IN must be placed close to the device and should connect between VIN and PGND. This will reduce copper trace resistance which effects input voltage ripple of the IC. For additional input voltage filtering, a 100nF bypass capacitor can be placed in parallel with C IN, close to the VIN pin, to shunt any high frequency noise to ground. The output capacitor, C OUT, should also be placed close to the device and should connect between V OUT and PGND. Any copper trace connections for the C OUT capacitor can in- crease the series resistance, which directly effects output voltage ripple and efficiency. The feedback network, resis- tors R1 and R2, should be kept close to the FB pin, and away from the inductor, to minimize copper trace connec- tions that can inject noise into the system. Trace connections made to the inductor and schottky diode should be mini- mized to reduce power dissipation and increase overall effi- ciency. The AGND and PGND pins must connect directly to each other at the device as shown in Figure 3 and Figure 4. Failure to do so may affect the performance of the LM2715 and limit its output current capability. LM2715 www.national.com 18
Physical Dimensions inches (millimeters) unless otherwise noted TSSOP-16 Pin Package (MTC) For Ordering, Refer to Ordering Information Table LLP-24 Pin Package (SQ) For Ordering, Refer to Ordering Information Table LM2715 www.national.com21
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