LM2710

LM2710 NSC | Alldatasheet

Document overview

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Technical content

Features

n 1.4A, 0.17Ω, internal power switch n VIN operating range: 2.2V to 7.5V n 600kHz/1.25MHz selectable frequency step-up DC/DC converter n 20 pin TSSOP package n Inrush current limiting circuitry n External softstart override n Vcom buffer n 4 Gamma buffers

Applications

n Cellular Phones/Digital Cameras Typical Application Circuit 20043431 February 2004 LM2710 TFT Step-up PWM DC/DC Converter Integrated with 5 Buffers © 2004 National Semiconductor Corporation DS200434 www.national.com

TJMAX = 125˚C,θJA = 120˚C/W(Note 1) Pin Description Pin Name Function 1V SW Power switch input. 2V IN Switching Regulator Power input. 3 SHDN Shutdown pin, active low. 4 FSLCT Frequency Select pin. FSLCT = V IN for 1.25 MHz, FSLCT = AGND or floating for 600kHz. 5 Vs+ Vcom and Gamma Buffer input supply. 6 Vcom-in Vcom Buffer input. 7 GMA1-in Gamma Buffer input. 8 GMA2-in Gamma Buffer input. 9 GMA3-in Gamma Buffer input. 10 GMA4-in Gamma Buffer input. 11 GMA4-out Gamma Buffer output. 12 GMA3-out Gamma Buffer output. 13 GMA2-out Gamma Buffer output. 14 GMA1-out Gamma Buffer output. 15 Vcom-out Vcom Buffer output. 16 SS Soft start pin. 17 V C Boost Compensation Network Connection. 18 FB Output Voltage Feedback input. 19 AGND Vcom and Gamma Buffer ground, Analog ground connection for Regulator. 20 GND Switch Power Ground. LM2710 www.national.com 2

VSW(Pin 1): This is the drain of the internal NMOS power switch. Minimize the metal trace area connected to this pin to minimize EMI. V IN(Pin 2):Input Supply Pin. Bypass this pin with a capacitor as close to the device as possible. The capacitor should connect between V IN and GND. SHDN(Pin 3): Shutdown Pin. The shutdown pin signal is active low. A voltage of less than 0.3V disables the device. A voltage greater than 0.85V enables the device. FSLCT(Pin 4):Frequency Select Pin. Connecting FSLCT to AGND selects a 600 kHz operating frequency for the switch- ing regulator. Connecting FSLCT to V IN selects a 1.25 MHz operating frequency. If FSLCT is left floating, the switching frequency defaults to 600 kHz. Vs+(Pin 5): Supply pin for the Vcom buffer and the four Gamma buffers. Bypass this pin with a capacitor as close to the device as possible. The capacitor should connect be- tween Vs+ and GND. Vcom-in(Pin 6):Vcom Buffer input pin. GMA1-in(Pin 7):Gamma Buffer input pin. GMA2-in(Pin 8):Gamma Buffer input pin. GMA3-in(Pin 9):Gamma Buffer input pin. GMA4-in(Pin 10):Gamma Buffer input pin. GMA4-out(Pin 11):Gamma Buffer output pin. GMA3-out(Pin 12):Gamma Buffer output pin. GMA2-out(Pin13): Gamma Buffer output pin. GMA1-out(Pin 14):Gamma Buffer output pin. Vcom-out(Pin 15):Vcom Buffer output pin. SS(Pin 16): Softstart pin. Connect capacitor to SS pin and AGND to slowly ramp inductor current on startup. V C(Pin 17): Compensation Network for Boost switching regulator. Connect resistor/capacitor network between V C pin and AGND for boost switching regulator AC compensa- tion. FB(Pin 18):Feedback pin. Set the output voltage by select- ing values of R1 and R2 using: Connect the ground of the feedback network to the AGND plane, which can be tied directly to the GND pin. AGND(Pin 19): Analog ground pin. Ground connection for the Vcom buffer, Gamma buffers and the boost switching regulator. AGND must be tied directly to GND at the pins. GND(Pin 20):Power ground pin. Ground connection for the NMOS power device of the boost switching regulator. GND must be tied directly to AGND at the pins.

Ordering Information

Order Number Package Type NSC Package Drawing Supplied As LM2710MT-ADJ TSSOP-20 MTC20 73 Units, Rail LM2710MTX-ADJ TSSOP-20 MTC20 2500 Units, Tape and Reel LM2710 www.national.com3

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Absolute Maximum Ratings(Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V IN -0.3V to 7.5V VSW Voltage -0.3V to 18V FB Voltage -0.3V to 7V V C Voltage 0.965V to 1.565V SHDN Voltage -0.3V to VIN FSLCT Voltage AGND to V IN Supply Voltage, Vs+ -0.3V to 12V Buffer Input Voltage Rail-to-Rail Buffer Output Voltage Rail-to-Rail ESD Ratings (Note 3) Human Body Model 2kV Machine Model 200V Operating Conditions Operating Temperature −40˚C to +125˚C Storage Temperature −65˚C to +150˚C Supply Voltage, V IN 2.2V to 7.5V VSW Voltage 17V Supply Vcom Buffer, Vs+ 4V to 12V Supply Gamma Buffer, Vs+ 4V to 12V

Electrical Characteristics

Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified, V IN =2.2V and Vs+ = 8V, Rox = 50 Ω, Cox = 1nF. Switching Regulator Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units IQ Quiescent Current Not Switching, FSCLT = 0V 1.6 2 mANot Switching, FSCLT = V IN 1.65 2.2 Switching, FSCLT = 0V 2.5 3 Switching, FSCLT = V IN 3.4 4 Shutdown mode 6 15 µA VFB Feedback Voltage 1.239 1.265 1.291 V %VFB/∆VIN Feedback Voltage Line Regulation 0.03 0.05 %/V ICL Switch Current Limit (Note 6) VIN = 2.5V, V OUT =8 V 1.4 A RDSON Switch RDSON (Note 7) V IN = 2.7V 170 m Ω IB FB Pin Bias Current(Note 8) 30 90 nA VIN Input Voltage Range 2.2 7.5 V ISS Soft Start Current 5 11 15 µA TSS Internal Soft Start Ramp Time FSLCT = 0V 6.7 10 mS gm Error Amp Transconductance ∆I = 5µA 60 135 250 µmho AV Error Amp Voltage Gain 135 V/V DMAX Maximum Duty Cycle 78 85 % fS Switching Frequency FSLCT = 0V 500 600 700 kHz FSLCT = V IN 0.9 1.25 1.5 MHz IL Switch Leakage Current V SW = 17V 0.185 20 µA SHDN SHDN Threshold Output High 0.85 0.6 V Output Low 0.6 0.3 V I SHDN Shutdown Pin Current 0V ≤ SHDN ≤ VIN 0.5 1 µA UVP On Threshold 1.8 1.9 2 V Off Threshold 1.7 1.8 1.9 V Hysteresis 100 mV LM2710 www.national.com5

Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified, V IN =2.2V and Vs+ = 8V, Rox = 50 Ω, Cox = 1nF. BUFFERS Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units VOS Input offset voltage 2.5 10 mV ∆Vos/∆T Offset Voltage Drift 8 µV/˚C IB Input Bias Current 170 800 nA CMVR Input Common-mode Voltage Range 0.05 Vs+-0.05 V ZIN Input Impedance 400 k Ω CIN Input Capacitance 1 pF IOUT Continuous Output Current Vs+=8V, Source 41 59 71 mAVs+=8V, Sink −65 −53 −36 Vs+=12V, Source 50 71 85 Vs+=12V, Sink −75 −61 −42 VOUT Swing R L=10k, Vo min. 0.075 VRL=10k, Vo max. 7.88 RL=2k, Vo min. 0.075 RL=2k, Vo max. 7.865 AVCL Voltage Gain R L =2 kΩ RL=10 kΩ 0.995 0.9985 0.998

0.9999 V/V

NL Gain Linearity R L =2 kΩ, Buffer input=0.5 to (Vs+-0.5V) 0.01 % Vs+ Supply Voltage 41 2 V PSRR Power Supply Rejection Ratio V s +=4t o1 2 V 90 316 µV/V Is+ Supply Current/Amplifier Vo = Vs+/2, No Load 1 2 mA SR Slew Rate 10 V/µs BW Bandwidth -3dB,R L =10 kΩ,C L =10pf 6 MHz φ 0 Phase Margin 50 Deg˚ Note 1: The maximum allowable power dissipation is a function of the maximum junction temperature, T J(MAX), the junction-to-ambient thermal resistance, θJA, and the ambient temperature, T A. See the Electrical Characteristics table for the thermal resistance of various layouts. The maximum allowable power dissipation at any ambient temperature is calculated using: P D (MAX) = (T J(MAX) −T A)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Note 2: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Ch aracteristics. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k Ω resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. Note 4: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested or guaranteed through statistical analysis. All limits at temperature extremes are guaranteed via correlation using standard St atistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 5: Typical numbers are at 25˚C and represent the most likely norm. Note 6: Duty cycle affects current limit due to ramp generator. See Switch Current Limit vs. V IN and Switch Current Limit vs. Temperature graphs in the Typical Performance Characteristicssection. Note 7: See Typical Performance Characteristicssection for Tri-Temperature data for RDSON vs. VIN. Note 8: Bias current flows into FB pin. LM2710 www.national.com 6

Typical Performance Characteristics Efficiency vs. Load Current (VOUT = 8V, fS = 600 kHz) Efficiency vs. Load Current (VOUT = 8V, fS = 1.25 MHz) 20043426 20043425 Efficiency vs. Load Current (VOUT = 10V, fS = 1.25 MHz) Switch Current Limit vs. Temperature (VOUT = 8V) 20043460 20043420 Switch Current Limit vs. VIN RDSON vs. VIN (ISW = 1A) 20043422 20043427 LM2710 www.national.com7

Typical Performance Characteristics (Continued) IQ vs. VIN (600 kHz, not switching) IQ vs. VIN (600 kHz, switching) 20043421 20043429 IQ vs. VIN (1.25 MHz, not switching) IQ vs. VIN (1.25 MHz, switching) 20043421 20043419 IQ vs. VIN (In shutdown) Frequency vs. VIN (600 kHz) 20043418 20043423 LM2710 www.national.com 8

Typical Performance Characteristics (Continued) Frequency vs. VIN (1.25 MHz) Feedback Pin Current vs. Temperature 20043424 20043457 CSS Pin Current vs. VIN Load Transient Response 20043458 20043476 VOUT = 8V, V IN = 3V, F = 1.25MHz 1) Load, 80mA to 260mA to 80mA 2) I L, 500mA/div, DC 3) VOUT, 100mV/div, AC T = 100µs/div Load Transient Response Load Transient Response 20043483 VOUT = 8V, V IN = 3V, F = 600kHz 1) Load, 80mA to 260mA to 80mA 2) I L, 500mA/div, DC 3) VOUT, 200mV/div, AC T = 100µs/div 20043475 VOUT = 10V, V IN = 5V, F = 1.25MHz 1) Load, 195mA to 385mA to 195mA 2) I L, 500mA/div, DC 3) VOUT, 500mV/div, AC T = 100µs/div LM2710 www.national.com9

Typical Performance Characteristics (Continued) Internal Soft Start Internal Soft Start 20043479 VOUT = 8V, V IN = 3V, R LOAD =2 7Ω,C SS = none, F = 600kHz 1) SHDN, 1V/div, DC 2) I L, 500mA/div, DC 3) VOUT, 5V/div, DC T = 1ms/div 20043477 VOUT = 8V, V IN = 3V, R LOAD =2 7Ω,C SS = none, F = 1.25MHz 1) SHDN, 1V/div, DC 2) I L, 500mA/div, DC 3) VOUT, 5V/div, DC T = 1ms/div External Soft Start Input Offset Voltage vs. Common Mode Voltage (3 units) 20043478 VOUT = 8V, V IN = 3V, R LOAD =2 7Ω,C SS = 330nF, F = 1.25MHz 1) SHDN, 1V/div, DC 2) I L, 500mA/div, DC 3) VOUT, 5V/div, DC T = 4ms/div 20043461 Input Offset Voltage vs. Common Mode Voltage (Over Temperature) Input Bias Current vs. Common Mode Voltage 20043462 20043463 LM2710 www.national.com 10

Typical Performance Characteristics (Continued) Output Voltage vs. Output Current (sinking) Output Voltage vs. Output Current (sourcing) 20043464 20043465 Supply Current vs. Common Mode Voltage Large Signal Step Response (50Ω, 1nF ext. compensation) 20043466 20043467 Large Signal Step Response (no ext. compensation) Positive Slew Rate vs. Capacitive Load 20043468 20043469 LM2710 www.national.com11

Typical Performance Characteristics (Continued) Negative Slew Rate vs. Capacitive Load Phase Margin vs. Capacitive Load 20043470 20043471 Unity Gain Frequency vs. Capacitive Load CMRR vs. Frequency 20043472 20043473 PSRR vs. Frequency 20043474 LM2710 www.national.com 12

lator operates in two cycles. The ratio of these two cycles determines the output voltage. 11µA current charges the external soft-start capacitor, Css. tion, the internal soft-start circuitry will override it. FIGURE 1. Simplified Boost Converter Diagram

the equation given in the Soft-Start Capacitorsection above. soft start current, 11µA, to set the soft start time. great, the circuit will be unstable above duty cycles of 50%. FIGURE 2. (a) Inductor current. (b) Diode current.

Operation (Continued) 4.7nF. Refer to the Applications Informationsection for rec- ommended values for specific circuits and conditions. Refer to the Compensation section for other design requirement. COMPENSATION FOR BOOST DC/DC This section will present a general design procedure to help insure a stable and operational circuit. The designs in this datasheet are optimized for particular requirements. If differ- ent conversions are required, some of the components may need to be changed to ensure stability. Below is a set of general guidelines in designing a stable circuit for continu- ous conduction operation, in most all cases this will provide for stability during discontinuous operation as well. The power components and their effects will be determined first, then the compensation components will be chosen to pro- duce stability. INDUCTOR AND DIODE SELECTION Although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be calculated. To ensure stability at duty cycles above 50%, the inductor must have some minimum value determined by the minimum input voltage and the maximum output voltage. This equa- tion is: where fs is the switching frequency, D is the duty cycle, and R DSON is the ON resistance of the internal switch taken from the graph "RDSON vs. VIN"i nt h eTypical Performance Char- acteristics section. This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the recommended values may be used. The corresponding in- ductor current ripple as shown in Figure 2(a) is given by: The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be the average inductor current (input current or I LOAD/D’) plus∆iL. As a side note, discontinuous operation occurs when the inductor current falls to zero during a switching cycle, or ∆i L is greater than the average inductor current. Therefore, con- tinuous conduction mode occurs when ∆iL is less than the average inductor current. Care must be taken to make sure that the switch will not reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a saturation current rating higher than the peak inductor current expected. The output voltage ripple is also affected by the total ripple current. The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output current. The typical current waveform for the diode in con- tinuous conduction mode is shown in Figure 2(b). The diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current. During short circuit testing, or if short circuit condi- tions are possible in the application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower forward voltage drop will decrease power dissipa- tion and increase efficiency. DC GAIN AND OPEN-LOOP GAIN Since the control stage of the converter forms a complete feedback loop with the power components, it forms a closed- loop system that must be stabilized to avoid positive feed- back and instability. A value for open-loop DC gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover frequency and the phase margin. A high phase margin (greater than 45˚) is desired for the best stability and transient response. For the purpose of stabilizing the LM2710, choosing a crossover point well be- low where the right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and checking the crossover using the DC gain will follow. INPUT AND OUTPUT CAPACITOR SELECTION The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is required to reduce the input ripple and noise for proper operation of the regulator. The size used is dependant on the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of the regulator is very close to the source output. The size will generally need to be larger for applications where the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value of 10µF should be used for the less stressful conditions while a 22µF to 47µF capacitor may be required for higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very low ripple on the input source voltage. The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted R ESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require more compen- sation which will be explained later on in the section. The ESR is also important because it determines the peak to peak output voltage ripple according to the approximate equation: OUT ) 2∆iLRESR (in Volts) A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output capaci- tor you can determine a pole-zero pair introduced into the control loop by the following equations: Where RL is the minimum load resistance corresponding to the maximum load current. The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the High Output Capacitor ESR Compensationsection. LM2710 www.national.com15

Operation (Continued) RIGHT HALF PLANE ZERO A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90˚ in the phase plot. This can cause undesirable effects if the control loop is influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be designed to have a bandwidth of less than 1⁄2 the frequency of the RHP zero. This zero occurs at a fre- quency of: where ILOAD is the maximum load current. SELECTING THE COMPENSATION COMPONENTS The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in the control loop. Simply choose values for RC and CC within the ranges given in the Introduction to Compensationsection to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is determined by the equation: where R O is the output impedance of the error amplifier, approximately 1MΩ. Since R C is generally much less than RO, it does not have much effect on the above equation and can be neglected until a value is chosen to set the zero f ZC. fZC is created to cancel out the pole created by the output capacitor, fP1. The output capacitor pole will shift with differ- ent load currents as shown by the equation, so setting the zero is not exact. Determine the range of f P1 over the ex- pected loads and then set the zero f ZC to a point approxi- mately in the middle. The frequency of this zero is deter- mined by: Now R C can be chosen with the selected value for C C. Check to make sure that the pole f PC is still in the 10Hz to 500Hz range, change each value slightly if needed to ensure both component values are in the recommended range. After checking the design at the end of this section, these values can be changed a little more to optimize performance if desired. This is best done in the lab on a bench, checking the load step response with different values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should produce a stable, high performance circuit. For improved transient response, higher values of R C should be chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to tran- sients. If more detail is required, or the most optimal perfor- mance is desired, refer to a more in depth discussion of compensating current mode DC/DC switching regulators. HIGH OUTPUT CAPACITOR ESR COMPENSATION When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding another capaci- tor, C C2, directly from the compensation pin VC to ground, in parallel with the series combination of R C and CC. The pole should be placed at the same frequency as f Z1, the ESR zero. The equation for this pole follows: To ensure this equation is valid, and that C C2 can be used without negatively impacting the effects of R C and CC,f PC2 must be greater than 10f ZC. CHECKING THE DESIGN The final step is to check the design. This is to ensure a bandwidth of 1⁄2 or less of the frequency of the RHP zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/ decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is less than 1⁄2 the RHP zero, the phase margin should be high enough for stability. The phase mar- gin can also be improved by adding C C2 as discussed earlier in the section. The equation for A DC is given below with additional equations required for the calculation: mc ) 0.072fs (in V/s) where RL is the minimum load resistance, V IN is the maxi- mum input voltage, g m is the error amplifier transconduc- tance found in the Electrical Characteristics table, and R D- SON is the value chosen from the graph "R DSON vs. VIN "i n the Typical Performance Characteristicssection. BUFFER (Vcom and GMAx) COMPENSATION The architecture used for the buffers in the LM2710 requires external compensation on the output. Depending on the equivalent capacitive load of the TFT-LCD panel, external components at the buffer outputs may or may not be neces- sary. If the capacitance presented by the load is equal to or greater than 5nF no external components are needed as the TFT-LCD panel will act as compensation itself. Distributed resistive and capacitive loads enhance stability and increase LM2710 www.national.com 16

Physical Dimensions inches (millimeters) unless otherwise noted TSSOP-20 Pin Package (MTC) For Ordering, Refer to Ordering Information Table LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LM2710 TFT Step-up PWM DC/DC Converter Integrated with 5 Buffers National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.