LM2702

LM2702 NSC | Alldatasheet

Document overview

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Technical content

Features

n 2A, 0.2Ω, internal power switch n VIN operating range: 2.2V to 12V n 600kHz switching frequency step-up DC/DC converter n Inrush current limiting circuitry n External softstart override n Internal 7.3Ω PMOS switch n PMOS switch control pin n PMOS switch delay pin n Vcom amplifier n Gamma buffer n 16 pin TSSOP package

Applications

Typical Application Circuit 20051131 November 2002 LM2702 TFT Panel Module © 2002 National Semiconductor Corporation DS200511 www.national.com

TJMAX = 125˚C,θJA = 120˚C/W(Note 1) Pin Description Pin Name Function 1 Vcom+ Vcom Amplifier positive input. 2 Vcom− Vcom Amplifier negative input. 3 Vcom Vcom Amplifier output. 4 Delay Switch delay. 5 Css Soft start pin. C Boost Compensation Network Connection. 7 FB Output Voltage Feedback input. 8 GND Ground. 9 SW NMOS power switch input. 10 V IN Main power input, step-up and switch circuitry. 11 SWI PMOS switch input. 12 SWO PMOS switch output. 13 SWC PMOS switch control pin. 14 AV IN Analog power input (buffers). 15 GMA Gamma buffer output. 16 GMA+ Gamma buffer input. LM2702 www.national.com 2

Vcom+(Pin 1):Positive input terminal of Vcom amplifier. Vcom−(Pin 2): Negative input terminal of Vcom amplifier. Vcom(Pin 3): Output terminal of Vcom amplifier. Delay(Pin 4):PMOS switch delay control pin. SeeOperation section for setting the delay time. The delay time begins when the output voltage of the DC/DC switching regulator reaches 85% of its true output voltage. This corresponds to a FB voltage of about 1.1V. The PMOS switch is controlled with both the delay time and the switch control pin, SWC. If no Cdelay capacitor is used, the PMOS switch is controlled solely with the SWC pin. Css(Pin 5):Softstart pin. Connect capacitor to Css pin and AGND plane to slowly ramp inductor current on startup. See Operation section for setting the softstart time. V C(Pin 6):Compensation Network for Boost switching regu- lator. Connect resistor/capacitor network between V C pin and AGND for boost switching regulator AC compensation. FB(Pin 7):Feedback pin. Set the output voltage by selecting values of R1 and R2 using: Connect the ground of the feedback network to the AGND plane, which should be tied directly to the GND pin. GND(Pin 8):Ground connect for LM2702. Connect all sen- sitive circuitry, ie. feedback resistors, softstart capacitor, de- lay capacitor, and compensation network to a dedicated AGND plane which connects directly to this pin. Connect all power ground components to a PGND plane which should also connect directly to this pin. Please see Layout Consid- erations under the Operation section for more details on layout suggestions. SW(Pin 9): This is the drain of the internal NMOS power switch. Minimize the metal trace area connected to this pin to minimize EMI. V IN(Pin 10):Input Supply Pin. Bypass this pin with a capaci- tor as close to the device as possible. The capacitor should connect between V IN and GND. SWI(Pin 11): PMOS switch input. Source connection of PMOS device. SWO(Pin 12): PMOS switch output. Drain connection of PMOS device. SWC(Pin13): PMOS switch control pin. This pin creates an AND function with the delay time after the output of the switching regulator has reached 85% of its nominal value. To ensure the PMOS switch is in the correct state, apply a voltage above 1.5V to this pin to turn on the PMOS switch and apply a voltage below 0.7V to turn off the PMOS switch. AV IN(Pin 14): Supply pin for the Vcom opamp and the Gamma buffer. Bypass this pin with a capacitor as close to the device as possible, about 100nF. The capacitor should connect between AV IN and PGND. GMA(Pin 15):Gamma Buffer output pin. GMA+(Pin 16):Gamma Buffer input pin.

Ordering Information

Order Number Package Type NSC Package Drawing Supplied As LM2702MT-ADJ TSSOP-16 MTC16 73 Units, Rail LM2702MTX-ADJ TSSOP-16 MTC16 2500 Units, Tape and Reel LM2702 www.national.com3

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Absolute Maximum Ratings(Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V IN -0.3V to 12V SW Voltage -0.3V to 18V FB Voltage -0.3V to 7V V C Voltage 0.96V to 1.56V Css Voltage -0.3V to 1.2V SWC Voltage -0.3V to 12V Supply Voltage, AV IN -0.3V to 12V Amplifier/Buffer Input/Output Voltage Rail-to-Rail Delay GND to 1.3V SWI -0.3V to 30V SWO -0.3V to 30V ESD Ratings (Notes 3, 4) Human Body Model 2kV Machine Model 200V Operating Conditions Operating Temperature −40˚C to +125˚C Storage Temperature −65˚C to +150˚C Supply Voltage, V IN 2.2V to 12V SW Voltage 17.5V Supply AV IN 4V to 12V SWI 2.2V to 30V

Electrical Characteristics

Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified, VIN =2.2V and AV IN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. Switching Regulator Symbol Parameter Conditions Min (Note 5) Typ (Note 6) Max (Note 5) Units IQ Quiescent Current Not Switching, FB = 2V 1.6 2.3 mASwitching, switch open, FB = 0.1V 2.6 5.2 VFB Feedback Voltage 1.239 1.265 1.291 V %VFB/∆VIN Feedback Voltage Line Regulation 0.01 0.1 %/V ICL Switch Current Limit (Note 7) VIN = 2.7V 1.4 2 2.6 A RDSON Switch RDSON (Note 8) V IN = 2.7V 200 m Ω IB FB Pin Bias Current (Note 9) 60 500 nA VIN Input Voltage Range 2.2 12 V ISS Soft Start Current 5 12 15 µA TSS Internal Soft Start Ramp Time 7 10 mS gm Error Amp Transconductance ∆I = 5µA 40 135 290 µmho AV Error Amp Voltage Gain 135 V/V DMAX Maximum Duty Cycle 78 85 % fS Switching Frequency 480 600 720 kHz IL Switch Leakage Current V SW = 18V 0.1 20 µA UVP On Threshold 1.79 1.92 2.05 V Off Threshold 1.69 1.82 1.95 V Hysteresis 100 mV LM2702 www.national.com5

Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified, VIN =2.2V and AV IN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. Vcom Amplifier Symbol Parameter Conditions Min (Note 5) Typ (Note 6) Max (Note 5) Units VOS Input Offset Voltage (Note 10) VCM = 1V 3.5 10 mVVCM = 7.5V 3 10 IB Input Bias Current V CM = 1V 65 200 nAVCM = 7.5V 190 300 IOS Input Offset Current V CM = 1V 45 130 nAVCM = 7.5V 5 110 CMVR Input Common-mode Voltage Range 08 V VOUT Swing R L=10k, Vo min. 0.003 .02 VRL=10k, Vo max. 7.94 7.98 RL=2k, Vo min. 0.003 .02 RL=2k, Vo max. 7.9 7.95 AVOL Large Signal Voltage Gain No Load, Vo = 2V to 7V 74.8 87.6 dBRL=10 kΩ,V o=2 Vt o7 V 66.8 75.1 RL=2 kΩ, Vo = 2V to 7V 55.8 AVIN Supply Voltage 41 2 V CMRR Common Mode Rejection Ratio VCM stepped from 0V to 1.1V 72 91.7 dBVCM stepped from 3V to 8V 80 105 VCM stepped from 0V to 8V 57 80.7 PSRR Power Supply Rejection Ratio VCM = 0.5V, AVIN =4t o1 2 V 70 77 dB Is+ Supply Current (Amplifier + Buffer) V o=A VIN/2, No Load 2.2 4 mA ISC Output Short Circuit Current Source 40 50 70 mASink 40 50 60 Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified, VIN =2.2V and AV IN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. Gamma Buffer Symbol Parameter Conditions Min (Note 5) Typ (Note 6) Max (Note 5) Units VOS Input Offset Voltage (Note 10) 11 0 m V IB Input Bias Current 170 300 nA VGR Gamma Input Voltage Range 08 V VOUT Swing R L=10k, Vo min. 0.05 0.075 VRL=10k, Vo max. 7.9 7.94 RL=2k, Vo min. 0.05 0.075 RL=2k, Vo max. 7.865 7.9 AVCL Voltage Gain No Load, Vo = 2V to 7V 0.995 0.999 V/VRL=10 kΩ,V o=2 Vt o7 V 0.995 0.999 RL=2 kΩ,V o=2 Vt o7 V 0.993 0.998 PSRR Power Supply Rejection Ratio AVIN =4t o1 2 V 70 77 dB LM2702 www.national.com 6

Electrical Characteristics (Continued) Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified, VIN =2.2V and AV IN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. Gamma Buffer Symbol Parameter Conditions Min (Note 5) Typ (Note 6) Max (Note 5) Units AVIN Supply Voltage 41 2 V Is+ Supply Current (Amplifier + Buffer) V o=A VIN/2, No Load 2.2 4 mA ISC Output Short Circuit Current Source 50 66 75 mASink 40 56 65 Specifications in standard type face are for T J = 25˚C and those with boldface typeapply over the full Operating Tempera- ture Range(T J = −40˚C to +125˚C). Unless otherwise specified, VIN =2.2V and AV IN = 8V, RCOM =R GAMMA =5 0Ω,C COM = CGAMMA = 1nF. PMOS Switch Logic Control Symbol Parameter Conditions Min (Note 5) Typ (Note 6) Max (Note 5) Units IDELAY Delay Current 5.1 5.7 6.1 µA RDSON PMOS Switch ON Resistance 7.3 20 Ω ISWO PMOS Switch Current Switch ON 20 mA ISWI PMOS Switch Input Current SWC = 0V, SWO Open, SWI = 30V 32 µASWC = 1.7V, SWO Open, SWI = 30V 118 VSWC Switch ON 1.5 1.1 VSwitch OFF 1.1 0.7 Note 1: The maximum allowable power dissipation is a function of the maximum junction temperature, T J(MAX), the junction-to-ambient thermal resistance, θJA, and the ambient temperature, T A. See the Electrical Characteristics table for the thermal resistance of various layouts. The maximum allowable power dissipation at any ambient temperature is calculated using: P D (MAX) = (T J(MAX) −T A)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Note 2: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Ch aracteristics. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k Ω resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. Note 4: Vcom pin is rated for 1.5kV Human Body Model and 150V Machine Model. Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested or guaranteed through statistical analysis. All limits at temperature extremes are guaranteed via correlation using standard St atistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 6: Typical numbers are at 25˚C and represent the most likely norm. Note 7: Duty cycle affects current limit due to ramp generator. Current limit is at 0% duty cycle and will decrease with higher duty cycles. See Typical Performance Characteristics for a graph of Power Switch Current Limit vs. V IN and Power Switch Current Limit vs. Temp. Note 8: See the graph titled "R DSON vs. VIN" for a more accurate value of the power switch R DSON. Note 9: Bias current flows into FB pin. Note 10: Refer to the graphs titled "Input Offset Voltage vs. Common Mode Voltage". LM2702 www.national.com7

Typical Performance Characteristics Efficiency vs. Load Current (VOUT = 8V) Efficiency vs. Load Current (VOUT = 10V) 20051126 20051173 Frequency vs. VIN Power Switch Current Limit vs. Temperature (VOUT = 8V) 20051125 20051120 Power Switch Current Limit vs. VIN RDSON vs. VIN (ISW = 1A) 20051122 20051127 LM2702 www.national.com 8

Typical Performance Characteristics (Continued) IQ vs. VIN (not switching) IQ vs. VIN (switching) 20051121 20051129 Feedback Current vs. Temperature Soft Start Current vs. V IN 20051163 20051164 Delay Current vs. VIN PMOS RDSON vs. SWI Voltage 20051165 20051166 LM2702 www.national.com9

Typical Performance Characteristics (Continued) SWI Current vs. SWI Voltage (PMOS ON) SWI Current vs. SWI Voltage (PMOS OFF) 20051167 20051168 Load Transient Response PMOS Switching Waveform 20051116 VOUT = 8V, V IN = 2.5V 1) Load, 20mA to 155mA to 20mA, DC 2) V OUT, 200mV/div, AC 3) IL, 500mA/div, DC T = 50µs/div 20051158 VOUT = 8V, V IN = 2.5V, R LOAD =4 0Ω,C SS = none CD = 100nF, R SW = 10k\\1.5k, SWI = 30V, 10% duty cycle 1) SWC, 1V/div, DC 2) SWO, 10V/div, DC T = 2.5µs/div PMOS Rising Edge PMOS Falling Edge 20051159 VOUT = 8V, V IN = 2.5V, R LOAD =4 0Ω,C SS = none CD = 100nF, R SW = 10k\\1.5k, SWI = 30V 1) SWC, 1V/div, DC 2) SWO, 10V/div, DC T = 50ns/div 20051160 VOUT = 8V, V IN = 2.5V, R LOAD =4 0Ω,C SS = none CD = 100nF, R SW = 10k\\1.5k, SWI = 30V 1) SWC, 1V/div, DC 2) SWO, 10V/div, DC T = 50ns/div LM2702 www.national.com 10

Typical Performance Characteristics (Continued) Internal Soft Start and PMOS Delay External Soft Start and PMOS Delay 20051161 VOUT = 8V, V IN = 2.5V, R LOAD =4 0Ω,C SS = none CD = 100nF, R SW = 10k\\1.5k, SWI = 30V, SWC = V IN 1) VIN, 2V/div, DC 2) VOUT, 10V/div, DC 3) IL, 500mA/div, DC 4) SWO, 20V/div, DC T = 5ms/div 20051162 VOUT = 8V, V IN = 2.5V, R LOAD =4 0Ω,C SS = 330nF CD = 100nF, R SW = 10k\\1.5k, SWI = 30V, SWC = V IN 1) VIN, 2V/div, DC 2) VOUT, 10V/div, DC 3) IL, 500mA/div, DC 4) SWO, 20V/div, DC T = 5ms/div Input Offset Voltage vs. Common Mode Voltage (Vcom, 3 units) Input Offset Voltage vs. Common Mode Voltage (Vcom Over Temperature) 20051174 20051175 Input Offset Voltage vs. Common Mode Voltage (Gamma, 3 units) Input Offset Voltage vs. Common Mode Voltage (Gamma Over Temperature) 20051176 20051177 LM2702 www.national.com11

Typical Performance Characteristics (Continued) Input Bias Current vs. Common Mode Voltage (Vcom) Input Bias Current vs. Common Mode Voltage (Gamma) 20051178 20051179 Output Voltage vs. Output Current (Vcom or Gamma, sinking) Output Voltage vs. Output Current (Vcom or Gamma, sourcing) 20051180 20051181 Supply Current vs. Common Mode Voltage (Both Amplifiers) Large Signal Step Response (50Ω, 1nF ext. compensation) 20051182 20051183 LM2702 www.national.com 12

Typical Performance Characteristics (Continued) Large Signal Step Response (no ext. compensation) Positive Slew Rate vs. Capacitive Load (Vcom or Gamma) 20051184 20051190 Negative Slew Rate vs. Capacitive Load (Vcom or Gamma) Phase Margin vs. Capacitive Load (Vcom) 20051185 20051186 Unity Gain Frequency vs. Capacitive Load (Vcom) CMRR vs. Frequency (Vcom) 20051187 20051188 LM2702 www.national.com13

Typical Performance Characteristics (Continued) PSRR vs. Frequency (Vcom) 20051189 LM2702 www.national.com 14

The ratio of these two cycles determines the output voltage. internal soft-start circuitry will override it. FIGURE 1. Simplified Boost Converter Diagram

the equation given in the Soft-Start Capacitorsection above. soft start current, 12µA, to set the soft start time. until a desired amount of time after the switcher starts up. The LM2702 contains a current mode PWM boost converter. great, the circuit will be unstable above duty cycles of 50%. be necessary to increase the inductance by as much as 2X. FIGURE 2. (a) Inductor current. (b) Diode current.

Operation (Continued) where R O is the output impedance of the error amplifier, approximately 1MΩ. For most applications, performance can be optimized by choosing values within the range 5k Ω≤ RC ≤ 40kΩ (RC can be up to 200k Ω if CC2 is used, see High Output Capacitor ESR Compensation) and 680pF ≤ CC ≤ 4.7nF. Refer to the Typical Application Circuit and the Appli- cations Informationsection for recommended values for spe- cific circuits and conditions. Refer to the Compensation sec- tion for other design requirement. COMPENSATION FOR BOOST DC/DC This section will present a general design procedure to help insure a stable and operational circuit. The designs in this datasheet are optimized for particular requirements. If differ- ent conversions are required, some of the components may need to be changed to ensure stability. Below is a set of general guidelines in designing a stable circuit for continu- ous conduction operation (Inductor current never reaches zero), in most all cases this will provide for stability during discontinuous operation as well. The power components and their effects will be determined first, then the compensation components will be chosen to produce stability. INDUCTOR AND DIODE SELECTION Although the inductor size mentioned earlier is fine for most applications, a more exact value can be calculated. To en- sure stability at duty cycles above 50%, the inductor must have some minimum value determined by the minimum input voltage and the maximum output voltage. This equa- tion is: where fs is the switching frequency, D is the duty cycle, and R DSON is the ON resistance of the internal switch taken from the graph "RDSON vs. VIN"i nt h eTypical Performance Char- acteristics section. This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the recommended values may be used. The corresponding in- ductor current ripple as shown in Figure 2(a) is given by: The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be the average inductor current (input current or I LOAD/D’) plus∆iL. As a side note, discontinuous operation occurs when the inductor current falls to zero during a switching cycle, or ∆i L is greater than the average inductor current. Therefore, con- tinuous conduction mode occurs when ∆iL is less than the average inductor current. Care must be taken to make sure that the switch will not reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a saturation current rating higher than the peak inductor current expected. The output and input voltage ripples are also affected by the total ripple current. The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output current. The typical current waveform for the diode in con- tinuous conduction mode is shown in Figure 2(b). The diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current. During short circuit testing, or if short circuit condi- tions are possible in the application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower forward voltage drop will decrease power dissipa- tion and increase efficiency. DC GAIN AND OPEN-LOOP GAIN Since the control stage of the converter forms a complete feedback loop with the power components, it forms a closed- loop system that must be stabilized to avoid positive feed- back and instability. A value for open-loop DC gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover frequency and the phase margin. A high phase margin (greater than 45˚) is desired for the best stability and transient response. For the purpose of stabilizing the LM2702, choosing a crossover point well be- low where the right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and checking the crossover using the DC gain will follow. INPUT AND OUTPUT CAPACITOR SELECTION The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is required to reduce the input ripple and noise for proper operation of the regulator. The size used depends on the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of the regulator is very close to the source output. The size will generally need to be larger for applications where the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value of 10µF should be used for the less stressful conditions while a 22µF to 47µF capacitor may be required for higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very low ripple on the input source voltage. The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted R ESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require more compen- sation which will be explained later on in the section. The ESR is also important because it determines the peak to peak output voltage ripple according to the approximate equation: OUT ) 2∆iLRESR (in Volts) A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output capaci- tor you can determine a pole-zero pair introduced into the control loop by the following equations: LM2702 www.national.com17

Operation (Continued) Where RL is the minimum load resistance corresponding to the maximum load current. The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the High Output Capacitor ESR Compensationsection. RIGHT HALF PLANE ZERO A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90˚ in the phase plot. This can cause undesirable effects if the control loop is influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be designed to have a bandwidth of less than 1⁄2 the frequency of the RHP zero. This zero occurs at a fre- quency of: where ILOAD is the maximum load current. SELECTING THE COMPENSATION COMPONENTS The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in the control loop. Simply choose values for RC and CC within the ranges given in the Introduction to Compensationsection to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is determined by the equation: where R O is the output impedance of the error amplifier, approximately 1MΩ. Since R C is generally much less than RO, it does not have much effect on the above equation and can be neglected until a value is chosen to set the zero f ZC. fZC is created to cancel out the pole created by the output capacitor, fP1. The output capacitor pole will shift with differ- ent load currents as shown by the equation, so setting the zero is not exact. Determine the range of f P1 over the ex- pected loads and then set the zero f ZC to a point approxi- mately in the middle. The frequency of this zero is deter- mined by: Now R C can be chosen with the selected value for C C. Check to make sure that the pole f PC is still in the 10Hz to 500Hz range, change each value slightly if needed to ensure both component values are in the recommended range. After checking the design at the end of this section, these values can be changed a little more to optimize performance if desired. This is best done in the lab on a bench, checking the load step response with different values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should produce a stable, high performance circuit. For improved transient response, higher values of R C should be chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to tran- sients. If more detail is required, or the most optimal perfor- mance is desired, refer to a more in depth discussion of compensating current mode DC/DC switching regulators. HIGH OUTPUT CAPACITOR ESR COMPENSATION When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding another capaci- tor, C C2, directly from the compensation pin VC to ground, in parallel with the series combination of R C and CC. The pole should be placed at the same frequency as f Z1, the ESR zero. The equation for this pole follows: To ensure this equation is valid, and that C C2 can be used without negatively impacting the effects of R C and CC,f PC2 must be greater than 10f ZC. CHECKING THE DESIGN The final step is to check the design. This is to ensure a bandwidth of 1⁄2 or less of the frequency of the RHP zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the crossover fre- quency. If the crossover frequency is less than 1⁄2 the RHP zero, the phase margin should be high enough for stability. The phase margin can also be improved by adding C C2 as discussed earlier in the section. The equation for A DC is given below with additional equations required for the calcu- lation: mc ) 0.181fs (in V/s) where RL is the minimum load resistance, V IN is the mini- mum input voltage, g m is the error amplifier transconduc- tance found in the Electrical Characteristics table, and R D- SON is the value chosen from the graph "R DSON vs. VIN "i n the Typical Performance Characteristicssection. LM2702 www.national.com 18

CGAMMA) capacitor from the output of the amplifier to ground. good performance for all conditions. trace connections that can inject noise into the system. FIGURE 3. Multi-Layer Layout

Physical Dimensions inches (millimeters) unless otherwise noted TSSOP-16 Pin Package (MTC) For Ordering, Refer to Ordering Information Table LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com LM2702 TFT Panel Module National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.