LM2611 TI1 | Alldatasheet
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C IN: TAIYO YUDEN X5R JMK325BJ226MM C CUK : TAIYO YUDEN X5R EMK316BJ105MF C OUT : TAIYO YUDEN X5R JMK325BJ226MM D: ON SEMICONDUCTOR MBR0520 L1: SUMIDA CR32-150 L2: SUMIDA CR32-470 C CUK 1 PF C OUT 22 PF 47 PH VIN D C FF 330 pF R FB1 29.4k R FB2 10k VIN SW NFB GND SHDN LM2611A C IN 22 PF 15 PH VOUT - 5V 300 mA Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LM2611 SNOS965J –JUNE 2001–REVISED DECEMBER 2015 LM26111.4-MHzCukConverter
1 Features 3 Description
The LM2611 is a current mode, PWM inverting 1• 1.4-MHz Switching Frequency switching regulator. Operating from a 2.7-V to 4-V• Low RDS(ON) DMOS FET supply, it is capable of producing a regulated
- 1-mVp-p Output Ripple negative output voltage of up to −(36 VIN(MAX)). The LM2611 utilizes an input and output inductor, which• −5 V at 300 mA From 5-V Input enables low voltage ripple and RMS current on both• Better Regulation Than a Charge Pump the input and the output. With a switching frequency• Uses Tiny Capacitors and Inductors of 1.4 MHz, the inductors and output capacitor can be physically small and low cost. High efficiency is• Wide Input Range: 2.7 V to 14 V achieved through the use of a low RDS(ON) FET.• Low Shutdown Current: <1 µA The LM2611 features a shutdown pin, which can be• 5-Pin SOT-23 Package activated when the part is not needed to lower the Iq and save battery life. A negative feedback (NFB) pin2 Applications provides a simple method of setting the output• MR Head Bias voltage, using just two resistors. Cycle-by-cycle
- Digital Camera CCD Bias current limiting and internal compensation further simplify the use of the LM2611.• LCD Bias The LM2611 is available as a small 5-pin, SOT-23• GaAs FET Bias package and comes in two grades. Grade A has a• Positive to Negative Conversion 1.2-A current limit and 0.5-Ω RDS(ON), and Grade B has a 0.9-A current limit and 0.7-Ω RDS(ON). Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM2611 SOT-23 (5) 1.60 mm × 2.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNOS965J –JUNE 2001–REVISED DECEMBER 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (April 2013) to Revision J Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision H (April 2013) to Revision I Page
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Product Folder Links: LM2611
5 VIN
4 SHDN
www.ti.com SNOS965J –JUNE 2001–REVISED DECEMBER 2015
5 Pin Configuration and Functions
TYPE(1) DESCRIPTION NO. NAME 1 SW A Drain of internal switch. Connect at the node of the input inductor and Cuk capacitor. 2 GND GND Analog and power ground. 3 NFB A Negative feedback. Connect to output via external resistor divider to set output voltage. 4 SHDN I Shutdown control input. VIN = Device on. Ground = Device in shutdown. Analog and power input. Filter out high frequency noise with a 0.1-µF ceramic capacitor5 VIN PWR placed close to the pin. (1) A = Analog, I = Input, GND = Ground, PWR = Power
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage, VIN 14.5 V SW voltage –0.4 36 V NFB voltage –6 0.4 V SHDN voltage –0.4 14.5 V Maximum junction temperature 125 °C Power dissipation (2) Internally limited Lead temperature 300 °C Storage temperature, Tstg −65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance of various layouts. The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000 V(ESD) Electrostatic discharge V Machine Model (MM)(3) ±200 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. (3) The machine model is a 200-pF capacitor discharged directly into each pin. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM2611
SNOS965J –JUNE 2001–REVISED DECEMBER 2015 www.ti.com
6.3 Recommended Operating Conditions
Supply voltage 2.7 14 V Operating junction temperature, TJ −40 125 °C
6.4 Thermal Information
THERMAL METRIC(1) DBV (SOT-23) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 163.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 115.2 °C/W RθJB Junction-to-board thermal resistance 27.4 °C/W ψJT Junction-to-top characterization parameter 12.9 °C/W ψJB Junction-to-board characterization parameter 26.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
Specifications in standard type face are for TJ = 25°C, unless otherwise specified. VIN = 5 V and IL = 0 A, unless otherwise specified. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT VIN Input voltage TJ = −40°C to +85°C 2.7 14 V Grade A 1.2 Grade A; TJ = −40°C to +85°C 1 2 ISW Switch current limit A Grade B 0.9 Grade B; TJ = −40°C to +85°C 0.7 Grade A 0.5 0.65 RDSON Switch ON resistance Ω Grade B 0.7 0.9 Device enabled; TJ = −40°C to +85°C 1.5 SHDNTH Shutdown threshold V Device disabled; TJ = −40°C to +85°C 0.5 VSHDN = 0 V 0 ISHDN Shutdown pin bias current VSHDN = 5 V 0 µA VSHDN = 5 V; TJ = −40°C to +85°C 1 VIN = 3 V −1.23 NFB Negative feedback reference V VIN = 3 V; TJ = −40°C to +85°C −1.205 −1.255 VNFB =−1.23 V −4.7 INFB NFB pin bias current µA VNFB =−1.23 V; TJ = −40°C to +85°C −2.7 −6.7 VSHDN = 5 V, Switching 1.8 mAVSHDN = 5 V, Switching; 3.5TJ = −40°C to +85°C VSHDN = 5 V, Not Switching 270 Iq Quiescent current µAVSHDN = 5 V, Not Switching; 500TJ = −40°C to +85°C VSHDN = 0 V 0.024 µA VSHDN = 0 V; TJ = −40°C to +85°C 1 %VOUT/ Reference line regulation 2.7 V ≤ VIN ≤ 14 V 0.02 %/VΔVIN (1) All limits are specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% tested through statistical analysis. All limits at temperature extremes via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). (2) Typical numbers are at 25°C and represent the expected value of the parameter.
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www.ti.com SNOS965J –JUNE 2001–REVISED DECEMBER 2015 Electrical Characteristics (continued) Specifications in standard type face are for TJ = 25°C, unless otherwise specified. VIN = 5 V and IL = 0 A, unless otherwise specified. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT TJ = 25°C 1.4 fS Switching frequency MHz TJ = −40°C to +85°C 1 1.8 TJ = 25°C 88% DMAX Maximum duty cycle TJ = −40°C to +85°C 82% IL Switch leakage VSW = 5 V, Not Switching 1 µA Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM2611
6.6 Typical Characteristics
Figure 1. RDS(ON) vs VIN Figure 2. RDS(ON) vs Ambient Temperature Figure 4. Switch Current Limit vs Ambient TemperatureFigure 3. Switch Current Limit vs VIN Figure 5. Oscillator Frequency vs VIN Figure 6. Oscillator Frequency vs Ambient Temperature
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2 GND
3 NFB
7 Detailed Description
7.1 Overview
designed to shut down the converter.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Cuk Converter
Figure 13. Operating Cycles of a Cuk Converter current ripple. This is a significant advantage over other inverting topologies such as the buck-boost and flyback.
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The following sections review the steady-state design of the LM2611 Cuk converter.
7.3.2 Output and Input Inductor
Figure 14 and Figure 15 show the steady-state voltage and current waveforms for L1 and L2, respectively. Figure 14. Voltage and Current Waveforms in Inductor L1 of a Cuk Converter when the switch is closed, VIN is applied across L2. When the switch opens, VOUT is applied across L2. Figure 15. Schematic of the Cuk Converter Using LM2611
compensation assumes L1 and L2 are equal to 10 to 22 µH, thus TI recommends staying within this range.
7.3.3 Switch Current Limit
limit. If at any time the switch current surpasses the current limit, the switch opens until the next switching period. LM2611 device's 5-pin, SOT-23 package (θJA = 265°C/W). Figure 16. Switch Current Waveform in a Cuk Converter.
7.3.4 Input Capacitor
smaller, the input ripple goes up. The RMS current in the input capacitor is shown in Equation 7. IC. This capacitor must be connected very close to pin 5 (within 0.2 inches).
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p FF FB1 FB2 R1 1 (rad / s)C R R /c230 /c246/c119 /c61 /c43 /c231 /c247 /c232 /c248 Z FF FB1 1 (rad / s)C R/c119 /c61 ESR OUT 1f (Hz) 2 C ESR/c61 /c112 L2 IN COUT(RMS) i s 2 o i V 1I 3 2 3 Vf L 1 V /c68/c61 /c61 /c230 /c246 /c43/c231 /c247 /c231 /c247 /c232 /c248 LM2611 www.ti.com SNOS965J –JUNE 2001–REVISED DECEMBER 2015 Feature Description (continued)
7.3.5 Output Capacitor
Like the input current, the output current is also continuous, triangular, and has low ripple (see IL2 in Figure 15). The output capacitor must be rated to handle its RMS current: (8) For example, ICOUT(RMS) can range from 30 mA to 180 mA with 10 µH ≤ L1,2 ≤ 22 µH, −10 V ≤ VOUT ≤ −3.3 V, and 2.7 V ≤ VIN ≤ 30 V (VIN may be 30 V if using separate power and analog supplies, see Split Supply Operation in the Typical Application section). The worst case conditions are with L1,2, VOUT(MAX), and VIN(MAX). Many capacitor technologies will provide this level of RMS current, but ceramic capacitors are ideally suited for the LM2611. Ceramic capacitors provide a good combination of capacitance and equivalent series resistance (ESR) to keep the zero formed by the capacitance and ESR at high frequencies. Use Equation 9 to calculate the ESR zero. (9) A general rule of thumb is to keep fESR > 80 kHz for LM2611 Cuk designs. Low ESR tantalum capacitors will usually be rated for at least 180 mA in a voltage rating of 10 V or above. However the ESR in a tantalum capacitor (even in a low ESR tantalum capacitor) is much higher than in a ceramic capacitor and could place fESR low enough to cause the LM2611 to become unstable.
7.3.6 Improving Transient Response and Compensation
The compensator in the LM2611 is internal. However, a zero-pole pair can be added to the open-loop frequency response by inserting a feed-forward capacitor, CFF, in parallel to the top feedback resistor (RFB1). Phase margin and bandwidth can be improved with the added zero-pole pair. This in turn improves the transient response to a step load change (see Figure 17 and Figure 18). The position of the zero-pole pair is a function of the feedback resistors and the capacitor value: (10) (11) The optimal position for this zero-pole pair will vary with circuit parameters such as D, IOUT, COUT, L1, L2, and CCUK. For most cases, the value for the zero frequency is between 5 kHz to 20 kHz. Notice how the pole position, ωp, is dependant on the feedback resistors RFB1 and RFB2, and therefore also dependant on the output voltage. As the output voltage becomes closer to −1.26 V, the pole moves towards the zero, tending to cancel it out. If the absolute magnitude of the output voltage is less than 3.3 V, adding the zero-pole pair will not have much effect on the response. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM2611
Figure 17. 130-mA to 400-mA Transient Response Figure 18. 130-mA to 400-mA Transient Response
7.4 Device Functional Modes
7.4.1 Hysteretic Mode
LM2611 in pulse-skipping mode at low loads. In this mode, the output ripple increases slightly. Figure 19. PWM Mode Figure 20. Pulse-Skipping Mode
7.4.1.1 Thermal Shutdown
junction temperature to drop from 163°C to 155°C with the switch off.
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
the components for the target application and shows some typical examples of applications to help the designer.
8.2 Typical Application
8.2.1 Cuk Converter With Integrated Switch
Figure 21. Typical Cuk Converter Implementation Using LM26211
8.2.1.1 Design Requirements
range ensures that the IC is suitable for the application and that the absolute maximum voltage are respected. The expected maximum output current is also needed to verify that the IC can deliver the required current.
8.2.1.2 Detailed Design Procedure
footprint and lower cost but the higher ripple makes a smaller inductance not compatible with every application. the peak-to-peak ripple is lower than 0.3 A of the average current by using Equation 3 and Equation 5. inductance is within the recommended range). Using the desired output voltage, calculate the value of the feedback resistors. The reference voltage is 1.23 V. Resistors of 50 kΩ or less must be used due to the leakage at the NFB pin.
key to ensure ideal sizing of the capacitor (either using load transient response or a loop response analyzer). See Improving Transient Response and Compensation for details regarding the CFF capacitor.
8.2.1.3 Application Curves
Figure 22. Maximum Output Current vs Output Voltage at Figure 23. Maximum Output Current vs Output Voltage at Figure 24. 5-V to –5-V Inverting Converter Schematic
8.2.2.1 Design Requirements
This design converts 5 V (VIN) to –5 V (VOUT). Adjust RFB2 to set a different output voltage.
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10 PHVIN
10 PH VOUT - 5V
8.2.2.2 Application Curves
Figure 25. Efficiency vs Load Current Figure 26. Maximum Output Current vs Output Voltage, 5 Figure 27. 9-V to –5-V Inverting Converter Schematic
8.2.3.1 Design Requirements
This design converts 9 V (VIN) to –5 V (VOUT). Adjust RFB2 to set a different output voltage.
22 PHVIN
22 PH VOUT - 5V
8.2.3.2 Application Curve
Figure 28. Maximum Output Current vs Output Voltage, 9 V to – 5 V Figure 29. 12-V to –5-V Inverting Converter Schematic
8.2.4.1 Design Requirements
This design converts 12 V (VIN) to –5 V (VOUT). Adjust RFB2 to set a different output voltage.
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8.2.4.2 Application Curve
Figure 30. Maximum Output Current vs Output Voltage, 12 V to –5 V
8.2.5 LM2611 Operating With Separate Power and Biasing Supplies
Figure 31. LM2611 Operating With Separate Power and Biasing Supplies Schematic
8.2.5.1 Design Requirements
Follow the design requirements in Cuk Converter With Integrated Switch.
8.2.5.2 Detailed Design Procedure
8.2.5.2.1 Split Supply Operation
2.7 V ≤ VDD ≤ 14 V (12)
0 V ≤ VIN ≤ (36 - IVOUTI) V (13)
single supply that is limited in voltage by VIN(MAX).
8.2.6 Shutdown and Soft-Start
Figure 32. LM2611 Soft-Start Circuit
8.2.6.1 Design Requirements
Follow the design requirements in Cuk Converter With Integrated Switch.
8.2.6.2 Detailed Design Procedure
8.2.6.2.1 Shutdown and Soft-Start
LM2611 is toggled between shutdown and run states while the output slowly decreases to its steady-state value. (see Figure 33 and Figure 34).
8.2.6.3 Application Curves
Figure 34. Start-Up Waveforms Without a Soft-Start CircuitFigure 33. Start-Up Waveforms With a Soft-Start Circuit
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8.2.7 High Duty Cycle and Load Current
Figure 35. LM2611 High Current Schematic
8.2.7.1 Design Requirements
Follow the design requirements in Cuk Converter With Integrated Switch.
8.2.7.2 Detailed Design Procedure
8.2.7.2.1 High Duty Cycle and Load Current Operation
necessary to stabilize the circuit under the combination of high duty cycle and high load currents.
9 Power Supply Recommendations
transients at the VIN pin, each time the input supply is cycled on and off.
10 Layout
10.1 Layout Guidelines
- Connection between L1 and SW pin should be kept as short as possible to minimize inductance
- Connection between CCUK and SW should also be kept short
- The feedback resistor should be placed close to the NFB pin to minimize the path of the higher impedance feedback node
- The feedback trace leading from Vout to the output to the feedback resistors should not pass under the switch node between L1 and CCUK and the switch node between CCUK, L2 and D
- The feedback trace leading from Vout to the output to the feedback resistors should not pass under the inductors L1 and L2
- A bypass capacitor CBYP of 0.1 µF should be placed close to VIN and GND pin
10.2 Layout Example
Figure 36. Example Layout Top Figure 37. Example Layout Bottom
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LM2611
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