LM26003 TI | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community LM26003,LM26003-Q1 SNVS576F –AUGUST 2008–REVISED FEBRUARY 2015 LM26003-xx3-ASwitchingRegulatorWithHighEfficiencySleepMode
1 Features 3 Description
The LM26003 is a switching regulator designed for 1• LM26003-Q1 is an Automotive-Grade Product the high-efficiency requirements of applications withThat is AEC-Q100 Grade 1 Qualified (–40°C to standby modes. The device features a low-current+125°C Operating Junction Temperature) sleep mode to maintain efficiency under light-load
- High-Efficiency Sleep Mode conditions and current-mode control for accurate regulation over a wide input voltage range. Quiescent• 40-µA Typical Iq in Sleep Mode
- 4.0-V to 38-V Continuous Input Range The LM26003 device can deliver up to 3 A of• 1.5% Reference Accuracy continuous load current with a fixed current limit,
- Cycle-by-Cycle Current Limit through the internal N-channel switch. The part has a wide input voltage range of 4.0 V to 38 V and can• Adjustable Frequency (150 kHz to 500 kHz) operate with input voltages as low as 3 V during line• Synchronizable to an External Clock transients.
- Power Good Flag Operating frequency is adjustable from 150 kHz to• Forced PWM Function 500 kHz with a single resistor and can be
- Adjustable Soft-Start synchronized to an external clock.
- 20-Pin HTSSOP Package Other features include Power Good, adjustable soft-
- Thermal Shut Down start, enable pin, input undervoltage protection, and an internal bootstrap diode for reduced component count.2 Applications
- Automotive Telematics Device Information(1)
- Navigation Systems PART NUMBER PACKAGE BODY SIZE (NOM)
- In-Dash Instrumentation LM26003 HTSSOP (20) 6.50 mm x 4.40 mm• Battery-Powered Applications LM26003-Q1
- Standby Power for Home Gateways and Set-Top (1) For all available packages, see the orderable addendum at Boxes the end of the datasheet.
4 Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM26003,LM26003-Q1 SNVS576F –AUGUST 2008–REVISED FEBRUARY 2015 www.ti.com Table of Contents
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (December 2014) to Revision F Page Changes from Revision D (March 2013) to Revision E Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision C (March 2013) to Revision D Page
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15 VBIAS
16 VDD
17 BOOT
11 PGND
13 FPWM
12 FREQ
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6 Pin Configuration and Functions
NAME NO. VIN 1 I Power supply input for high side FET VIN 2 I Power supply input for high side FET VIN 3 I Power supply input for high side FET AVIN 4 I Power supply input for IC supply PGOOD 5 O Power Good pin. An open-drain output which goes high when the output voltage is greater than 92% of nominal. EN 6 I Enable is an analog level input pin. When pulled below 0.8 V, the device enters shutdown mode. SS 7 I Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time. COMP 8 I Compensation pin. Connect to a resistor capacitor pair to compensate the control loop. FB 9 I Feedback pin. Connect to a resistor divider between VOUT and GND to set output voltage. AGND 10 GND Analog GND as IC reference PGND 11 GND Power GND is GND for the switching stage of the regulator FREQ 12 O Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency. FPWM 13 I FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation is disabled. SYNC 14 I Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be pulled low for non-synchronized operation. VBIAS 15 I Connect to an external 3-V or greater supply to bypass the internal regulator for improved efficiency. If not used, VBIAS should be tied to GND. VDD 16 O The output of the internal regulator. Bypass with a minimum 1.0-µF capacitor. BOOT 17 I Bootstrap capacitor pin. Connect a 0.1-µF minimum ceramic capacitor from this pin to SW to generate the gate drive bootstrap voltage. SW 18 O Switch pin. The source of the internal N-channel switch. SW 19 O Switch pin. The source of the internal N-channel switch. SW 20 O Switch pin. The source of the internal N-channel switch. EP EP GND Exposed Pad thermal connection. Connect to GND. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM26003 LM26003-Q1
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)(2) MIN MAX UNIT VIN –0.3 40 V SW –1 40 V VDD –0.3 7 V VBIAS –0.3 10 V FB -0.3 7 VVoltages from the indicated BOOT VSW-0.3 VSW+7 V pins to GND PGOOD –0.3 7 V FREQ –0.3 7 V SYNC –0.3 7 V EN –0.3 40 V FPWM –0.3 7 V Power Dissipation 3.1 W Recommended Vapor Phase (70s) 215 °C Lead Temperature Infrared (15s) 220 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
7.2 ESD Ratings: LM26003
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all ±1000V(ESD) Electrostatic discharge Vpins(2) Charged machine model ±200000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings: LM26003-Q1
Human body model (HBM), per AEC Q100-002(1) ±2000 Corner pins (1, 10, 11, and 20) ±1000Charged device model (CDM), perV(ESD) Electrostatic discharge VAEC Q100-011 Other pins ±1000 Charged machine model ±200 (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.4 Recommended Operating Conditions
Operating Junction Temperature −40 125 °C Supply Voltage 3.0 38 V
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7.5 Thermal Information
LM26003, LM26003-Q1 THERMAL METRIC(1) UNITPWP
20 PINS
RθJA Junction-to-ambient thermal resistance 25.4 RθJC(top) Junction-to-case (top) thermal resistance 19.6 RθJB Junction-to-board thermal resistance 16.5 °C/W ψJT Junction-to-top characterization parameter 0.5 ψJB Junction-to-board characterization parameter 16.3 RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.6 Electrical Characteristics
Unless otherwise stated, Vin = 12 V, TJ = 25°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT SYSTEM ISD (2) Shutdown Current EN = 0 V 10.8 µA EN = 0 V, –40°C ≤ TJ ≤ 125°C 20 IqSleep_VB (2) Quiescent Current Sleep mode, VBIAS = 5 V 40 µA Sleep mode, VBIAS = 5 V, 70 –40°C ≤ TJ ≤ 125°C IqSleep_VDD Quiescent Current Sleep mode, VBIAS = GND 76 µA Sleep mode, VBIAS = GND, 125 –40°C ≤ TJ ≤ 125°C IqPWM_VB Quiescent Current PWM mode, VBIAS = 5 V 0.16 0.23 mA FPWM = 2 V IqPWM_VDD Quiescent Current PWM mode, VBIAS = GND 0.65 0.85 mA FPWM = 2 V IBIAS_Sleep (2) Bias Current Sleep mode, VBIAS = 5 V 33 µA Sleep mode, VBIAS = 5 V, 60 –40°C ≤ TJ ≤ 125°C IBIAS_PWM Bias Current PWM mode, VBIAS = 5 V 0.5 0.7 mA VFB Feedback Voltage 5 V < Vin < 38 V 1.236 V 5 V < Vin < 38 V, –40°C ≤ TJ ≤ 1.217 1.255 125°C IFB FB Bias Current VFB = 1.20 V ±200 nA ΔVOUT/ΔVIN Output Voltage Line Regulation 5 V < Vin < 38 V 0.00025 %/V ΔVOUT/ΔIOUT Output Voltage Load Regulation 0.8 V < VCOMP < 1.15 V 0.08 %/A VDD VDD Pin Output Voltage 7 V < Vin < 35 V, IVDD= 0 mA to 5.99 V 5 mA 7 V < Vin < 35 V, IVDD= 0 mA to 5.50 6.50 5 mA, –40°C ≤ TJ ≤ 125°C ISS_Source Soft-start Source Current 2.5 µA Vbias_th VBIAS On Voltage Specified at IBIAS = 92.5% of full 2.64 2.9 3.07 V value (1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). (2) Iq and ISD specify the current into the VIN and AVIN pins. IBIAS is the current into the VBIAS pin when the VBIAS voltage is greater than 3 V. All quiescent current specifications apply to non-switching operation. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM26003 LM26003-Q1
LM26003,LM26003-Q1 SNVS576F –AUGUST 2008–REVISED FEBRUARY 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise stated, Vin = 12 V, TJ = 25°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT PROTECTION ILIMPK Peak Current Limit 4.7 A –40°C ≤ TJ ≤ 125°C 3.15 6.05 VFB_SC Short Circuit Frequency Foldback Measured at FB falling 0.87 V Threshold F_min_sc Min Frequency in Foldback VFB < 0.3 V 45 kHz VTH_PGOOD Power Good Threshold Measured at FB, PGOOD rising 92% Measured at FB, PGOOD rising, 89% 95% –40°C ≤ TJ ≤ 125°C PGOOD Hysteresis 2% 6% 8% IPGOOD_HI PGOOD Leakage Current PGOOD = 5 V 1.25 nA RDS_PGOOD PGOOD On Resistance PGOOD sink current = 500 µA 150 Ω VUVLO Under-voltage Lock-Out Threshold Vin falling , shutdown, VDD = 2.96 V VIN Vin falling , shutdown, VDD = 2.70 3.30 VIN, –40°C ≤ TJ ≤ 125°C Vin rising, soft-start, VDD = VIN 3.99 Vin rising, soft-start, VDD = VIN, 3.70 4.30 –40°C ≤ TJ ≤ 125°C TSD Thermal Shutdown Threshold 160 °C θJA Thermal Resistance Power dissipation = 1W, 0 lfpm 32 °C/W air flow LOGIC VthEN Enable Threshold Voltage Enable rising 1.18 V Enable rising, –40°C ≤ TJ ≤ 0.8 1.4 125°C Enable Hysteresis 180 mV IEN_Source EN Source Current EN = 0 V 4.85 µA VTH_FPWM FPWM Threshold 1.24 V IFPWM FPWM Leakage Current FPWM = 5 V 3 nA EA gm Error Amp Trans-conductance 675 µmho –40°C ≤ TJ ≤ 125°C 400 1000 ICOMP COMP Source Current VCOMP = 0.9 V 57 µA COMP Sink Current VCOMP = 0.9 V 57 µA VCOMP COMP Pin Voltage Range 0.64 1.27 V
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7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Isw = 2A 0.095 RDS(ON) Switch On Resistance Ω Isw = 2A, –40°C ≤ TJ ≤ 125°C 0.040 0.200 Vin = 38 V, VSW = 0 V 0.002 Isw_off Switch Off State Leakage Current μAVin = 38 V, VSW = 0 V, –40°C ≤ TJ 5.0 ≤ 125°C RFREQ = 62k, 124k, 240k, –40°C ≤ ±10%fsw Switching Frequency TJ ≤ 125°C VFREQ FREQ Voltage 1.0 V fSW range Switching Frequency Range –40°C ≤ TJ ≤ 125°C 150 500 kHz SYNC rising 1.23 SYNC rising, –40°C ≤ TJ ≤ 125°C 1.6 Sync Pin Threshold V VSYNC SYNC falling 1.10 SYNC falling, –40°C ≤ TJ ≤ 125°C 0.8 Sync Pin Hysteresis 135 mV ISYNC SYNC Leakage Current 2 nA Upper Frequency Synchronization As compared to nominal fSW, –40°C +30%FSYNC_UP Range ≤ TJ ≤ 125°C Lower Frequency Synchronization As compared to nominal fSW, –40°C –20%FSYNC_DN Range ≤ TJ ≤ 125°C TOFFMIN Minimum Off-time 300 ns TONMIN Minimum On-time 190 ns THSLEEP_HYS Sleep Mode Threshold Hysteresis VFB rising, % of THWAKE 101.3% Measured at falling FB, COMP = 0.6 1.236THWAKE Wake Up Threshold VV BOOT = 6 V, SW = GND 0.001 IBOOT BOOT Pin Leakage Current μABOOT = 6 V, SW = GND, –40°C ≤ 5.0 TJ ≤ 125°C Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM26003 LM26003-Q1
7.8 Typical Characteristics
Unless otherwise specified the following conditions apply: Vin = 12 V, TJ = 25°C. Figure 1. Efficiency vs Load Current (300 kHz) Figure 2. Efficiency vs Load Current (500 kHz) Figure 3. VFB vs Temperature Figure 4. VFB vs Vin (IDC = 300 mA) Figure 5. IQ and IVBIAS vs Temperature (Sleep Mode) Figure 6. IQ and IVBIAS vs Temperature (PWM Mode)
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8 Detailed Description
8.1 Overview
PWM waveforms are shown in Figure 10. Figure 10. PWM Waveforms 1A-Load, Vin = 12 V
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 FPWM
Figure 11. Discontinuous Mode Waveforms 75-mA Load, Vin = 12 V condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation.
8.3.2 Soft-Start
- tss is the desired soft-start time
- Iss is the soft-start source current. (1) During soft-start, current limit and synchronization remain in effect, while sleep mode and frequency foldback are disabled. Soft-start mode ends when the SS pin voltage reaches 1.23 V typical. At this point, output voltage control is transferred to the FB pin and the SS pin is discharged.
8.3.3 Current Limit
Typical Characteristics section. increased to slow the current ramp and reduce the peak overcurrent.
8.3.4 Frequency Adjustment and Synchronization
Figure 12. Switching Frequency vs RFREQ
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Sync_Dmin /c741 - fnom fsync LM26003,LM26003-Q1 www.ti.com SNVS576F –AUGUST 2008–REVISED FEBRUARY 2015 Feature Description (continued) The switching frequency can also be synchronized to an external clock signal using the SYNC pin. The SYNC pin allows the operating frequency to be varied above and below the nominal frequency setting. The adjustment range is from 30% above nominal to 20% below nominal. External synchronization requires a 1.23-V minimum (typical) peak signal level at the SYNC pin. The FREQ resistor must always be connected to initialize the nominal operating frequency. The operating frequency is synchronized to the falling edge of the SYNC input. When SYNC goes low, the high-side switch turns on. This allows any duty-cycle to be used for the sync signal when synchronizing to a frequency higher than nominal. When synchronizing to a lower frequency, however, there is a minimum duty-cycle requirement for the SYNC signal, given in the equation below: where
- fnom is the nominal switching frequency set by the FREQ resistor
- fsync is a square wave. (5) If the SYNC pin is not used, it must be pulled low for normal operation. A 10 kΩ pulldown resistor is recommended to protect against a missing sync signal. Although the LM26003 device is designed to operate at up to 500 kHz, maximum load current may be limited at higher frequencies due to increased temperature rise. See the Thermal Considerations and TSD section.
8.3.5 VBIAS
The VBIAS pin is used to bypass the internal regulator which provides the bias voltage to the LM26003 device. When the VBIAS pin is connected to a voltage greater than 3 V, the internal regulator automatically switches over to the VBIAS input. This reduces the current into VIN (Iq) and increases system efficiency. Using the VBIAS pin has the added benefit of reducing power dissipation within the device. For most applications where 3 V < Vout < 10 V, VBIAS can be connected to VOUT. If not used, VBIAS should be tied to GND. If VBIAS drops below 2.9 V (typical), the device automatically switches over to supply the internal bias voltage from Vin. When the LM26003 device is powered with the circuit's output voltage through VBIAS, especially at low output voltages such as 3.3 V, output ripple noise can couple in through the Vbias pin causing some falling edge jitter on the switch node. To avoid this, additional bypassing close to the VBIAS pin with a low ESR capacitor can be implemented. The circuit diagram in Figure 16 shows this bypass capacitor C8.
8.3.6 Low VIN Operation and UVLO
The LM26003 device is designed to remain operational during short line transients when the input voltage may drop as low as 3.0 V. Minimum nominal operating input voltage is 4.0 V. Below this voltage, switch RDS(ON) increases, due to the lower gate drive voltage from VDD. The minimum voltage required at VDD is approximately 3.5 V for normal operation within specification. VDD can also be used as a pullup voltage for functions such as PGOOD and FPWM. Note that if VDD is used externally, the pin is not recommended for loads greater than 1 mA. If the input voltage approaches the nominal output voltage, the duty-cycle is maximized to hold up the output voltage. In this mode of operation, once the duty-cycle reaches its maximum, the LM26003 device can skip a maximum of seven off pulses, effectively increasing the duty-cycle and thus minimizing the dropout from input to output. Typical off-pulse skipping waveforms are shown in Figure 13. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LM26003 LM26003-Q1
Figure 13. Off-Pulse Skipping Waveforms Vin = 3.5 V, Vnom = 3.3 V, fnom = 305 kHz holding up VDD, a larger cap can also reduce the RDS(ON) (and dropout voltage) in low VIN conditions. may be triggered by VDD even though the VIN voltage is above the UVLO threshold. voltage and VDD voltage rise above 3.99 V (typical) the device will restart from soft-start mode.
8.3.7 PGOOD
improved noise immunity, there is a 5-µs delay between the PGOOD threshold and the PGOOD pin going low.
8.4 Device Functional Modes
The LM26003 device has three basic operation modes: shutdown, sleep or light load operation and full operation. quiescent current is minimized. See the Enable section for more details. for details about operating in Sleep mode as well as entering and exiting sleep mode. operating frequency to protect from short circuits. See Current Limit for more details.
8.4.1 Enable
this pin can be left open for always-on operation. When open, EN will be pulled up to VIN.
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driven externally with a maximum voltage of 38 V or VIN + 15 V, whichever is lower.
8.4.2 Sleep Mode
shows typical switching and output voltage waveforms in sleep mode. Figure 14. Sleep Mode Waveforms 25-mA Load, Vin = 12 V
- Imin = Ilim/16 (4.7A/16 typically)
- D = duty-cycle, defined as (Vout + Vdiode)/Vin. (6) When load current increases above this limit, the LM26003 device is forced back into PWM operation. The sleep mode threshold varies with frequency, inductance, and duty-cycle as shown in Figure 15.
Figure 15. Sleep Mode Threshold vs Vin Vout = 3.3 V
LM26003,LM26003-Q1 SNVS576F –AUGUST 2008–REVISED FEBRUARY 2015 www.ti.com Device Functional Modes (continued) Dwake = Iload/Isleep where
- Dwake is the percentage of time awake when the load current is below the sleep threshold. (7) Sleep mode combined with low IQ operation minimizes the input supply current. Input supply current in sleep mode can be calculated based on the wake duty cycle, as shown below: Iin = Iq + (IQG x Dwake) + (Io x D) (8) Where IQG is the gate drive current, calculated as: IQG = (9.2 x 10-9) x fSW And Io is the sum of Iload, Ibias, and current through the feedback resistors. Because this calculation applies only to sleep mode, use the Iq_Sleep_VB and IBIAS_SLEEP values from the Electrical Characteristics. If VBIAS is connected to ground, use the same equation with Ibias equal to zero and Iq_Sleep_VDD.
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9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
the design criteria given in the following sections. Figure 16. Example Circuit 3A, 300 kHz
9.2.1 Design Requirements
Table 1. Design Parameters
9.2.2 Detailed Design Procedure
Table 2. Bill of Materials
9.2.2.1 Setting Output Voltage
- Vfb = 1.236 V typically. (9) A maximum value of 150 kΩ is recommended for the sum of R1 and R2. As input voltage decreases towards the nominal output voltage, the LM26003 device can skip up to seven off- pulses as described in the Low VIN Operation and UVLO section. In low output voltage applications, if the on- time reaches TonMIN, the device will skip on-pulses to maintain regulation. There is no limit to the number of pulses that are skipped. In this mode of operation, however, output ripple voltage may increase slightly.
9.2.2.2 Inductor
compared to load current, or ripple content, is defined as Iripple/Iload. Ripple content should be less than 40%. Larger ripple content increases losses in the inductor and reduces the effective current limit. effective current limit threshold. Remember that inductor value also affects the sleep mode threshold as shown in Figure 15. inductor current are lowered, which increases the current limit margin. output capacitors have some amount of ESR. It does not apply to ceramic output capacitors.
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Irms = Vin Vout x (Vin /cb1 Vout)Iload x C MIN = (/c27 Vt)2 - (/c27 It x Re)2 /c27 Vt -L x/ca9/ca7 /ca9/ca7 Vout x Re /c27Vt /c27It Re MAX = LM26003,LM26003-Q1 www.ti.com SNVS576F –AUGUST 2008–REVISED FEBRUARY 2015 If this method is used, ripple content should still be verified to be less than 40% and that the peak currents do not exceed the minimum current threshold.
9.2.2.3 Output Capacitor
The primary criterion for selecting an output capacitor is equivalent series resistance, or ESR. ESR (Re) can be selected based on the requirements for output ripple voltage and transient response. Once an inductor value has been selected, ripple voltage can be calculated for a given Re using the equation above for LMIN. Lower ESR values result in lower output ripple. Re can also be calculated from the following equation: where
- ΔVt is the allowed voltage excursion during a load transient
- ΔIt is the maximum expected load transient. (13) If the total ESR is too high, the load transient requirement cannot be met, no matter how large the output capacitance. If the ESR criteria for ripple voltage and transient excursion cannot be met, more capacitors should be used in parallel. For non-ceramic capacitors, the minimum output capacitance is of secondary importance, and is determined only by the load transient requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if the maximum ESR requirement is met. The minimum capacitance is calculated as follows: (14) It is assumed the total ESR, Re, is no greater than ReMAX. Also, it is assumed that L has already been selected. Generally speaking, the output capacitance requirement decreases with Re, ΔIt, and L. A typical value greater than 120 µF works well for most applications.
9.2.2.4 Input Capacitor
In a switching converter, very fast switching pulse currents are drawn from the input rail. Therefore, input capacitors are required to reduce noise, EMI, and ripple at the input to the LM26003 device. Capacitors must be selected that can handle both the maximum ripple RMS current at highest ambient temperature as well as the maximum input voltage. The equation for calculating the RMS input ripple current is shown below: (15) For noise suppression, a ceramic capacitor in the range of 1.0 µF to 10 µF should be placed as close as possible to the PVIN pin. For the AVIN pin also some decoupling is necessary. It is very important that the pin is decoupled with such a capacitor close to the AGND pin and the GND pin of the IC to avoid switching noise to couple into the IC. Also some RC input filtering can be implemented using a small resistor between PVIN and AVIN. In Figure 16 the resistor value of R7 is selected to be 0Ω but can be increased to filter with different time constants depending on the capacitor value used. When using a R7 resistor, keep in mind that the resistance will increase the minimum input voltage threshold due to the voltage drop across the resistor. The PVIN decoupling should be implemented in a way to minimize the trace length between the Cin capacitor gnd and the Schottky diode gnd. A larger, high ESR input capacitor should also be used. This capacitor is recommended for damping input voltage spikes during power-on and for holding up the input voltage during transients. In low input voltage applications, line transients may fall below the UVLO threshold if there is not enough input capacitance. Both tantalum and electrolytic type capacitors are suitable for the bulk capacitor. However, large tantalums may not be available for high input voltages and their working voltage must be derated by at least 2X. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LM26003 LM26003-Q1
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9.2.2.5 Bootstrap
The drive voltage for the internal switch is supplied via the BOOT pin. This pin must be connected to a ceramic capacitor, Cboot, from the switch node, shown as C6 in the typical application. The LM26003 device provides the VDD voltage internally, so no external diode is needed. A maximum value of 0.1 µF is recommended for Cboot. Values smaller than 0.022 µF may result in insufficient hold up time for the drive voltage and increased power dissipation. During low Vin operation, when the on-time is extended, the bootstrap capacitor is at risk of discharging. If the Cboot capacitor is discharged below approximately 2.5 V, the LM26003 device enters a high frequency re-charge mode. The Cboot cap is re-charged via the synchronous FET shown in the block diagram. Switching returns to normal when the Cboot cap has been recharged.
9.2.2.6 Catch Diode
When the internal switch is off, output current flows through the catch diode. Alternately, when the switch is on, the diode sees a reverse voltage equal to Vin. Therefore, the important parameters for selecting the catch diode are peak current and peak inverse voltage. The average current through the diode is given by: IDAVE = Iload x (1-D) where
- D is the duty-cycle, defined as Vout/Vin. (16) The catch diode conducts the largest currents during the lowest duty-cycle. Therefore IDAVE should be calculated assuming maximum input voltage. The diode should be rated to handle this current continuously. For overcurrent or short-circuit conditions, the catch diode should be rated to handle peak currents equal to the peak current limit. The peak inverse voltage rating of the diode must be greater than maximum input voltage. A Schottky diode must be used. It's low forward voltage maximizes efficiency and BOOT voltage, while also protecting the SW pin against large negative voltage spikes. When selecting the catch diode for high efficiency low output load applications, select a Schottky diode with low reverse leakage current. Also keep in mind that the reverse leakage current of a Schottky diode increases with temperature and with reverse voltage. Reverse voltage equals roughly the input voltage in a buck converter. At hot, the diode reverse leakage current may be larger than the current consumption of the LM26003 device.
9.2.2.7 Compensation
The purpose of loop compensation is to ensure stable operation while maximizing dynamic performance. Stability can be analyzed with loop gain measurements, while dynamic performance is analyzed with both loop gain and load transient response. Loop gain is equal to the product of control-output transfer function (power stage) and the feedback transfer function (the compensation network). For stability purposes, our target is to have a loop gain slope that is –20dB/decade from a very low frequency to beyond the crossover frequency. Also, the crossover frequency should not exceed one-fifth of the switching frequency, that is, 60 kHz in the case of 300 kHz switching frequency. For dynamic purposes, the higher the bandwidth, the faster the load transient response. The downside to high bandwidth is that it increases the regulators susceptibility to board noise which ultimately leads to excessive falling edge jitter of the switch node voltage. A large DC gain means high DC regulation accuracy (that is, DC voltage changes little with load or line variations). To achieve this loop gain, the compensation components should be set according to the shape of the control- output bode plot. A typical plot is shown in Figure 17.
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an approximation intended to simplify loop compensation calculations. Figure 19. Compensation Network
- The compensation network automatically introduces a low frequency pole (fpc), which is close to 0 Hz.
- Once the fp range is determined, R5 should be calculated using:
- Next, place a zero (fzc) near fp using C5. C5 can be determined with the following equation:
- A second pole (fpc1) can also be placed at fz. This pole can be created with a single capacitor, C4. The
is most helpful for high input voltage applications or when synchronizing to a frequency greater than nominal. This capacitor, shown as C11 in Figure 19, should be placed in parallel with the top feedback resistor, R1. placed somewhat below the fpz1 frequency set by C4. However, if C11 is too large, it will have no effect.
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9.2.3 Application Curves
Refer to Typical Characteristics. Figure 20. Startup Waveforms Figure 21. Load Transient Response
LM26003,LM26003-Q1 SNVS576F –AUGUST 2008–REVISED FEBRUARY 2015 www.ti.com
10 Power Supply Recommendations
The LM26003 device is designed to operate from various DC power supplies including a car battery. If so, VIN input should be protected from reversal voltage and voltage dump over 48 V. The impedance of the input supply rail should be low enough that the input current transient does not cause a drop below VIN UVLO level. If the input supply is connected by using long wires, additional bulk capacitance may be required in addition to normal input capacitor.
11 Layout
11.1 Layout Guidelines
Good board layout is critical for switching regulators such as the LM26003 device. First, the ground plane area must be sufficient for thermal dissipation purposes, and second, appropriate guidelines must be followed to reduce the effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes at the SW node and also at the VIN node. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI) and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise. The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can cause duty-cycle jitter which leads to increased spectrum noise. Although the LM26003 device has 150 ns blanking time at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. Following the important guidelines below will help minimize switching noise and its effect on current sensing. The switch node area should be as small as possible. The catch diode, input capacitors, and output capacitors should be grounded to the same local ground, with the bulk input capacitor grounded as close as possible to the catch diode anode. Additionally, the ground area between the catch diode and bulk input capacitor is very noisy and should be somewhat isolated from the rest of the ground plane. A ceramic input capacitor must be connected as close as possible to the AVIN pin as well as PVIN pin. The capacitor between AVIN and ground should be grounded close to the GND pins of the LM26003 device and the PVIN capacitor should be grounded close to the Schottky diode ground. Often, the AVIN bypass capacitor is most easily located on the bottom side of the PCB. It increases trace inductance due to the vias, it reduces trace length however. The above layout recommendations are illustrated in Figure 22. It is a good practice to connect the EP, GND pin, and small signal components (COMP, FB, FREQ) to a separate ground plane, shown in Figure 22 as EP GND, and in the schematics as a signal ground symbol. Both the exposed pad and the GND pin must be connected to ground. This quieter plane should be connected to the high current ground plane at a quiet location, preferably near the Vout ground as shown by the dashed line in Figure 22. The EP GND plane should be made as large as possible, since it is also used for thermal dissipation. Several vias can be placed directly below the EP to increase heat flow to other layers when they are available. The recommended via hole diameter is 0.3mm. The trace from the FB pin to the resistor divider should be short and the entire feedback trace must be kept away from the inductor and switch node. See AN-1229 SIMPLE SWITCHER ® PCB Layout Guidelines, SNVA054, for more information regarding PCB layout for switching regulators.
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Product Folder Links: LM26003 LM26003-Q1
11.2 Layout Example
Figure 22. Example PCB Layout
11.3 Thermal Considerations and TSD
consideration to determine the maximum allowable load current. board type and metallization area. If the power dissipation remains above the maximum allowable level, device temperature will continue to rise. When the junction temperature exceeds its maximum, the LM26003 device engages Thermal Shut Down (TSD). In TSD, the part remains in a shutdown state until the junction temperature falls to within normal operating limits. At this point, the device restarts in soft-start mode.
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
12.3 Related Links
resources, tools and software, and quick access to sample or buy. Table 3. Related Links
12.4 Trademarks
SIMPLE SWITCHER is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM26003MH/NOPB Active Production HTSSOP (PWP) | 20 73 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 MH LM26003MH/NOPB.A Active Production HTSSOP (PWP) | 20 73 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 MH LM26003MH/NOPB.B Active Production HTSSOP (PWP) | 20 73 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 MH LM26003MHX/NOPB Active Production HTSSOP (PWP) | 20 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 MH LM26003MHX/NOPB.A Active Production HTSSOP (PWP) | 20 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 MH LM26003MHX/NOPB.B Active Production HTSSOP (PWP) | 20 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 MH LM26003QMH/NOPB Active Production HTSSOP (PWP) | 20 73 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 QMH LM26003QMH/NOPB.A Active Production HTSSOP (PWP) | 20 73 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 QMH LM26003QMH/NOPB.B Active Production HTSSOP (PWP) | 20 73 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 QMH LM26003QMHX/NOPB Active Production HTSSOP (PWP) | 20 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 QMH LM26003QMHX/NOPB.A Active Production HTSSOP (PWP) | 20 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 QMH LM26003QMHX/NOPB.B Active Production HTSSOP (PWP) | 20 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM26003 QMH (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1
www.ti.com 23-May-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM26003, LM26003-Q1 :
- Catalog : LM26003
- Automotive : LM26003-Q1 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM26003MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0 LM26003QMHX/NOPB HTSSOP PWP 20 2500 356.0 356.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM26003MH/NOPB PWP HTSSOP 20 73 495 8 2514.6 4.06 LM26003MH/NOPB.A PWP HTSSOP 20 73 495 8 2514.6 4.06 LM26003MH/NOPB.B PWP HTSSOP 20 73 495 8 2514.6 4.06 LM26003QMH/NOPB PWP HTSSOP 20 73 495 8 2514.6 4.06 LM26003QMH/NOPB.A PWP HTSSOP 20 73 495 8 2514.6 4.06 LM26003QMH/NOPB.B PWP HTSSOP 20 73 495 8 2514.6 4.06 Pack Materials-Page 3
www.ti.com MXA20A (Rev C)
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