LM26003 NSC | Alldatasheet
Document overview
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Technical content
Features
■ High efficiency sleep mode ■ 40 µA typical Iq in sleep mode ■ 10.8 µA typical Iq in shutdown mode ■ 3.0V minimum input voltage ■ 4.0V to 38V continuous input range ■ 1.5% reference accuracy ■ Cycle-by-cycle current limit ■ Adjustable Frequency (150 kHz to 500 kHz) ■ Synchronizable to an external clock ■ Power Good Flag ■ Forced PWM function ■ Adjustable Soft-start ■ TSSOP-20 exposed pad package ■ Thermal Shut Down
Applications
■ Automotive Telematics ■ Navigation systems ■ In-Dash Instrumentation ■ Battery Powered Applications ■ Stand-by power for home gateways/set-top boxes Typical Application Circuit 30067601 © 2008 National Semiconductor Corporation 300676 www.national.com LM26003 3A Switching Regulator with High Efficiency Sleep Mode
20-Lead Exposed Pad TSSOP Package
Ordering Information
Order Number Package Type Package Drawing Package Marking Supplied As LM26003MH TSSOP-20EXP MXA20A LM26003MH 73 Units in Rail LM26003MHX LM26003MH 2500 Units in Tape and Reel Pin Descriptions Pin # Pin Name Description
1 VIN Power supply input for high side FET
2 VIN Power supply input for high side FET
3 VIN Power supply input for high side FET
4 AVIN Power supply input for IC supply
5 PGOOD Power Good pin. An open drain output which goes high when the output voltage is greater than 92% of nominal. 6 EN Enable is an analog level input pin. When pulled below 0.8V, the device enters shutdown mode. 7 SS Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time. 8 COMP Compensation pin. Connect to a resistor capacitor pair to compensate the control loop. 9 FB Feedback pin. Connect to a resistor divider between VOUT and GND to set output voltage.
10 AGND Analog GND as IC reference
11 PGND Power GND is GND for the switching stage of the regulator
12 FREQ Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency. 13 FPWM FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation is disabled. 14 SYNC Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be pulled low for non-synchronized operation. 15 VBIAS Connect to an external 3V or greater supply to bypass the internal regulator for improved efficiency. If not used, VBIAS should be tied to GND. 16 VDD The output of the internal regulator. Bypass with a minimum 1.0 µF capacitor. 17 BOOT Bootstrap capacitor pin. Connect a 0.1 µF minimum ceramic capacitor from this pin to SW to generate the gate drive bootstrap voltage. 18 SW Switch pin. The source of the internal N-channel switch. 19 SW Switch pin. The source of the internal N-channel switch. 20 SW Switch pin. The source of the internal N-channel switch. EP EP Exposed Pad thermal connection. Connect to GND. www.national.com 2 LM26003
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltages from the indicated pins to GND: VIN -0.3V to 40V SW (Note 7) -1V to 40V VDD -0.3V to 7V VBIAS -0.3V to 10V FB -0.3V to 6V BOOT VSW-0.3V to VSW+7V PGOOD -0.3V to 7V FREQ -0.3V to 7V SYNC -0.3V to 7V EN -0.3V to 40V FPWM -0.3V to 7V Storage Temperature -65°C to +150°C Power Dissipation (Note 2) 3.1W Recommended Lead Temperature Vapor Phase (70s) 215°C Infrared (15s) 220°C ESD Susceptibility (Note 3) Human Body Model 2 kV Operating Ratings (Note 1) Operating Junction Temp. −40°C to 125°C Supply Voltage (Note 4) 3.0V to 38V Electrical Characteristics Specifications in standard type are for TJ = 25°C only, and limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Unless otherwise stated, Vin = 12V. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Symbol Parameter Conditions Min Typ (Note 5) Max Unit System ISD (Note 6) Shutdown Current EN = 0V 10.8 20 µA IqSleep_VB (Note 6) Quiescent Current Sleep mode, VBIAS = 5V 40 70 µA IqSleep_VDD Quiescent Current Sleep mode, VBIAS = GND 76 125 µA IqPWM_VB Quiescent Current PWM mode, VBIAS = 5V FPWM = 2V 0.16 0.23 mA IqPWM_VDD Quiescent Current PWM mode, VBIAS = GND FPWM = 2V 0.65 0.85 mA IBIAS_Sleep (Note 6) Bias Current Sleep mode, VBIAS = 5V 33 60 µA IBIAS_PWM Bias Current PWM mode, VBIAS = 5V 0.5 0.7 mA VFB Feedback Voltage 5V < Vin < 38V 1.217 1.236 1.255 V IFB FB Bias Current VFB = 1.20V ±200 nA ΔVOUT/ΔVIN Output Voltage Line Regulation 5V < Vin < 38V 0.00025 %/V ΔVOUT/ΔIOUT Output Voltage Load Regulation 0.8V < VCOMP < 1.15V 0.08 %/A VDD VDD Pin Output Voltage 7V < Vin < 35V IVDD= 0 mA to 5 mA 5.50 5.99 6.50 V ISS_Source Soft-start Source Current 1.5 2.5 4.6 µA Vbias_th VBIAS On Voltage Specified at IBIAS = 92.5% of full value 2.64 2.9 3.07 V Switching RDS(ON) Switch On Resistance Isw = 2A 0.040 0.095 0.200 Ω Isw_off Switch Off State Leakage Current Vin = 38V, VSW = 0V 0.002 5.0 µA fsw Switching Frequency RFREQ = 62k, 124k, 240k ±10 % VFREQ FREQ Voltage 1.0 V fSW range Switching Frequency Range 150 500 kHz VSYNC Sync Pin Threshold SYNC rising 1.23 1.6 V SYNC falling 0.8 1.10 Sync Pin Hysteresis 135 mV ISYNC SYNC Leakage Current 2 nA FSYNC_UP Upper Frequency Synchronization Range As compared to nominal fSW +30 % FSYNC_DN Lower Frequency Synchronization Range As compared to nominal fSW -20 % 3 www.national.com LM26003
Symbol Parameter Conditions Min Typ (Note 5) Max Unit TOFFMIN Minimum Off-time 300 ns TONMIN Minimum On-time 190 ns THSLEEP_HYS Sleep Mode Threshold Hysteresis VFB rising, % of THWAKE 101.3 % THWAKE Wake Up Threshold Measured at falling FB COMP = 0.6V 1.236 V IBOOT BOOT Pin Leakage Current BOOT = 6V, SW = GND 0.001 5.0 µA Protection ILIMPK Peak Current Limit 3.15 4.7 6.05 A VFB_SC Short Circuit Frequency Foldback Threshold Measured at FB falling 0.87 V F_min_sc Min Frequency in Foldback VFB < 0.3V 45 kHz VTH_PGOOD Power Good Threshold Measured at FB, PGOOD rising 89 92 95 % PGOOD Hysteresis 2 6 8 % IPGOOD_HI PGOOD Leakage Current PGOOD = 5V 1.25 nA RDS_PGOOD PGOOD On Resistance PGOOD sink current = 500 µA 150 Ω VUVLO Under-voltage Lock-Out Threshold Vin falling , shutdown, VDD = VIN 2.70 2.96 3.30 V Vin rising, soft-start, VDD = VIN 3.70 3.99 4.30 TSD Thermal Shutdown Threshold 160 °C θJA Thermal Resistance Power dissipation = 1W 0 lfpm air flow 32 °C/W Logic VthEN Enable Threshold Voltage Enable rising 0.8 1.18 1.4 V Enable Hysteresis 180 mV IEN_Source EN Source Current EN = 0V 4.85 µA VTH_FPWM FPWM Threshold 0.8 1.24 1.6 V IFPWM FPWM Leakage Current FPWM = 5V 3 nA EA gm Error Amp Trans-conductance 400 675 1000 µmho ICOMP COMP Source Current VCOMP = 0.9V 57 µA COMP Sink Current VCOMP = 0.9V 57 µA VCOMP COMP Pin Voltage Range 0.575 1.365 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions. Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX - TA) /θJA. The maximum power dissipation of 3.1W is determined using TA = 25°C, θJA = 32°C/W, and TJ_MAX = 125°C. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 4: Below 4.0V input, power dissipation may increase due to increased RDS(ON). Therefore, a minimum input voltage of 4.0V is required to operate continuously within specification. A minimum of 3.9V (typical) is also required for startup. Note 5: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 6: Iq and ISD specify the current into the VIN and AVIN pins. IBIAS is the current into the VBIAS pin when the VBIAS voltage is greater than 3V. All quiescent current specifications apply to non-switching operation. Note 7: The absolute maximum specification applies to DC voltage. An extended negative voltage limit of -3V applies for a pulse of up to 200 ns, and -6V for a pulse of up to 50 ns. www.national.com 4 LM26003
Typical Performance Characteristics Unless otherwise specified the following conditions apply: Vin = 12V, TJ = 25°C. Efficiency vs Load Current (300 kHz) 30067637 Efficiency vs Load Current (500 kHz) 30067639 VFB vs Temperature 30067634 VFB vs Vin (IDC = 300 mA) 30067636 IQ and IVBIAS vs Temperature (Sleep Mode) 30067635 IQ and IVBIAS vs Temperature (PWM Mode) 30067638 5 www.national.com LM26003
Peak Current Limit vs Temperature 30067641 Load Transient Response 30067646 Normalized Switching Frequency vs Temperature (300kHz) 30067643 UVLO Threshold vs Temperature (VDD = VIN) 30067645 www.national.com 6 LM26003
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discontinuous operation waveforms are shown below. FIGURE 4. Discontinuous Mode Waveforms and total quiescent current is reduced to 10.8 µA (typical). open, EN will be pulled up to VIN. with at least 2.2 µF to ensure low jitter operation. cycle corresponds to a reduction in output voltage. at the leading edge for increased immunity to switching noise.
The output inductor should be selected based on inductor ripple current. The amount of inductor ripple current com- pared to load current, or ripple content, is defined as Iripple/ Iload. Ripple content should be less than 40%. Inductor ripple current, Iripple, can be calculated as shown below: Larger ripple content increases losses in the inductor and re- duces the effective current limit. Larger inductance values result in lower output ripple voltage and higher efficiency, but a slightly degraded transient re- sponse. Lower inductance values allow for smaller case size, but the increased ripple lowers the effective current limit threshold. Remember that inductor value also affects the sleep mode threshold as shown in Figure 3. When choosing the inductor, the saturation current rating must be higher than the maximum peak inductor current and the RMS current rating should be higher than the maximum load current. Peak inductor current, Ipeak, is calculated as: For example, at a maximum load of 3A and a ripple content of 10%, peak inductor current is equal to 3.15A which is safely at the minimum current limit of 3.15A. By increasing the in- ductor size, ripple content and peak inductor current are lowered, which increases the current limit margin. The size of the output inductor can also be determined using the desired output ripple voltage, Vrip. The equation to deter- mine the minimum inductance value based on Vrip is as follows: Where Re is the ESR of the output capacitors, and Vrip is a peak-to-peak value. This equation assumes that the output capacitors have some amount of ESR. It does not apply to ceramic output capacitors. If this method is used, ripple content should still be verified to be less than 40% and that the peak currents do not exceed the minimum current threshold. OUTPUT CAPACITOR The primary criterion for selecting an output capacitor is equivalent series resistance, or ESR. ESR (Re) can be selected based on the requirements for out- put ripple voltage and transient response. Once an inductor value has been selected, ripple voltage can be calculated for a given Re using the equation above for LMIN. Lower ESR values result in lower output ripple. Re can also be calculated from the following equation: Where ΔVt is the allowed voltage excursion during a load transient, and ΔIt is the maximum expected load transient. If the total ESR is too high, the load transient requirement cannot be met, no matter how large the output capacitance. If the ESR criteria for ripple voltage and transient excursion cannot be met, more capacitors should be used in parallel. For non-ceramic capacitors, the minimum output capacitance is of secondary importance, and is determined only by the load transient requirement. If there is not enough capacitance, the output voltage excur- sion will exceed the maximum allowed value even if the maximum ESR requirement is met. The minimum capaci- tance is calculated as follows: It is assumed the total ESR, Re, is no greater than Re MAX. Also, it is assumed that L has already been selected. Generally speaking, the output capacitance requirement de- creases with Re, ΔIt, and L. A typical value greater than 120 µF works well for most applications. INPUT CAPACITOR In a switching converter, very fast switching pulse currents are drawn from the input rail. Therefore, input capacitors are required to reduce noise, EMI, and ripple at the input to the LM26003. Capacitors must be selected that can handle both the maximum ripple RMS current at highest ambient temper- ature as well as the maximum input voltage. The equation for calculating the RMS input ripple current is shown below: For noise suppression, a ceramic capacitor in the range of 1.0 µF to 10 µF should be placed as close as possible to the PVIN pin. For the AVIN pin also some decoupling is necessary. It is very important that the pin is decoupled with such a capac- itor close to the AGND pin and the GND pin of the IC to avoid switching noise to couple into the IC. Also some RC input fil- tering can be implemented using a small resistor between PVIN and AVIN. In figure 7 the resistor value of R7 is selected to be 0Ω but can be increased to filter with different time con- stants depending on the capacitor value used. When using a R7 resistor, keep in mind that the resistance will increase the minimum input voltage threshold due to the voltage drop across the resistor. The PVIN decoupling should be implemented in a way to minimize the trace length between the Cin capacitor gnd and the Schottky diode gnd. A larger, high ESR input capacitor should also be used. This capacitor is recommended for damping input voltage spikes during power on and for holding up the input voltage during transients. In low input voltage applications, line transients may fall below the UVLO thresh- old if there is not enough input capacitance. Both tantalum and electrolytic type capacitors are suitable for the bulk ca- pacitor. However, large tantalums may not be available for high input voltages and their working voltage must be derated by at least 2X. www.national.com 12 LM26003
FIGURE 10. Compensation Network
- The compensation network automatically introduces a low
frequency pole (fpc), which is close to 0 Hz.
- Once the fp range is determined, R5 should be calculated
point. Bandwidth increases with increasing values of R3.
- Next, place a zero (fzc) near fp using C5. C5 can be de-
but too high a value will slow the transient response time. response, but lower phase margin.
- A second pole (fpc1) can also be placed at fz. This pole can
stability, C4 is very helpful in suppressing noise. the top feedback resistor, R1. too large, it will have no effect. to minimize the effect of this switching noise. what isolated from the rest of the ground plane.
Physical Dimensions inches (millimeters) unless otherwise noted eTSSOP-20 Package 20-Lead Exposed Pad TSSOP Package www.national.com 16 LM26003
17 www.national.com LM26003
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