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LM26001BMHX/NOPB

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LM26001B 1.5A Switching Regulator with High Efficiency Sleep Mode

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LM26001B 1.5A Switching Regulator with High Efficiency Sleep Mode (Rev. B)

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Manufacturer or author: Texas Instruments, Incorporated [SNVS491,B]
PDF pages: 27

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L R1 C6 R4 D1 VDD EPR6 EN SYNC LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 LM26001B1.5ASwitchingRegulatorwithHighEfficiencySleepMode Check forSamples: LM26001B 1FEATURES DESCRIPTION The LM26001B isa switchingregulatordesignedfor 2• High EfficiencySleep Mode the highefficiencyrequirementsof applicationswith• 40 µA TypicalIqinSleep Mode stand-bymodes. The devicefeaturesa low-current

10 µA TypicalIqinShutdown Mode sleep mode to maintainefficiencyunder light-load conditionsand current-modecontrolfor accurate• 3.0VMinimum InputVoltage regulationovera wide inputvoltagerange.Quiescent• 4.0Vto18V Continuous InputRange currentis reduced to 10 µA typicallyin shutdown
2.0% ReferenceAccuracy mode and lessthan 40 µA in sleepmode. Forced PWM mode isalsoavailabletodisablesleepmode.• Cycle-by-CycleCurrentLimit
AdjustableFrequency (150kHz to500 kHz) The LM26001B can deliverup to1.5A ofcontinuous load currentwitha fixedcurrentlimit,throughthe• Synchronizabletoan ExternalClock internalN-channelswitch.The parthas a wide input• Power Good Flag voltagerange of 4.0V to 18V and can operatewith
Forced PWM Function inputvoltagesas lowas 3V duringlinetransients.
AdjustableSoft-Start Operatingfrequencyis adjustablefrom 150 kHz to
HTSSOP-16 Exposed Pad Package 500 kHz with a single resistorand can be synchronizedtoan externalclock.• Thermal Shut Down Other featuresincludePower good, adjustablesoft- APPLICATIONS start,enablepin,inputunder-voltageprotection,and an internalbootstrapdiode forreduced component• Automotive Telematics count.• NavigationSystems
In-DashInstrumentation
BatteryPowered Applications
Stand-byPower forHome Gateways/Set-Top Boxes TypicalApplicationCircuit Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

9 FREQ

10 FPWM

11 SYNC

12 VBIAS

13 VDD

14 BOOT

SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com Connection Diagram Top View Figure1. 16-Lead Exposed Pad HTSSOP Package See Package Number PWP0016A Pin Descriptions Pin # Pin Name Description

1 VIN Power supplyinput

2 VIN Power supplyinput

3 PGOOD Power Good pin.An open drainoutputwhichgoes highwhen theoutputvoltageisgreaterthan92% of nominal. 4 EN Enableisan analoglevelinputpin.When pulledbelow0.8V,thedeviceentersshutdownmode. 5 SS Soft-startpin.Connecta capacitorfromthispintoGND tosetthesoft-starttime. 6 COMP Compensationpin.Connecttoa resistorcapacitorpairtocompensate thecontrolloop. 7 FB Feedback pin.Connecttoa resistordividerbetween Voutand GND tosetoutputvoltage.

8 GND Ground

9 FREQ Frequencyadjustpin.Connecta resistorfromthispintoGND tosettheoperatingfrequency. 10 FPWM FPWM isa logiclevelinputpin.Fornormaloperation,connecttoGND. When pulledhigh,sleepmode operationisdisabled. 11 SYNC Frequencysynchronizationpin.Connecttoan externalclocksignalforsynchronizedoperation.SYNC must be pulledlowfornon-synchronizedoperation. 12 VBIAS Connecttoan external3V orgreatersupplytobypasstheinternalregulatorforimprovedefficiency.If notused,VBIAS shouldbe tiedtoGND. 13 VDD The outputoftheinternalregulator.Bypass witha minimum 1.0µF capacitor. 14 BOOT Bootstrapcapacitorpin.Connecta 0.1µF minimum ceramiccapacitorfromthispintoSW togenerate thegatedrivebootstrapvoltage. 15 SW Switchpin.The sourceoftheinternalN-channelswitch. 16 SW Switchpin.The sourceoftheinternalN-channelswitch. EP EP Exposed Pad thermalconnection.ConnecttoGND. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 AbsoluteMaximum Ratings(1) VoltagesfromtheindicatedpinstoGND: VIN -0.3Vto20V SW (2) -0.5Vto20V VDD -0.3Vto7V VBIAS -0.3Vto10V FB -0.3Vto6V BOOT SW-0.3V toSW+7V PGOOD -0.3Vto7V FREQ -0.3Vto7V SYNC -0.3Vto7V EN -0.3Vto20V FPWM -0.3Vto7V SS -0.3Vto7V StorageTemperature -65°C to+150°C Power Dissipation(3) 2.6W Vapor Phase (70s) 215°C Recommended Lead Temperature Infrared(15s) 220°C Machine Model 200V ESD Susceptibility(4) Human Body Model 2KV Charged DeviceModel 1kV (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notensurespecificperformancelimits.Forensuredspecificationsand test conditions,see theElectricalCharacteristics. (2) The absolutemaximum specificationappliestoDC voltage.An extendednegativevoltagelimitof-2V appliesfora pulseofup to1µs, and -1V fora pulseofup to20µs. (3) The maximum allowablepower dissipationisa functionofthemaximum junctiontemperature,TJ_MAX ,thejunction-to-ambientthermal resistance,θJA,and theambienttemperature,TA.The maximum allowablepower dissipationatany ambienttemperatureiscalculated using:PD_MAX = (TJ_MAX -TA)/θJA.The maximum power dissipationof2.6W isdeterminedusingTA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. (4) The human body model isa 100 pF capacitordischargedthrougha 1.5kΩ resistorintoeach pin.The machine model isa 200pF capacitordischargeddirectlyintoeach pin.The chargeddevicemodel isperJESD22-C101-C. OperatingRatings(1) OperatingJunctionTemp. −40°C to125°C SupplyVoltage(2) 3.0Vto18V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notensurespecificperformancelimits.Forensuredspecificationsand test conditions,see theElectricalCharacteristics. (2) Below 4.0Vinput,power dissipationmay increasedue toincreasedR DS(ON) .Therefore,a minimum inputvoltageof4.0Visrequiredto operatecontinuouslywithinspecification.A minimum of3.9V(typical)isalsorequiredforstartup. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM26001B

SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics SpecificationsinstandardtypeareforTJ = 25°C only,and limitsinboldfacetypeapplyoverthejunctiontemperature(TJ) rangeof-40°C to+125°C. Unlessotherwisestated,Vin=12V.Minimum and Maximum limitsareensuredthroughtest,design, orstatisticalcorrelation.Typicalvaluesrepresentthemost likelyparametricnorm atTJ = 25°C, and areprovidedforreference purposesonly(1) Symbol Parameter Conditions Min Typ Max Unit System ISD (2) Shutdown Current EN = 0V 10.8 20 µA Iq_Sleep_VB(2) QuiescentCurrent Sleepmode, VBIAS = 5V 38 70 µA Iq_Sleep_VDD QuiescentCurrent Sleepmode, VBIAS = GND 75 125 µA Iq_PWM_VB QuiescentCurrent PWM mode, VBIAS = 5V 150 230 µA Iq_PWM_VDD QuiescentCurrent PWM mode, VBIAS = GND 0.65 0.85 mA IBIAS_Sleep(2) BiasCurrent Sleepmode, VBIAS = 5V 33 85 µA IBIAS_PWM BiasCurrent PWM mode, VBIAS = 5V 0.5 0.70 mA VFB Feedback Voltage 5V < Vin< 18V 1.2093 1.234 1.2589 V IFB FB BiasCurrent ±200 nA ΔVOUT /ΔVIN VoutLineRegulation 5V < Vin< 18V 0.001 %/V ΔVOUT /ΔIOUT VoutLoad Regulation 0.8V< VCOMP < 1.15V 0.07 % VDD 7V < Vin< 18V,IVDD = 0 mA to5VDD OutputVoltage 5.50 5.95 6.50 VmA ISS_Source Soft-StartSourceCurrent 1.5 2.2 4.6 µA Vbias_th SpecifiedatIBIAS = 92.5% offullVBIAS On Voltage 2.64 2.9 3.07 Vvalue Switching R DS(ON) SwitchOn Resistance Isw= 1A 0.12 0.2 0.42 Ω Isw_off SwitchOffStateLeakage Current Vin= 18V,VSW = 0V 0.002 5.0 µA fsw SwitchingFrequency RFREQ = 62k,124k,240k ±10 % VFREQ FREQ Voltage 1.0 V fSW range SwitchingFrequencyRange 150 500 kHz VSYNC SYNC rising 1.2 1.6 Sync PinThreshold V SYNC falling 0.8 1.1 Sync PinHysteresis 114 mV ISYNC SYNC Leakage Current 6 nA FSYNC_UP Upper frequencysynchronizationrange As compared tonominalfSW +30 % FSYNC_DN Lower frequencysynchronizationrange As compared tonominalfSW -20 % TOFFMIN Minimum Off-time 365 ns TONMIN Minimum On-time 155 ns TH SLEEP_HYS SleepMode ThresholdHysteresis VFB rising,% ofTH WAKE 101.2 % TH WAKE Measured atfallingFB,Wake Up Threshold 1.234 VCOMP = 0.6V IBOOT BOOT PinLeakage Current BOOT = 16V,SW = 10V 0.0006 5.0 µA (1) Allroom temperaturelimitsare100% productiontested.Alllimitsattemperatureextremesarespecifiedthroughcorrelationusing standardStatisticalQualityControl(SQC) methods.Alllimitsareused tocalculateAverageOutgoingQualityLevel(AOQL). (2) Iqand ISD specifythecurrentintotheVIN pin.IBIASisthecurrentintotheVBIAS pinwhen theVBIAS voltageisgreaterthan3V.All quiescentcurrentspecificationsapplytonon-switchingoperation.

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www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 ElectricalCharacteristics(continued) SpecificationsinstandardtypeareforTJ = 25°C only,and limitsinboldfacetypeapplyoverthejunctiontemperature(TJ) rangeof-40°C to+125°C. Unlessotherwisestated,Vin=12V.Minimum and Maximum limitsareensuredthroughtest,design, orstatisticalcorrelation.Typicalvaluesrepresentthemost likelyparametricnorm atTJ = 25°C, and areprovidedforreference purposesonly(1) Symbol Parameter Conditions Min Typ Max Unit Protection ILIMPK Peak CurrentLimit 1.80 2.5 3.25 A VFB_SC ShortCircuitFrequencyFoldback Measured atFB falling 0.87 VThreshold F_min_sc Min FrequencyinFoldback VFB < 0.3V 71 kHz VTH_PGOOD Power Good Threshold Measured atFB, PGOOD rising 89 92 95 % PGOOD Hysteresis 2 7 8 % IPGOOD_HI PGOOD Leakage Current PGOOD = 5V 0.2 nA R DS_PGOOD PGOOD On Resistance PGOOD sinkcurrent= 500 µA 64 Ω VUVLO Vinfalling,shutdown,VDD = VIN 2.60 2.9 3.20 Under-VoltageLock-OutThreshold V Vinrising,soft-start,VDD = VIN 3.60 3.9 4.20 TSD ThermalShutdown Threshold 160 °C θJA Power dissipation= 1W,ThermalResistance 38 °C/W0 lfpmairflow Logic VthEN EnableThresholdvoltage 0.8 1.2 1.4 V EnableHysteresis 120 mV IEN_Source EN SourceCurrent EN = 0V 4.5 µA VTH_FPWM FPWM Threshold 0.8 1.2 1.6 V IFPWM FPWM Leakage Current FPWM = 5V 35 nA EA gm ErrorAmp Trans-Conductance 400 670 1000 µmho ICOMP COMP SourceCurrent VCOMP = 0.9V 56 µA COMP SinkCurrent VCOMP = 0.9V 56 µA VCOMP COMP PinVoltageRange 0.64 1.27 V Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM26001B

VIN (V) 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 TEMPERATURE (ºC) -40 -20 0 20 40 60 80 100 120 140 On Threshold Off Threshold 100 101 102 -40 0 40 80 120 TEMPERATURE (ºC) SWITCHING FREQUENCY (%) 100 1406020-20 TEMPERATURE (ºC) CURRENT ( PA) -40 0 40 80 120 100 1406020-20 IQ (VBIAS=0V) IQ (VBIAS=5V) IVBIAS (VBIAS=5V) 500 700 TEMPERATURE (ºC) CURRENT ( PA) 600 100 200 300 400 -40 0 40 80 120 100 1406020-20 IQ (VBIAS=0V) IQ (VBIAS=5V) IVBIAS (VBIAS=5V) 0 4 8 12 16 20 VFB (V) VIN (V) 1.232 1.236 1.235 1.233 1.234 TEMPERATURE (ºC) VFB (V) -40 0 40 80 120100 1406020-20 1.228 1.230 1.232 1.234 1.236 LM26001B SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics Unlessotherwisespecifiedthefollowingconditionsapply:Vin= 12V,TJ = 25°C. VFB vs Vin VFB vs Temperature (IDC= 300 mA) Figure2. Figure3. IQ and IVBIAS vs IQ and IVBIAS vs Temperature (SleepMode) Temperature (PWM Mode) Figure4. Figure5. NormalizedSwitchingFrequency UVLO Thresholdvs vs Temperature (300kHz) Temperature (VDD = VIN) Figure6. Figure7.

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EFFICIENCY (%) IDC (mA) 10 100 1000 10000 5Vout 3.3Vout FPWM mode50 100 EFFICIENCY (%) IDC (mA) 10 100 1000 10000 5Vout 3.3Vout FPWM mode50 100 VFB (V) SWITCHING FREQUENCY (kHz) 100 150 200 250 300 350 TEMPERATURE (ºC) ILIM PEAK (A) 2.0 2.2 2.4 2.6 2.8 3.0 -40 -20 0 20 40 60 80 100 120 140 LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 TypicalPerformance Characteristics(continued) Unlessotherwisespecifiedthefollowingconditionsapply:Vin= 12V,TJ = 25°C. Peak CurrentLimit ShortCircuitFoldback Frequency vs Temperature vs VFB (325kHz nominal) Figure8. Figure9. Efficiencyvs Efficiencyvs Load Current(330kHz) Load Current(500kHz) Figure10. Figure11. StartupWaveforms Figure12. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM26001B

3 3.5 4 4.5 5 5.5 VIN (V) VIN-VOUT DROPOUT (mV) 1A 125°C 1A 25°C 1A -40°C 40mA -40°C 40mA 25 to 125°C Vout 40 mV/Div Iout 500 mA/Div

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SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) Unlessotherwisespecifiedthefollowingconditionsapply:Vin= 12V,TJ = 25°C. Low InputVoltageDropout Load TransientResponse Nominal VOUT = 5V Figure13. Figure14.

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0.6V 2 PA 0.9V V clamp SS logic TSD VDD_low ss end blanking qn qn fpwm Sync and bootstrap controlfpwm LG LG 5 PA VDD_low EN FB SW SW FPWM COMP PGOOD SS GND SYNC BOOT VIN VBIAS VDD VIN SD Clock / Sync BG BG I Sense PWM Comp BG IREF TSD FPWM / Sleep Peak Current Control Sleep Reset EA PG 0.92BG Corrective Ramp PWM Control Logic Sleep Set LDO UVLO on Switchover control VREG sleep EP frequency foldback FREQ soft start on SD ff ff LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 Block Diagram OperationDescription GENERAL The LM26001B isa currentmode PWM buck regulator.At thebeginningofeach clockcycle,theinternalhigh- sideswitchturnson, allowingcurrentto ramp up inthe inductor.The inductorcurrentisinternallymonitored duringeach switchingcycle.A controlsignalderivedfromtheinductorcurrentiscompared tothevoltagecontrol signalattheCOMP pin,derivedfromthefeedbackvoltage.When theinductorcurrentreachesthethreshold,the high-sideswitchisturnedoffand inductorcurrentramps down. While the switchisoff,inductorcurrentis suppliedthroughthecatchdiode.Thiscyclerepeatsatthenextclockcycle.Inthisway, dutycycleand output voltageare controlledby regulatinginductorcurrent.Currentmode controlprovidessuperiorlineand load regulation.Otherbenefitsincludecycleby cyclecurrentlimitingand a simplifiedcompensationscheme. Typical PWM waveformsareshown inFigure15. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM26001B

ISleep = Imin + 0.13 P Vin - Vout L x fsw x L D x 2 x (Vin ± Vout) Vout 50 mV/Div VSW 5V/Div IL 200 mA/Div

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SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com Figure15. PWM Waveforms 1A Load, Vin = 12V SLEEP MODE Inlightloadconditions,theLM26001B automaticallyswitchesintosleepmode forimprovedefficiency.As loading decreases,thevoltageatFB increasesand theCOMP voltagedecreases.When theCOMP voltagereachesthe 0.6V(typical)clamp threshold,and theFB voltagerises1% above nominal,sleepmode isenabledand switching stops.The regulatorremains in sleepmode untilthe FB voltagefallsto the resetthreshold,at which point switchingresumes.This1% FB window limitsthecorrespondingoutputrippletoapproximately1% ofnominal outputvoltage.The sleepcyclewillrepeatuntilloadcurrentisincreased.Figure16 shows typicalswitchingand outputvoltagewaveformsinsleepmode. Figure16. Sleep Mode Waveforms 25mA Load, Vin = 12V In sleepmode, quiescentcurrentisreduced to lessthan 40 µA when not switching.The DC sleepmode thresholdcan be calculatedaccordingtotheequationbelow: where

Imin=Ilim/16(2.5A/16typically)and D=duty cycle,definedas (Vout+Vdiode)/Vin (1) When loadcurrentincreasesabove thislimit,theLM26001B isforcedback intoPWM operation.The sleepmode thresholdvarieswithfrequency,inductance,and dutycycleas shown inFigure17.

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VIN (V) IDC (mA) 100 120 160 10 14 16 20 22 PH 15 PH 22 PH 15 PH 500 kHz 330 kHz 140 4 6 8 12 18 LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 Figure17. Sleep Mode Thresholdvs Vin Vout = 3.3V FPWM Pullingthe FPWM pinhighdisablessleepmode and forcesthe LM26001B to always operateinPWM mode. LightloadefficiencyisreducedinPWM mode, butswitchingfrequencyremainsstable.The FPWM pincan be connectedtotheVDD pintopullithigh.InFPWM mode, under lightloadconditions,theregulatoroperatesin discontinuousconductionmode (DCM) .Indiscontinuousconductionmode, currentthroughtheinductorstartsat zeroand ramps up toitspeak,thenramps down tozeroagain.Untilthenextcycle,theinductorcurrentremains atzero.At nominalloadcurrents,inFPWM mode, thedeviceoperatesincontinuousconductionmode, where positivecurrentalwaysflowsintheinductor.Typicaldiscontinuousoperationwaveformsareshown below. Figure18. DiscontinuousMode Waveforms 75mA Load, Vin = 12V At verylightload,inFPWM mode, the LM26001B may entersleepmode. Thisisto preventan over-voltage conditionfromoccurring.However,theFPWM sleepthresholdismuch lowerthaninnormaloperation. ENABLE The LM26001B providesa shutdown functionviatheEN pintodisablethedevicewhen theoutputvoltagedoes notneed tobe maintained.EN isan analoglevelinputwithtypically120 mV ofhysteresis.The deviceisactive when theEN pinisabove 1.2V (typical)and inshutdown mode when EN isbelow thisthreshold.When EN goes high,theinternalVDD regulatorturnson and chargestheVDD capacitor.When VDD reaches3.9V (typical),the soft-startpinbeginsto sourcecurrent.In shutdown mode, the VDD regulatorshutsdown and totalquiescent currentisreducedto10 µA (typical).Because theEN pinsources4.5µA (typical)ofpull-upcurrent,thispincan be leftopen orconnectedtoVIN foralways-onoperation.When open,EN willbe pulledup toVIN. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM26001B

(Vin ± Vout) x Vout fsw x L x VinIripple = Iripple 2Iloadmax = 1.80A - Iss x tss 1.234VCss = LM26001B SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com SOFT-START The soft-startfeatureprovidesa controlledoutputvoltageramp up atstartup.Thisreducesinrushcurrentand eliminatesoutputovershootatturn-on.The soft-startpin,SS, must be connectedtoGND througha capacitor.At power-on,enable,orUVLO recovery,an internal2.2µA (typical)currentchargesthesoft-startcapacitor.During soft-start,theerroramplifieroutputvoltageiscontrolledby boththesoft-startvoltageand thefeedbackloop.As the SS pinvoltageramps up, the dutycycleincreasesproportionalto the soft-startramp, causingthe output voltageto ramp up. The rateat which the dutycycleincreasesdepends on the capacitanceof the soft-start capacitor.The higherthecapacitance,theslowertheoutputvoltageramps up.The soft-startcapacitorvaluecan be calculatedwiththefollowingequation: (2) Where tssisthedesiredsoft-starttimeand Issisthesoft-startsourcecurrent.Duringsoft-start,currentlimitand synchronizationremainineffect,whilesleepmode and frequencyfoldbackare disabled.Soft-startmode ends when theSS pinvoltagereaches1.23V typical.At thispoint,outputvoltagecontrolistransferredtotheFB pin and theSS pinisdischarged. CURRENT LIMIT The peak currentlimitissetinternallyby directlymeasuringpeak inductorcurrentthroughtheinternalswitch.To ensureaccuratecurrentsensing,VIN shouldbe bypassed witha minimum 1µF ceramiccapacitorplaceddirectly atthepin. When the inductorcurrentreachesthe currentlimitthreshold,the internalFET turnsoffimmediatelyallowing inductorcurrentto ramp down untilthe nextcycle.Thisreductionindutycyclecorrespondsto a reductionin outputvoltage. The currentlimitcomparatorisdisabledforlessthan 100ns at the leadingedge forincreasedimmunityto switchingnoise. Because the currentlimitmonitorspeak inductorcurrent,the DC load currentlimitthresholdvarieswith inductanceand frequency.Assuming a minimum currentlimitof1.80A,maximum loadcurrentcan be calculated as follows: where

Irippleisthepeak-to-peakinductorripplecurrent,calculatedas (3) To findtheworstcase (lowest)currentlimitthreshold,use themaximum inputvoltageand minimum currentlimit specification. Duringhighover-currentconditions,such as outputshortcircuit,theLM26001B employs frequencyfoldbackas a second levelof protection.Ifthe feedbackvoltagefallsbelow the shortcircuitthresholdof 0.9V,operating frequencyis reduced,therebyreducingaverage switchcurrent.This is especiallyhelpfulin shortcircuit conditions,when inductorcurrentcan riseveryhighduringtheminimum on-time.Frequencyreductionbeginsat 20% belowthenominalfrequencysetting.The minimum operatingfrequencyinfoldbackmode is71 kHz typical. Ifthe FB voltagefallsbelow the frequencyfoldbackthresholdduringfrequencysynchronizedoperation,the SYNC functionisdisabled.OperatingfrequencyversusFB voltageinshortcircuitconditionsisshown inthe TypicalPerformanceCharacteristicssection. Inconditionswhere theon timeisclosetominimum (lessthan200nsec typically),such as highinputvoltageand highswitchingfrequency,the currentlimitmay not functionproperly.Thisisbecause the currentlimitcircuit cannotreducetheon-timebelow minimum which preventsentryintofrequencyfoldbackmode. There are two ways to ensure propercurrentlimitand foldbackoperationunder high inputvoltageconditions.First,the operatingfrequencycan be reduced to increasethe nominal on time.Second, the inductorvalue can be increasedtoslowthecurrentramp and reducethepeak over-current.

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Iinput = Iq + IQG + IBIAS x D eff© Sync_Dmin t1 - fnom fsync 0 50 100 150 200 250 300 R FREQ (k:) 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz) LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 FREQUENCY ADJUSTMENT AND SYNCHRONIZATION The switchingfrequencyof the LM26001B can be adjustedbetween 150 kHz and 500 kHz usinga single externalresistor.Thisresistorisconnectedfrom the FREQ pinto ground as shown inthe TypicalApplication Circuit.The resistorvaluecan be calculatedwiththefollowingempiricallyderivedequation: R FREQ = (6.25x 1010)x fSW -1.042 (4) Figure19. SwtichingFrequency vs R FREQ The switchingfrequencycan alsobe synchronizedtoan externalclocksignalusingtheSYNC pin.The SYNC pinallowstheoperatingfrequencytobe variedabove and below thenominalfrequencysetting.The adjustment rangeisfrom30% above nominalto20% below nominal.Externalsynchronizationrequiresa 1.2V (typical)peak signallevelattheSYNC pin.The FREQ resistormust alwaysbe connectedtoinitializethenominaloperating frequency.The operatingfrequencyissynchronizedto the fallingedge of the SYNC input.When SYNC goes low,thehigh-sideswitchturnson.Thisallowsany dutycycletobe used forthesync signalwhen synchronizing toa frequencyhigherthannominal.When synchronizingtoa lowerfrequency,however,thereisa minimum duty cyclerequirementfortheSYNC signal,givenintheequationbelow: (5) Where fnom isthe nominalswitchingfrequencysetby the FREQ resistor,and fsyncisa square wave. Ifthe SYNC pinisnotused,itmust be pulledlow fornormaloperation.A 10kΩ pull-downresistorisrecommended to protectagainsta missingsync signal.Althoughthe LM26001B is designed to operateat up to 500 kHz, maximum loadcurrentmay be limitedathigherfrequenciesdue toincreasedtemperaturerise.See theThermal Considerationssection. VBIAS The VBIAS pinisused tobypass theinternalregulatorwhichprovidesthebiasvoltagetotheLM26001B. When theVBIAS pinisconnectedtoa voltagegreaterthan3V, theinternalregulatorautomaticallyswitchesovertothe VBIAS input.ThisreducesthecurrentintoVIN (Iq)and increasessystemefficiency.UsingtheVBIAS pinhas the added benefitofreducingpower dissipationwithinthedevice. For most applicationswhere 3V < Vout < 10V, VBIAS can be connectedtoVout.Ifnotused,VBIAS shouldbe tiedtoGND. IfVBIAS dropsbelow 2.9V (typical),thedeviceautomaticallyswitchesovertosupplytheinternalbiasvoltage fromVin. Totaldeviceinputcurrentisthesum ofIq,gatedrivecurrent,and VBIAS current,plussome negligiblecurrent intotheFB pin.Totalminimum inputsupplycurrentcan be calculatedas shown below: where

IQG isthegatedrivecurrent,calculatedas IQG = (4.6x 10-9)x fSW (6) Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM26001B

4 Ps/DIV

SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com Totalsupplyinputcurrentvariesaccordingto load,system efficiency,and operatingfrequency.To calculate minimum inputcurrentduringsleepmode, use Iq_Sleep_VB,and IBIAS_SLEEP . ForinputcurrentinPWM mode, use thesame equation,withIq_PWM_VB ,and IBIAS_PWM . IfVBIAS isconnectedtoground,use thesame equationwiththeIbiastermeliminatedand eitherIq_Sleep_VDD or Iq_PWM_VDD . LOW VIN OPERATION AND UVLO The LM26001B isdesignedtoremainoperationalduringshortlinetransientswhen inputvoltagemay dropas low as 3.0V.Minimum nominaloperatinginputvoltageis4.0V.Below thisvoltage,switchR DS(ON) increases,due to thelowergatedrivevoltagefromVDD. The minimum voltagerequiredatVDD isapproximately3.5V fornormal operationwithinspecification. VDD can alsobe used as a pull-upvoltageforfunctionssuch as PGOOD and FPWM. Note thatifVDD isused externally,thepinisnotrecommended forloadsgreaterthan1 mA. Ifthe inputvoltageapproachesthe nominaloutputvoltage,the dutycycleismaximized to holdup the output voltage.In thismode of operation,once the duty cyclereaches itsmaximum, the LM26001B can skipa maximum ofseven offpulses,effectivelyincreasingthedutycycleand thusminimizingthedropoutfrominputto output.Typicaloff-pulseskippingwaveformsareshown below. Figure20. Off-pulseSkippingWaveforms Vin = 3.5V,Vnom = 3.3V,fnom = 305kHz UVLO issensed atbothVIN and VDD, and isactivatedwhen eithervoltagefallsbelow 2.9V (typical).Although VDD istypicallylessthan200mV below VIN,itwillnotdischargethroughVIN.Thereforewhen theVIN voltage dropsrapidly,VDD may remainhigh,especiallyinsleepmode. For fastlinevoltagetransients,usinga larger capacitorat the VDD pin can help to hold offa UVLO shutdown by extendingthe VDD dischargetime.By holdingup VDD, a largercap can also reduce the R DS(ON) (and dropoutvoltage)in low VIN conditions. Alternately,under heavy loadingtheVDD voltagecan fallseveralhundred mV below VIN.Inthiscase,UVLO may be triggeredby VDD even thoughtheVIN voltageisabove theUVLO threshold. When UVLO isactivatedtheLM26001B entersa standbystateinwhichVDD remainscharged.As inputvoltage and VDD voltageriseabove 3.9V(typical)thedevicewillrestartfromsoftstartmode. PGOOD A power good pin,PGOOD, isavailabletomonitortheoutputvoltagestatus.The pinisinternallyconnectedto an open drainMOSFET, which remainsopen whiletheoutputvoltageiswithinoperatingrange.PGOOD goes low (lowimpedance toground)when theoutputfallsbelow 85% ofnominalorEN ispulledlow.When theoutput voltagereturnsto within92% of nominal,as measured at the FB pin,PGOOD returnsto a high state.For improvednoiseimmunity,thereisa 5us delaybetween thePGOOD thresholdand thePGOOD pingoinglow.

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(Vin ± Vout) x Vout fsw x L x VinIripple = R2 = Vout Vfb© LM26001B SW SW BOOT FB COMP VDD GNDFPWM FREQ SS SYNC EN PGOOD VIN2 139 144 Vin: 4V ± 18V Vout: 3.3V VIN VBIAS1 12 3.3 PF 25V 10 nF R3 120k 4.7 nF 15k L 22 PH 3.5A 0.1 PF 33k 56k 100 PF 12 m: 10 PF 30V VDD EP 10k EN SYNC + C2 47 PF 25V PGOOD 47 pF 200k LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 Design Information EXAMPLE CIRCUIT Figure21 shows a completetypicalapplicationschematic.The components have been selectedbased on the designcriteriagiveninthefollowingsections. Figure21. Example Circuit 1.5A Max, 305 kHz SETTING OUTPUT VOLTAGE The outputvoltageissetby the ratioof a voltagedividerat the FB pinas shown inthe TypicalApplication Circuit.The resistorvaluescan be determinedby thefollowingequation: where

Vfb= 1.234Vtypically (7) A maximum valueof150kΩ isrecommended forthesum ofR1 and R2. As inputvoltagedecreasestowardsthenominaloutputvoltage,theLM26001B can skipup toseven off-pulses as describedintheLow VinOperationsection.Inlow outputvoltageapplications,iftheon-timereachesTonMIN , thedevicewillskipon-pulsestomaintainregulation.Thereisno limittothenumber ofpulsesthatareskipped.In thismode ofoperation,however,outputripplevoltagemay increaseslightly. INDUCTOR The outputinductorshouldbe selectedbased on inductorripplecurrent.The amount ofinductorripplecurrent compared toloadcurrent,orripplecontent,isdefinedas Iripple/Iload.Ripplecontentshouldbe lessthan40%. Inductorripplecurrent,Iripple,can be calculatedas shown below: (8) Largerripplecontentincreaseslossesintheinductorand reducestheeffectivecurrentlimit. Largerinductancevaluesresultin loweroutputripplevoltageand higherefficiency,but a slightlydegraded transientresponse.Lower inductancevaluesallowforsmallercase size,but the increasedripplelowersthe effectivecurrentlimitthreshold. Remember thatinductorvaluealsoaffectsthesleepmode thresholdas shown inFigure17. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM26001B

C MIN = ('Vt)2 - ('It x Re)2 'Vt -L x©§ Vout x Re 'Vt 'It Re MAX = (Vin ± Vout) x Vout x Re Vin x fsw x VripLMIN = Iripple 2Ipeak = Iload + LM26001B SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com When choosingthe inductor,the saturationcurrentratingmust be higherthan the maximum peak inductor currentand the RMS currentratingshouldbe higherthan the maximum loadcurrent.Peak inductorcurrent, Ipeak,iscalculatedas: (9) For example,ata maximum loadof1.5A and a ripplecontentof33%, peak inductorcurrentisequalto1.75A whichissafelybelowtheminimum currentlimitof1.80A.By increasingtheinductorsize,ripplecontentand peak inductorcurrentarelowered,whichincreasesthecurrentlimitmargin. The sizeof the outputinductorcan also be determinedusing the desiredoutputripplevoltage,Vrip.The equationtodeterminetheminimum inductancevaluebased on Vripisas follows: where

Re istheESR oftheoutputcapacitors
Vripisa peak-to-peakvalue (10) Thisequationassumes thattheoutputcapacitorshave some amount ofESR. Itdoes notapplytoceramicoutput capacitors. Ifthismethod isused,ripplecontentshouldstillbe verifiedtobe lessthan40%. OUTPUT CAPACITOR The primarycriterionforselectingan outputcapacitorisequivalentseriesresistance,orESR. ESR (Re)can be selectedbased on therequirementsforoutputripplevoltageand transientresponse.Once an inductorvaluehas been selected,ripplevoltagecan be calculatedfora givenRe usingtheequationabove for Lmin.Lower ESR valuesresultinloweroutputripple. Re can alsobe calculatedfromthefollowingequation: where
ΔVtistheallowedvoltageexcursionduringa loadtransient
ΔItisthemaximum expectedloadtransient (11) Ifthe totalESR istoo high,the load transientrequirementcannot be met, no matterhow largethe output capacitance. IftheESR criteriaforripplevoltageand transientexcursioncannotbe met,more capacitorsshouldbe used in parallel. For non-ceramiccapacitors,theminimum outputcapacitanceisofsecondaryimportance,and isdeterminedonly by theloadtransientrequirement. Ifthereisnotenough capacitance,theoutputvoltageexcursionwillexceed themaximum allowedvalueeven if themaximum ESR requirementismet.The minimum capacitanceiscalculatedas follows: (12) Itisassumed thetotalESR, Re, isno greaterthanRe MAX .Also,itisassumed thatL has alreadybeen selected. Generallyspeaking,theoutputcapacitancerequirementdecreaseswithRe, ΔIt,and L.A typicalvaluegreater than100 µF workswellformost applications.

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Irms = Vin Vout x (Vin ± Vout)Iload x LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 INPUT CAPACITOR In a switchingconverter,very fastswitchingpulse currentsare drawn from the inputrail.Therefore,input capacitorsare requiredto reduce noise,EMI, and rippleat the inputto the LM26001B. Capacitorsmust be selectedthatcan handleboththemaximum rippleRMS currentathighestambienttemperatureas wellas the maximum inputvoltage.The equationforcalculatingtheRMS inputripplecurrentisshown below: (13) Fornoisesuppression,a ceramiccapacitorintherangeof1.0µF to10 µF shouldbe placedas closeas possible totheVIN pin. A larger,high ESR inputcapacitorshouldalsobe used. This capacitorisrecommended fordamping input voltagespikesduringpower on and forholdingup the inputvoltageduringtransients.In low inputvoltage applications,linetransientsmay fallbelow the UVLO thresholdifthereisnot enough inputcapacitance.Both tantalumand electrolytictypecapacitorsaresuitableforthebulkcapacitor.However,largetantalumsmay notbe availableforhighinputvoltagesand theirworkingvoltagemust be deratedby atleast2X. BOOTSTRAP The drivevoltagefortheinternalswitchissuppliedviatheBOOT pin.Thispinmust be connectedtoa ceramic capacitor,Cboot,fromtheswitchnode,shown as C4 inthetypicalapplication.The LM26001B providestheVDD voltageinternally,so no externaldiode isneeded. A minimum valueof 0.1 uF isrecommended forCboot. Smallervaluesmay resultininsufficientholdup timeforthedrivevoltageand increasedpower dissipation. Duringlow Vin operation,when theon-timeisextended,thebootstrapcapacitorisatriskofdischarging.Ifthe Cboot capacitorisdischargedbelow approximately2.5V,the LM26001B entersa high frequencyre-charge mode. The Cboot cap isre-chargedviatheLG synchronousFET shown intheBlockDiagram.Switchingreturns tonormalwhen theCboot cap has been recharged. CATCH DIODE When theinternalswitchisoff,outputcurrentflowsthroughthecatchdiode.Alternately,when theswitchison, thediodesees a reversevoltageequaltoVin.Therefore,theimportantparametersforselectingthecatchdiode arepeak currentand peak inversevoltage.The averagecurrentthroughthediodeisgivenby: IDAVE = Iloadx (1-D) (14) Where D isthedutycycle,definedas Vout/Vin.The catchdiodeconductsthelargestcurrentsduringthelowest dutycycle.ThereforeIDAVE shouldbe calculatedassuming maximum inputvoltage.The diodeshouldbe ratedto handlethiscurrentcontinuously.For over-currentor shortcircuitconditions,thecatchdiodeshouldbe ratedto handlepeak currentsequaltothepeak currentlimit. The peak inversevoltageratingofthediodemust be greaterthanmaximum inputvoltage. A Schottkydiodemust be used.It'slow forwardvoltagemaximizes efficiencyand BOOT voltage,whilealso protectingtheSW pinagainstlargenegativevoltagespikes COMPENSATION The purposeofloopcompensationistoensurestableoperationwhilemaximizingdynamicperformance.Stability can be analyzedwithloopgainmeasurements,whiledynamic performanceisanalyzedwithbothloopgainand loadtransientresponse.Loop gainisequaltotheproductofcontrol-outputtransferfunction(powerstage)and thefeedbacktransferfunction(thecompensationnetwork). For stabilitypurposes,ourtargetistohave a loopgainslopethatis-20dB /decadefroma verylow frequencyto beyond the crossoverfrequency.Also,the crossoverfrequencyshouldnot exceed one-fifthof the switching frequency,i.e.60 kHz inthecase of300 kHz switchingfrequency. For dynamic purposes,thehigherthebandwidth,thefastertheloadtransientresponse.A largeDC gainmeans highDC regulationaccuracy(i.e.DC voltagechanges littlewithloadorlinevariations).To achievethisloopgain, thecompensationcomponents shouldbe setaccordingtotheshape ofthecontrol-outputbode plot.A typical plotisshown inFigure22 below. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM26001B

fswfn = 10 x S x Ro x Cofp = + 0.5 2 x S x L x fsw x Co 2S x Re x Cofz = B fzc fpc1 FREQUENCY GAIN (dB) fpc (0Hz) -20dB /dec -20dB/dec 0dB/dec -60 -40 -20 0.01 0.1 1 10 100 FREQUENCY (kHz) GAIN (dB) 1000 -45 -90 -135 -180 PHASE (º) fp fz fn LM26001B SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com Figure22. Control-OutputTransferFunction The control-outputtransferfunctionconsistsof one pole(fp),one zero (fz),and a doublepoleat fn (halfthe switchingfrequency). ReferringtoFigure22,thefollowingshouldbe done tocreatea -20dB /decaderoll-offoftheloopgain: 1.Placea poleat0Hz (fpc) 2.Placea zeroatfp(fzc) 3.Placea second poleatfz(fpc1) The resultingfeedback (compensation)bode plotis shown below in Figure23. Adding the control-output responsetothefeedbackresponsewillthenresultina nearlycontinuous-20db/decadeslope. Figure23. Feedback TransferFunction The control-outputcornerfrequenciescan be determinedapproximatelyby thefollowingequations: (15) (16) where

Co istheoutputcapacitance
Ro istheloadresistance
Re istheoutputcapacitorESR
fswistheswitchingfrequency (17)

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2 x S x R1 x C10fzff = 2 x S x fz x R5C9 = 2 x S x fPMAX x R5C8 = R5 = R1 + R2 R2© gm x FB COMP SS R1R2 C10 To Vout LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 The effectsofslopecompensationand currentsense gainareincludedinthisequation.However,theequationis an approximationintendedtosimplifyloopcompensationcalculations.To derivetheexacttransferfunction,use 0.2V/Vsense amp gainand 36mVp-p slopecompensation. Since fp is determinedby the outputnetwork,itshiftswith loading.Determine the range of frequencies (fpmin/max)acrosstheexpectedloadrange.Then determinethecompensationvaluesas describedbelow and shown inFigure24. Figure24. Compensation Network 1.The compensationnetworkautomaticallyintroducesa lowfrequencypole(fpc),whichiscloseto0Hz. 2.Once thefprangeisdetermined,R5 shouldbe calculatedusing: where

B isthedesiredfeedbackgaininv/vbetween fpand fz
gm isthetransconductanceoftheerroramplifier (18) A gainvaluearound10dB (3.3v/v)isgenerallya good startingpoint.Bandwidthincreaseswithincreasingvalues ofR5. 3.Next,placea zero(fzc)nearfpusingC8. C8 can be determinedwiththefollowingequation: (19) The selectedvalueofC8 shouldplacefzcwithina decade above or below fpmax,and notlessthanfpmin.A higherC8 value(closerto fpmin)generallyprovidesa more stableloop,but too high a valuewillslow the transientresponsetime.Conversely,a smallerC8 valuewillresultina fastertransientresponse,butlowerphase margin. 4. A second pole(fpc1)can alsobe placedat fz.Thispolecan be createdwitha singlecapacitor,C9. The minimum valueforthiscapacitorcan be calculatedby: (20) C9 may notbe necessaryinallapplications.However iftheoperatingfrequencyisbeingsynchronizedbelow the nominalfrequency,C9 isrecommended. Althoughitisnotrequiredforstability,C9 isveryhelpfulinsuppressing noise. A phase leadcapacitorcan alsobe added toincreasethephase and gainmargins.The phase leadcapacitoris most helpfulforhighinputvoltageapplicationsorwhen synchronizingtoa frequencygreaterthannominal.This capacitor,shown as C10 in Figure24, shouldbe placedin parallelwiththe top feedbackresistor,R1. C10 introducesan additionalzero and poleto the compensationnetwork.These frequenciescan be calculatedas shown below: (21) Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM26001B

Vfbfpff = fzff x Vout LM26001B SNVS491B –MAY 2007–REVISED APRIL 2013 www.ti.com (22) A phase leadcapacitorwillboostloopphase aroundtheregionofthezerofrequency,fzff.fzffshouldbe placed somewhat belowthefpz1frequencysetby C9. However,ifC10 istoolarge,itwillhave no effect. PCB Layout Good board layoutiscriticalforswitchingregulatorssuch as theLM26001B. First,theground planearea must be sufficientforthermaldissipationpurposes,and second,appropriateguidelinesmust be followedtoreducethe effectsofswitchingnoise. Switchmode convertersare veryfastswitchingdevices.In such devices,the rapidincreaseof inputcurrent combined withparasitictraceinductancegeneratesunwanted Ldi/dtnoisespikesattheSW node and alsoatthe VIN node. The magnitudeof thisnoisetendsto increaseas the outputcurrentincreases.Thisparasiticspike noisemay turnintoelectromagneticinterference(EMI),and can alsocause problemsindeviceperformance. Therefore,caremust be takeninlayouttominimizetheeffectofthisswitchingnoise. The currentsensingcircuitincurrentmode devicescan be easilyaffectedby switchingnoise.Thisnoisecan cause dutycyclejitterwhichleadstoincreasedspectralnoise.AlthoughtheLM26001B has 100ns blankingtime atthebeginningofeverycycletoignorethisnoise,some noisemay remainaftertheblankingtime.Followingthe importantguidelinesbelowwillhelpminimizeswitchingnoiseand itseffecton currentsensing. The switchnode area shouldbe as smallas possible.The catchdiode,inputcapacitors,and outputcapacitors shouldbe groundedtoa largegroundplane,withthebulkinputcapacitorgroundedas closeas possibletothe catchdiodeanode.Additionally,thegroundareabetween thecatchdiodeand bulkinputcapacitorisverynoisy and shouldbe somewhat isolatedfromtherestofthegroundplane. A ceramicinputcapacitormust be connectedas closeas possibletotheVIN pinand groundedclosetotheGND pin.Oftenthiscapacitorismost easilylocatedon thebottomsideofthepcb.IfplacementclosetotheGND pin isnotpractical,theceramicinputcapacitorcan alsobe grounded closetothecatchdiodeground.The above layoutrecommendationsareillustratedbelowinFigure25. Figure25. Example PCB Layout Itisa good practicetoconnecttheEP, GND pin,and smallsignalcomponents (COMP, FB, FREQ) toa separate ground plane,shown inFigure25 as EP GND, and inthe schematicsas a signalground symbol.Both the exposed pad and theGND pinmust be connectedtoground.Thisquieterplaneshouldbe connectedtothehigh currentground plane at a quietlocation,preferablynear the Vout ground as shown by the dashed linein Figure25. The EP GND planeshouldbe made as largeas possible,sinceitisalsoused forthermaldissipation.Several viascan be placeddirectlybelow the EP to increaseheat flowto otherlayerswhen theyare available.The recommended viaholediameteris0.3mm. The tracefromtheFB pintotheresistordividershouldbe shortand theentirefeedbacktracemust be keptaway fromtheinductorand switchnode.See ApplicationNote AN-1229 formore informationregardingPCB layoutfor switchingregulators.

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Psw AC = Vin x Iload x fsw xVin x 10-9 1.33© LM26001B www.ti.com SNVS491B –MAY 2007–REVISED APRIL 2013 Thermal Considerationsand TSD AlthoughtheLM26001B has a builtincurrentlimit,atambienttemperaturesabove 80°C, devicetemperaturerise may limitthe actualmaximum load current.Therefore,temperaturerisemust be taken intoconsiderationto determinethemaximum allowableloadcurrent. Temperatureriseisa functionofthepower dissipationwithinthedevice.The followingequationscan be used to calculatepower dissipation(PD) and temperaturerise,where totalPD isthesum ofFET switchinglosses,FET DC losses,drivelosses,Iq,and VBIAS losses: PD TOTAL = Psw AC + Psw DC + PQG + PIq + PVBIAS (23) (24) Psw DC = D x Iload2 x (0.2+ 0.00065x (Tj-25)) (25) PQG = Vinx 4.6x 10-9 x fsw (26) PIq = Vinx Iq (27) PVBIAS = Vbiasx IVBIAS (28) Giventhistotalpower dissipation,junctiontemperaturecan be calculatedas follows: Tj= Ta + (PDTOTAL x θJA) where

θJA=38°C/W (typically)when usinga multi-layerboardwitha largecopperplanearea (29) θJA varieswithboardtypeand metallizationarea. To calculatethemaximum allowablepower dissipation,assume Tj= 125°C. To ensurethatjunctiontemperature does notexceed themaximum operatingratingof125°C, power dissipationshouldbe verifiedatthemaximum expectedoperatingfrequency,maximum ambienttemperature,and minimum and maximum inputvoltage.The calculatedmaximum load currentisbased on continuousoperationand may be exceeded duringtransient conditions. Ifthe power dissipationremainsabove the maximum allowablelevel,devicetemperaturewillcontinueto rise. When the junctiontemperatureexceeds itsmaximum, the LM26001B engages Thermal Shut Down (TSD).In TSD, thepartremainsina shutdown stateuntilthejunctiontemperaturefallstowithinnormaloperatinglimits.At thispoint,thedevicerestartsinsoft-startmode. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM26001B

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REVISION HISTORY

Changes from RevisionA (April2013)toRevisionB Page

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www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LM26001BMH/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L26001 BMH LM26001BMHX/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L26001 BMH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM26001BMHX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 Pack Materials-Page 2

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