LM26001B NSC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
Features
■ High efficiency sleep mode ■ 40 µA typical Iq in sleep mode ■ 10 µA typical Iq in shutdown mode ■ 3.0V minimum input voltage ■ 4.0V to 18V continuous input range ■ 2.0% reference accuracy ■ Cycle-by-cycle current limit ■ Adjustable Frequency (150 kHz to 500 kHz) ■ Synchronizable to an external clock ■ Power Good Flag ■ Forced PWM function ■ Adjustable Soft-start ■ TSSOP-16 exposed pad package ■ Thermal Shut Down
Applications
■ Automotive Telematics ■ Navigation systems ■ In-Dash Instrumentation ■ Battery Powered Applications ■ Stand-by power for home gateways/set-top boxes Typical Application Circuit 30001901 © 2008 National Semiconductor Corporation 300019 www.national.com LM26001B 1.5A Switching Regulator with High Efficiency Sleep Mode
16-Lead Exposed Pad TSSOP Package
Ordering Information
Order Number Package Type Package Drawing Supplied As LM26001BMH TSSOP-16EXP MXA16A 92 Units of Rail LM26001BMHX TSSOP-16EXP MXA16A 2500 Units of Tape and Reel Pin Descriptions Pin # Pin Name Description
1 VIN Power supply input
2 VIN Power supply input
3 PGOOD Power Good pin. An open drain output which goes high when the output voltage is greater than 92% of nominal. 4 EN Enable is an analog level input pin. When pulled below 0.8V, the device enters shutdown mode. 5 SS Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time. 6 COMP Compensation pin. Connect to a resistor capacitor pair to compensate the control loop. 7 FB Feedback pin. Connect to a resistor divider between Vout and GND to set output voltage.
8 GND Ground
9 FREQ Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency. 10 FPWM FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation is disabled. 11 SYNC Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be pulled low for non-synchronized operation. 12 VBIAS Connect to an external 3V or greater supply to bypass the internal regulator for improved efficiency. If not used, VBIAS should be tied to GND. 13 VDD The output of the internal regulator. Bypass with a minimum 1.0 µF capacitor. 14 BOOT Bootstrap capacitor pin. Connect a 0.1µF minimum ceramic capacitor from this pin to SW to generate the gate drive bootstrap voltage. 15 SW Switch pin. The source of the internal N-channel switch. 16 SW Switch pin. The source of the internal N-channel switch. EP EP Exposed Pad thermal connection. Connect to GND. www.national.com 2 LM26001B
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltages from the indicated pins to GND: VIN -0.3V to 20V SW (Note 7) -0.5V to 20V VDD -0.3V to 7V VBIAS -0.3V to 10V FB -0.3V to 6V BOOT SW-0.3V to SW+7V PGOOD -0.3V to 7V FREQ -0.3V to 7V SYNC -0.3V to 7V EN -0.3V to 20V FPWM -0.3V to 7V SS -0.3V to 7V Storage Temperature -65°C to +150°C Power Dissipation (Note 2) 2.6 W Recommended Lead Temperature Vapor Phase (70s) 215°C Infrared (15s) 220°C ESD Susceptibility (Note 3) Machine Model 200V Human Body Model 2KV Charged Device Model 1kV Operating Ratings (Note 1) Operating Junction Temp. −40°C to 125°C Supply Voltage (Note 4) 3.0V to 18V Electrical Characteristics Specifications in standard type are for TJ = 25°C only, and limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Unless otherwise stated, Vin=12V. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. (Note 5) Symbol Parameter Conditions Min Typ Max Unit System ISD (Note 6) Shutdown Current EN = 0V 10.8 20 µA Iq_Sleep_VB (Note 6) Quiescent Current Sleep mode, VBIAS = 5V 38 70 µA Iq_Sleep_VDD Quiescent Current Sleep mode, VBIAS = GND 75 125 µA Iq_PWM_VB Quiescent Current PWM mode, VBIAS = 5V 150 230 µA Iq_PWM_VDD Quiescent Current PWM mode, VBIAS = GND 0.65 0.85 mA IBIAS_Sleep (Note 6) Bias Current Sleep mode, VBIAS = 5V 33 85 µA IBIAS_PWM Bias Current PWM mode, VBIAS = 5V 0.5 0.70 mA VFB Feedback Voltage 5V < Vin < 18V 1.2093 1.234 1.2589 V IFB FB Bias Current ±200 nA ΔVOUT/ΔVIN Vout Line Regulation 5V < Vin < 18V 0.001 %/V ΔVOUT/ΔIOUT Vout Load Regulation 0.8V < VCOMP < 1.15V 0.07 % VDD VDD Output Voltage 7V < Vin < 18V, IVDD= 0 mA to 5 mA 5.50 5.95 6.50 V ISS_Source Soft-Start Source Current 1.5 2.2 4.6 µA Vbias_th VBIAS On Voltage Specified at IBIAS = 92.5% of full value 2.64 2.9 3.07 V Switching RDS(ON) Switch On Resistance Isw = 1A 0.12 0.2 0.42 Ω Isw_off Switch Off State Leakage Current Vin = 18V, VSW = 0V 0.002 5.0 µA fsw Switching Frequency RFREQ = 62k, 124k, 240k ±10 % VFREQ FREQ Voltage 1.0 V fSW range Switching Frequency Range 150 500 kHz VSYNC Sync Pin Threshold SYNC rising 1.2 1.6 V SYNC falling 0.8 1.1 Sync Pin Hysteresis 114 mV ISYNC SYNC Leakage Current 6 nA FSYNC_UP Upper frequency synchronization range As compared to nominal fSW +30 % 3 www.national.com LM26001B
Symbol Parameter Conditions Min Typ Max Unit FSYNC_DN Lower frequency synchronization range As compared to nominal fSW -20 % TOFFMIN Minimum Off-time 365 ns TONMIN Minimum On-time 155 ns THSLEEP_HYS Sleep Mode Threshold Hysteresis VFB rising, % of THWAKE 101.2 % THWAKE Wake Up Threshold Measured at falling FB, COMP = 0.6V 1.234 V IBOOT BOOT Pin Leakage Current BOOT = 16V, SW = 10V 0.0006 5.0 µA Protection ILIMPK Peak Current Limit 1.80 2.5 3.25 A VFB_SC Short Circuit Frequency Foldback Threshold Measured at FB falling 0.87 V F_min_sc Min Frequency in Foldback VFB < 0.3V 71 kHz VTH_PGOOD Power Good Threshold Measured at FB, PGOOD rising 89 92 95 % PGOOD Hysteresis 2 7 8 % IPGOOD_HI PGOOD Leakage Current PGOOD = 5V 0.2 nA RDS_PGOOD PGOOD On Resistance PGOOD sink current = 500 µA 64 Ω VUVLO Under-Voltage Lock-Out Threshold Vin falling , shutdown, VDD = VIN 2.60 2.9 3.20 V Vin rising, soft-start, VDD = VIN 3.60 3.9 4.20 TSD Thermal Shutdown Threshold 160 °C θJA Thermal Resistance Power dissipation = 1W, 0 lfpm air flow 38 °C/W Logic VthEN Enable Threshold voltage 0.8 1.2 1.4 V Enable Hysteresis 120 mV IEN_Source EN Source Current EN = 0V 4.5 µA VTH_FPWM FPWM Threshold 0.8 1.2 1.6 V IFPWM FPWM Leakage Current FPWM = 5V 35 nA EA gm Error Amp Trans-Conductance 400 670 1000 µmho ICOMP COMP Source Current VCOMP = 0.9V 56 µA COMP Sink Current VCOMP = 0.9V 56 µA VCOMP COMP Pin Voltage Range 0.64 1.27 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX - TA) /θJA. The maximum power dissipation of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. The charged device model is per JESD22-C101-C. Note 4: Below 4.0V input, power dissipation may increase due to increased RDS(ON). Therefore, a minimum input voltage of 4.0V is required to operate continuously within specification. A minimum of 3.9V (typical) is also required for startup. Note 5: All room temperature limits are 100% production tested. All limits at temperature extremes are guaranteed through correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 6: Iq and ISD specify the current into the VIN pin. IBIAS is the current into the VBIAS pin when the VBIAS voltage is greater than 3V. All quiescent current specifications apply to non-switching operation. Note 7: The absolute maximum specification applies to DC voltage. An extended negative voltage limit of -2V applies for a pulse of up to 1µs, and -1V for a pulse of up to 20µs. www.national.com 4 LM26001B
Typical Performance Characteristics Unless otherwise specified the following conditions apply: Vin = 12V, TJ = 25°C. VFB vs Temperature 30001903 VFB vs Vin (IDC = 300 mA) 30001905 IQ and IVBIAS vs Temperature (Sleep Mode) 30001904 IQ and IVBIAS vs Temperature (PWM Mode) 30001906 Normalized Switching Frequency vs Temperature (300kHz) 30001916 UVLO Threshold vs Temperature (VDD = VIN) 30001917 5 www.national.com LM26001B
Peak Current Limit vs Temperature 30001915 Short Circuit Foldback Frequency vs VFB (325 kHz nominal) 30001912 Efficiency vs Load Current (330kHz) 30001908 Efficiency vs Load Current (500kHz) 30001909 Startup Waveforms 30001910 Load Transient Response 30001952 www.national.com 6 LM26001B
Nominal VOUT = 5V 30001953 7 www.national.com LM26001B
www.national.com 8 LM26001B
discontinuous operation waveforms are shown below. FIGURE 4. Discontinuous Mode Waveforms operation. When open, EN will be pulled up to VIN. minimum 1µF ceramic capacitor placed directly at the pin. cycle corresponds to a reduction in output voltage. at the leading edge for increased immunity to switching noise.
For example, at a maximum load of 1.5A and a ripple content of 33%, peak inductor current is equal to 1.75A which is safely below the minimum current limit of 1.80A. By increasing the inductor size, ripple content and peak inductor current are lowered, which increases the current limit margin. The size of the output inductor can also be determined using the desired output ripple voltage, Vrip. The equation to deter- mine the minimum inductance value based on Vrip is as follows: Where Re is the ESR of the output capacitors, and Vrip is a peak-to-peak value. This equation assumes that the output capacitors have some amount of ESR. It does not apply to ceramic output capacitors. If this method is used, ripple content should still be verified to be less than 40%. OUTPUT CAPACITOR The primary criterion for selecting an output capacitor is equivalent series resistance, or ESR. ESR (Re) can be selected based on the requirements for out- put ripple voltage and transient response. Once an inductor value has been selected, ripple voltage can be calculated for a given Re using the equation above for Lmin. Lower ESR values result in lower output ripple. Re can also be calculated from the following equation: Where ΔVt is the allowed voltage excursion during a load transient, and ΔIt is the maximum expected load transient. If the total ESR is too high, the load transient requirement cannot be met, no matter how large the output capacitance. If the ESR criteria for ripple voltage and transient excursion cannot be met, more capacitors should be used in parallel. For non-ceramic capacitors, the minimum output capacitance is of secondary importance, and is determined only by the load transient requirement. If there is not enough capacitance, the output voltage excur- sion will exceed the maximum allowed value even if the maximum ESR requirement is met. The minimum capaci- tance is calculated as follows: It is assumed the total ESR, Re, is no greater than Re MAX. Also, it is assumed that L has already been selected. Generally speaking, the output capacitance requirement de- creases with Re, ΔIt, and L. A typical value greater than 100 µF works well for most applications. INPUT CAPACITOR In a switching converter, very fast switching pulse currents are drawn from the input rail. Therefore, input capacitors are required to reduce noise, EMI, and ripple at the input to the LM26001B. Capacitors must be selected that can handle both the maximum ripple RMS current at highest ambient temper- ature as well as the maximum input voltage. The equation for calculating the RMS input ripple current is shown below: For noise suppression, a ceramic capacitor in the range of 1.0 µF to 10 µF should be placed as close as possible to the VIN pin. A larger, high ESR input capacitor should also be used. This capacitor is recommended for damping input voltage spikes during power on and for holding up the input voltage during transients. In low input voltage applications, line transients may fall below the UVLO threshold if there is not enough input capacitance. Both tantalum and electrolytic type capacitors are suitable for the bulk capacitor. However, large tantalums may not be available for high input voltages and their working voltage must be derated by at least 2X. BOOTSTRAP The drive voltage for the internal switch is supplied via the BOOT pin. This pin must be connected to a ceramic capacitor, Cboot, from the switch node, shown as C4 in the typical ap- plication. The LM26001B provides the VDD voltage internally, so no external diode is needed. A minimum value of 0.1 uF is recommended for Cboot. Smaller values may result in insuf- ficient hold up time for the drive voltage and increased power dissipation. During low Vin operation, when the on-time is extended, the bootstrap capacitor is at risk of discharging. If the Cboot ca- pacitor is discharged below approximately 2.5V, the LM26001B enters a high frequency re-charge mode. The Cboot cap is re-charged via the LG synchronous FET shown in the block diagram. Switching returns to normal when the Cboot cap has been recharged. CATCH DIODE When the internal switch is off, output current flows through the catch diode. Alternately, when the switch is on, the diode sees a reverse voltage equal to Vin. Therefore, the important parameters for selecting the catch diode are peak current and peak inverse voltage. The average current through the diode is given by: IDAVE = Iload x (1-D) Where D is the duty cycle, defined as Vout/Vin. The catch diode conducts the largest currents during the lowest duty cycle. Therefore IDAVE should be calculated assuming maxi- mum input voltage. The diode should be rated to handle this current continuously. For over-current or short circuit condi- tions, the catch diode should be rated to handle peak currents equal to the peak current limit. The peak inverse voltage rating of the diode must be greater than maximum input voltage. A Schottky diode must be used. It's low forward voltage max- imizes efficiency and BOOT voltage, while also protecting the SW pin against large negative voltage spikes 13 www.national.com LM26001B
point. Bandwidth increases with increasing values of R5.
- Next, place a zero (fzc) near fp using C8. C8 can be de-
but too high a value will slow the transient response time. response, but lower phase margin.
- A second pole (fpc1) can also be placed at fz. This pole can
stability, C9 is very helpful in suppressing noise. too large, it will have no effect. to minimize the effect of this switching noise. what isolated from the rest of the ground plane. possible to the VIN pin and grounded close to the GND pin. illustrated below in Figure 11. FIGURE 11. Example PCB Layout the dashed line in Figure 11.
Thermal Considerations and TSD Although the LM26001B has a built in current limit, at ambient temperatures above 80°C, device temperature rise may limit the actual maximum load current. Therefore, temperature rise must be taken into consideration to determine the maximum allowable load current. Temperature rise is a function of the power dissipation within the device. The following equations can be used to calculate power dissipation (PD) and temperature rise, where total PD is the sum of FET switching losses, FET DC losses, drive losses, Iq, and VBIAS losses: PDTOTAL = PswAC + PswDC + PQG + PIq + PVBIAS PswDC = D x Iload2 x (0.2 + 0.00065 x (Tj - 25)) PQG = Vin x 4.6 x 10-9 x fsw PIq = Vin x Iq PVBIAS = Vbias x IVBIAS Given this total power dissipation, junction temperature can be calculated as follows: Tj = Ta + (PDTOTAL x θJA) Where θJA=38°C/W (typically) when using a multi-layer board with a large copper plane area. θJA varies with board type and metallization area. To calculate the maximum allowable power dissipation, as- sume Tj = 125°C. To ensure that junction temperature does not exceed the maximum operating rating of 125°C, power dissipation should be verified at the maximum expected op- erating frequency, maximum ambient temperature, and min- imum and maximum input voltage. The calculated maximum load current is based on continuous operation and may be exceeded during transient conditions. If the power dissipation remains above the maximum allow- able level, device temperature will continue to rise. When the junction temperature exceeds its maximum, the LM26001B engages Thermal Shut Down (TSD). In TSD, the part remains in a shutdown state until the junction temperature falls to with- in normal operating limits. At this point, the device restarts in soft-start mode. www.national.com 16 LM26001B
Physical Dimensions inches (millimeters) unless otherwise noted eTSSOP-16 Package 16-Lead Exposed Pad TSSOP Package 17 www.national.com LM26001B
LM26001B 1.5A Switching Regulator with High Efficiency Sleep Mode For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2008 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: support@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Technical Support Center Email: europe.support@nsc.com German Tel: +49 (0) 180 5010 771 English Tel: +44 (0) 870 850 4288 National Semiconductor Asia Pacific Technical Support Center Email: ap.support@nsc.com National Semiconductor Japan Technical Support Center Email: jpn.feedback@nsc.com www.national.com